JPH10209435A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a gate electrode from peeling off due to stress for improved mechanical strength, by forming a side etching part at an opening part comprising a multi-layer structure of SiO2 and SiN layer, for incorporation of the gate electrode. SOLUTION: With a wet processing with buffered hydrofluoric acid, only an SiO2 layer 7 is selectively etched in horizontal direction to form a side etching part 14. Then by a CVD method wherein particle's sticking factor is very small wile excellent in creeping characteristics, a film-formation for a gate electrode is performed, so that Wsi and W may infiltrate inside the side etching part 14, thereby filling up an opening part. Further, a gate electrode 10 is shaped by reactive dry etching. With this method, the gate electrode 10 infiltrates in the side etching part 14, so peeling-off caused by stress is prevented, thus degradation in element characteristics is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using a compound semiconductor such as GaAs or AlGaAs and a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, a MESFET using GaAs is used.
(Metal-semiconductor field effect transistor) or AlGaAs
HJFET (heterojunction field effect transistor) using the same or the like, in order to obtain high reliability of the device characteristics,
In many cases, a heat-resistant metal such as Si is used as a gate material.
By using a heat-resistant WSi gate, good Schottky characteristics can be maintained even at a relatively high temperature of about 500 ° C. or higher. For this reason, the ohmic electrodes of the source and drain can be formed after the gate is formed, so that the process width can be expanded, and even if the high output operation is performed for a long time, the problem such as deterioration of the current value does not occur. There are advantages.

On the other hand, since WSi is a material having a relatively high resistance (specific resistance value: 100 to 200 μΩ · cm), WSi is required to reduce the resistance of the gate electrode and improve the device characteristics.
A method of forming another low-resistance metal on Si to form a multilayer structure is used. Conventionally, as the above metal material,
A having a relatively small specific resistance of about 10 μΩ · cm
Precious metals such as u and Pt have often been used.

On the other hand, with the recent miniaturization and high performance of elements, the dry etching process has become the mainstream from the conventional lift-off method as a gate forming method. However, in order to dry Au, Pt or the like, ion etching is required. It is necessary to perform physical processing using the collision energy of ions using a milling method, and as a result, chips such as Au and Pt are likely to be generated. These chips cause a short circuit between wirings, a malfunction of the transistor, and the like, thereby lowering the element yield. Therefore, the generation of the chips should be avoided as much as possible.

[0005] Therefore, instead of Au or Pt, W, which can be dry-etched by a chemical effect and has excellent adhesion to WSi, has been used as the metal material. A method for manufacturing a semiconductor device using such a gate configuration is disclosed, for example, in Japanese Patent Application No. 6-222585 filed by the present applicant. The manufacturing process of this conventional example is shown in FIGS.

[0006] First, as shown in FIG.
An undoped high-purity GaAs buffer layer 42 and an Si-doped n-type AlGsAs electron supply layer 4 on an As substrate 41
3. The Si-doped n-type GaAs contact layer 44 is epitaxially grown in sequence using the well-known molecular beam epitaxy (MBE) method. In FIG. 15, reference numeral 45 denotes a two-dimensional electron gas.

Next, as shown in FIG. 16, a gate insulating film 46 made of SiO _{2 is} formed on the n-type GaAs contact layer 4.
4 on top.

Next, as shown in FIG. 17, BCl ₃ /
Electron cyclotron resonance (EC) using SF ₆ gas
R) GaAs / AlGaAs by plasma etching
An opening 47 is formed by performing selective dry etching to selectively remove the low-resistance GaAs layer.

Next, as shown in FIG.
SiO ₂ is grown on the side wall of the substrate and anisotropically etched by RIE using CF ₄ gas to form a side wall film 48.

[0010] Next, as shown in FIG.
WF ₆ to be the gate electrode 49 and W for lowering the resistance are formed on the inner surface of the substrate.

Next, as shown in FIG. 20, a source electrode 50 and a drain electrode 51 are formed by photolithography.
Patterning, lift-off method and about 400 ° C
AuGeNi is alloyed with the n-type GaAs contact layer 44 by heat treatment to form a low-resistance ohmic junction to form the source electrode 50 and the drain electrode 51. Thus, the field effect transistor shown in FIG. 20 is manufactured.

In JP-A-61-120476, as shown in FIG. 21, a gate electrode 62 is provided between a source electrode 60 and a drain electrode 61, and the gate electrode 62 is formed of a semi-insulating GaAs substrate. Openings 6 of insulating films 65 and 66 formed in drain ion implantation layer 64 on
7 embedded. Opening 67 of insulating films 65 and 66
A groove 68 is formed in the side wall of the gate electrode 62, and a part of the gate electrode 62 enters the groove 68.

[0013]

[Problems to be Solved by the Invention] Japanese Patent Application No. 6-22258
In the conventional example disclosed in No. 5, W usually has a relatively large compressive stress (about 1 × 10 ¹⁰ dyn / cm ² ). Therefore, when the film thickness is increased to reduce the gate resistance, the thickness of the gate electrode is reduced. In some cases, the end portions are peeled off from the semiconductor to deteriorate the characteristics of the device.

In the conventional example disclosed in Japanese Patent Application Laid-Open No. 61-120476, a part of the gate electrode enters a groove formed on the side wall of the opening of the insulating film.
Although a gate electrode having high mechanical strength against stress can be formed, it is difficult to form a groove in a desired shape. Therefore, it is difficult to prevent peeling due to the stress of the gate electrode with good reproducibility using the structure of the conventional example.

An object of the present invention is to provide a semiconductor device capable of forming a side-etched portion having good reproducibility in an opening of a gate electrode and obtaining a gate electrode having high mechanical strength, and a method of manufacturing the same. And

[0016]

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device having an opening for burying a gate electrode, the opening has a multilayer structure of a SiO ₂ layer and a SiN layer, and has a side etching portion formed by selectively etching the SiO ₂ layer in a substantially horizontal direction. In addition, the gate electrode enters the side-etched portion.

According to the present invention, a side-etched portion is formed in an opening for burying a gate electrode, and the gate electrode enters the side-etched portion by a film forming method having a good burying property such as a CVD method. Can be prevented from being peeled off due to the stress.

The opening has a multilayer structure of a SiO ₂ layer and a SiN layer, and the side etching portion of the opening has
Since the SiO ₂ layer is formed by selectively etching in a substantially horizontal direction, a side-etched portion with good reproducibility can be formed.

The opening may be formed such that the SiO ₂ layer is disposed between the SiN layers, and the side-etched portion may be formed at a predetermined distance from the bottom surface of the opening.
In this case, since the gate length does not increase by providing the side etching portion in the gate portion, it is particularly effective for manufacturing a field effect transistor requiring a short gate length.

According to the method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device having an opening for burying a gate electrode, (1) forming an opening with a multilayer structure of a SiO ₂ layer and a SiN layer; 2) a step of selectively etching the SiO ₂ layer in a substantially horizontal direction to form a side-etched portion, and (3) a step of forming a gate electrode so as to enter the side-etched portion. Is what you do.

The side etching portion may be formed by a wet etching process or a dry etching process.

Further, an opening may be formed so that the SiO ₂ layer is disposed between the SiN layers, and the side etching portion may be formed at a position separated from the bottom surface of the opening by a predetermined distance.

[0023]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. The manufacturing steps of the first embodiment of the present invention will be described in order with reference to FIGS.

First, as shown in FIG.
undoped high-purity Ga having a thickness of 600 nm
As buffer layer 2, 40 nm thick, Si doped (Nd
= 2 × 10 ¹⁸ cm ⁻³ ) n-type AlGsAs electron supply layer 3, 80 nm thick and Si-doped (Nd = 3.5 × 10 ¹⁸⁾
cm) of the n-type GaAs contact layer 4 is epitaxially grown in sequence using the well-known molecular beam epitaxy (MBE) method. The Al composition of the n-type AlGaAs electron supply layer 3 is set to 0.2. In FIG. 1, reference numeral 5 denotes a two-dimensional electron gas.

Next, as shown in FIG. 2, electron cyclotron resonance (ECR) is performed using the photoresist 6 as a mask.
GaAs / AlGaAs selective dry etching is performed by plasma etching to selectively remove the low-resistance GaAs layer 4 to form an opening 13. The gas type and gas flow rate were BCl ₃ (4 SCCM) / SF ₆ (1.5 SCCM), the plasma gas pressure was 4 mTorr, and the microwave power was 1
00W.

[0026] Then, as shown in FIG. 3, SiO ₂ (2
Two silicon oxide (Si) layers 7 and SiN (silicon nitride) layers 8 are formed in this order by a CVD method. SiO ₂ layer 7 and SiN
The thickness of the layer 8 is 50 nm (SiO ₂ ) and 50 nm, respectively.
0 nm (SiN).

Next, as shown in FIG.
With the mask 9 as the mask₆Parallel using gas plasma
SiN / S by flat reactive dry etching
iO _TwoThe layer film is processed vertically. SF₆Gas flow rate is 50 SCCM
Gas pressure is 10mTorr, RF bias power is 50W
You. The opening width is about 0.5 μm.

Next, as shown in FIG. 5, by performing a wet process with buffered hydrofluoric acid (BHF), only the SiO ₂ layer 7 is selectively etched in the horizontal direction to form a side etching portion 14. . The amount of side etching is determined by the etching time, and 100 n
m. In this case, the dimension ratio between the vertical (film thickness) and the horizontal (side etch distance) of the side etching portion 14 is 1: 2.

Next, after removing the photoresist mask by organic washing, a gate electrode is formed by a CVD method. First, using WF ₆ and SiH ₄ gas, the substrate temperature 3
At 50 ° C., a WSi film is formed to a thickness of 100 nm. The gas flow rates were 10 SCCM (WF ₆ ) and 120 SCCM (Si
H ₄ ), the total gas pressure is 20 Torr. Subsequently, at a substrate temperature of 400 ° C., W is deposited to a thickness of 500 nm using a combination of WF ₆ , H ₂ and Ar gas. The gas flow rates were 20 SCCM (WF ₆ ), 200 SCCM (H ₂ ),
000 SCCM (Ar). The total gas pressure is 30 To
rr. Since the CVD method has an extremely small particle adhesion coefficient and excellent wraparound property, WSi and W enter the inside of the side etching portion 14 and the opening is completely filled.

Next, as shown in FIG. 6, the gate electrode 10 is shaped by reactive dry etching using a photoresist as a mask. Gas type and flow rate are SF ₆
(10 SCCM), the plasma pressure is 7 mTorr.

Next, as shown in FIG. 7, the source electrode 11 and the drain electrode 12 are patterned by a photolithographic method, an AuGeNi film is vacuum deposited, and the source electrode 11 and the drain electrode 12 are shaped by a lift-off method.

Finally, AuGeNi and the n-type GaAs contact layer 4 are alloyed in an H ₂ (hydrogen) atmosphere at about 400 ° C. to form a low-resistance ohmic junction to form a source electrode 11 and a drain electrode 12. I do. As described above, the field effect transistor shown in FIG. 7 is manufactured.

According to the present invention, the side etching portion 14 is formed in the opening 13 in which the gate electrode 10 is buried, and the gate electrode 10 enters the side etching portion 14 by a film forming method having a good burying property such as a CVD method. Therefore, peeling of the gate electrode 10 due to stress can be prevented. As a result, deterioration of device characteristics can be prevented, and a high-performance field-effect transistor can be produced at a high yield.

The opening 13 is formed by the SiO ₂ layer 7 and the SiN
Since the side etching portion 14 of the opening is formed by selectively etching the SiO ₂ layer 7 in a substantially horizontal direction, the side etching portion 14 with good reproducibility can be formed. .

Next, the manufacturing steps of the second embodiment of the present invention will be described in order with reference to FIGS.

First, as shown in FIG.
Undoped high-purity G having a thickness of 600 nm on the s substrate 21
aAs buffer layer 22, 40 nm thick Si-doped (Nd = 2 × 10 ¹⁸ cm ⁻³ ) n-type AlGaAs electron supply layer 23, 80 nm thick Si-doped (Nd = 3.5 ×
An n-type GaAs contact layer 24 of 10 ¹⁸ cm ^-3 ) is epitaxially grown in sequence using a well-known molecular beam epitaxy (MBE) method. n-type AlGaAs electron supply layer 23
Has an Al composition of 0.2. In FIG. 8, reference numeral 25 denotes a two-dimensional electron gas.

Next, as shown in FIG. 9, using the photoresist 26 as a mask, GaAs / AlGaAs selective dry etching is performed to selectively remove the low-resistance GaAs layer to form an opening 27. The gas type and gas flow rate were BCl ₃ (4 SCCM) / SF ₆ (1.5 SCCM),
The plasma gas pressure is 4 mTorr.

Next, as shown in FIG.
8, the SiO ₂ layer 29 and the SiN layer 30
Three layers are formed by the method D. The film thickness is 100 nm each.
(SiN) / 50 nm (SiO ₂ ) / 500 nm (Si
N).

Then, as shown in FIG. 11, using the photoresist 31 as a mask, SiN / SiO ₂ 2 is formed by parallel plate dry etching using SF ₆ gas plasma.
The layer film is processed vertically. The SF ₆ gas flow rate was 50 SCCM, the gas pressure was 10 mTorr, and the RF bias power was 50 W.
The opening width is 0.8 μm.

Next, as shown in FIG. 12, CF ₄ (4
By reactive dry etching using a mixed gas plasma of fluorocarbon and CO (carbon monoxide), Si
Only the SiO ₂ layer 29 disposed between the N layers 28 and 30 is selectively etched in the horizontal direction to form a side etching portion 32. The gas flow rates of CF ₄ and CO were 40 SCCM and 160 SCCM, respectively, the gas pressure was 50 mTorr,
The RF bias power is 500 mW. The amount of side etching is determined by the etching time, and is adjusted to be 150 nm. In this case, the side etching portion 3
The dimensional ratio between the length (film thickness) and the width (side etch distance) of No. 2 is 1: 3.

Next, after removing the photoresist 31 by organic washing, a gate electrode is formed by a CVD method. First, WF ₆ (tungsten hexafluoride) and SiH
_{4 Using} (silane) gas at a substrate temperature of 350 ° C, WS
i is deposited to a thickness of 100 nm. Gas flow rate is 10
SCCM (WF ₆ ) and 120 SCCM (SiH ₄ ), total gas pressure is 20 Torr. Subsequent substrate temperature is 400 ° C
A film of W is formed to a thickness of 500 nm using a combination of WF ₆ , H ₂ and Ar (argon) gas. The gas flow rates were 20 SCCM (WF ₆ ), 200 SCCM (H ₂ ),
0 SCCM (Ar). Further, the total gas flow rate is 30 Torr.

Next, as shown in FIG. 13, the gate electrode 33 is shaped by reactive dry etching using a photoresist as a mask. Gas type and flow rate are SF
₆ (10 SCCM), the plasma pressure is 30 mTorr.

Next, the source electrode 34 and the drain electrode 35 are patterned by a photolithographic method, an AuGeNi film is vacuum-deposited, and the source electrode 34 and the drain electrode 35 are shaped by a lift-off method.

Finally, the AuG in an H ₂ atmosphere at about 400 ° C.
eNi and the n-type GaAs contact layer 24 are alloyed,
By forming a low-resistance ohmic junction, the source electrode 34 is formed.
And a drain electrode 35 are formed. As described above, the field effect transistor shown in FIG. 14 is manufactured.

According to the second embodiment of the present invention, since the gate length is not increased by providing the side etching portion in the gate portion, it is particularly suitable for manufacturing a field effect transistor requiring a short gate length. It is valid.

[0046]

According to the present invention, a side-etched portion is formed in an opening for burying a gate electrode, and the gate electrode enters the side-etched portion by a film forming method having a good burying property such as a CVD method. Peeling due to stress of the gate electrode can be prevented. As a result, deterioration of device characteristics can be prevented, and a high-performance field-effect transistor can be produced at a high yield.

The opening has a multilayer structure of a SiO ₂ layer and a SiN layer, and the side etching portion of the opening has
Since the SiO ₂ layer is formed by selectively etching in a substantially horizontal direction, a side-etched portion with good reproducibility can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing step according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing step of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing step of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing step according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing step according to the second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a manufacturing step according to the second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a manufacturing step of the second embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a manufacturing step according to the second embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a manufacturing step of the second embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a conventional manufacturing process.

FIG. 16 is a cross-sectional view showing a conventional manufacturing process.

FIG. 17 is a cross-sectional view showing a conventional manufacturing process.

FIG. 18 is a cross-sectional view showing a conventional manufacturing process.

FIG. 19 is a cross-sectional view showing a conventional manufacturing process.

FIG. 20 is a cross-sectional view showing a conventional manufacturing process.

FIG. 21 is a sectional view showing another conventional semiconductor device.

[Explanation of symbols]

1: semi-insulating GaAs substrate 2: high-purity GaAs buffer layer 3: n-type AlGaAs electron supply layer 4: n-type GaAs contact layer 5: two-dimensional electron gas 6: photoresist 7: SiO ₂ layer 8: SiN layer 9: Photoresist 10: Gate electrode 11: Source electrode 12: Drain electrode 13: Opening 14: Side etching part

Claims (6)

[Claims] In a semiconductor device having an opening for burying a gate electrode, the opening has a multilayer structure of an SiO ₂ layer and a SiN layer, and is formed by selectively etching the SiO ₂ layer in a substantially horizontal direction. A semiconductor device having a side-etched portion, wherein the gate electrode enters the side-etched portion. 2. The method according to claim 1, wherein the opening is formed such that the SiO ₂ layer is disposed between the SiN layers, and the side etching part is formed at a position separated from the bottom surface of the opening by a predetermined distance. 2. The semiconductor device according to claim 1, wherein: 3. A method of manufacturing a semiconductor device having an opening for burying a gate electrode, wherein:
A step of forming a multilayer structure of _two layers and a SiN layer;
(2) a step of selectively etching the SiO ₂ layer in a substantially horizontal direction to form a side etching portion; and (3) a step of forming the gate electrode so as to enter the side etching portion. A method for manufacturing a semiconductor device, comprising: 4. The method according to claim 3, wherein said side etching portion is formed by a wet etching process. 5. The method according to claim 3, wherein the side etching portion is formed by a dry etching process. 6. The method according to claim 1, wherein the opening is formed so that the SiO ₂ layer is disposed between the SiN layers, and the side etching portion is formed at a position separated from the bottom surface of the opening by a predetermined distance. Item 6. The method for manufacturing a semiconductor device according to any one of Items 3 to 5.