JP2655490B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device using a compound semiconductor, and more particularly to a method of manufacturing a compound semiconductor field effect transistor.

[0002]

2. Description of the Related Art In a field effect transistor using a compound semiconductor such as GaAs, a method is known in which a gate is formed by opening an insulating film above a conductive layer and a carrier supply layer and depositing an electrode metal in the opening. Widely used.

In order to improve the characteristics of these field effect transistors, it is desirable to reduce the gate resistance Rg as much as possible. However, Rg is easily influenced by the buried shape of the gate electrode, and when the burying property is poor, Rg tends to increase. On the other hand, with the recent miniaturization of elements,
The aspect ratio (depth / minimum dimension of the uppermost portion) of such a gate opening becomes large, and as a result, the embeddability of the gate metal is easily affected.

As a method of manufacturing this type of semiconductor device, for example, there is a method described in Japanese Patent Application Laid-Open No. Hei 5-335341 (conventional example). Next, this conventional example will be described.

First, as shown in FIG. 5A, on a semi-insulating GaAs substrate 1, a channel layer 2 composed of a high-purity GaAs layer, an electron supply layer 3 composed of an N-type Al _0.3 Ga _0.7 As layer, and A semiconductor substrate is prepared by sequentially epitaxially growing a contact layer 4 made of an N-type GaAs layer. next,
After element isolation by hydrogen ion implantation or the like, an SiON film 19 and an Al ₂ O ₃ film 15 are grown in this order, and then the resist film is patterned by photolithography, and then the Al ₂ O 3 is phosphoric acid. _After removing the _three layers 20, anisotropically etching the SiON film 19 by reactive ion etching (RIE) using CF ₄ gas, and then removing the resist film, the opening 2 is removed.
Form one.

Next, as shown in FIG. 5B, a 150 nm thick SiON film 22 is deposited by a plasma CVD method.

Next, as shown in FIG. 5C, the SiON film 22 is etched by RIE using CF ₄ gas to leave a sidewall insulating film 23 only on the sidewall of the contact hole (opening 21).

Next, as shown in FIG. 5D, a pattern of a photoresist film 24 having an opening slightly wider than the contact hole (21) is formed.

Next, for example, R using CCl ₂ F ₂ gas
After selectively etching the N-type GaAs layer (4) in the contact hole by IE, the photoresist film 24 is formed.
Is removed to form an opening 25 as shown in FIG. Etching is performed using N-type Al _0.3 Ga _0.7
Almost all of the surface of the As layer 3 stops.

Next, a gate electrode 19 is formed. First, as shown in FIG. 6B, a tungsten silicide film 8 is deposited to a thickness of about 300 nm by a sputtering method, and then a photoresist is applied to form a T-type gate electrode, followed by predetermined patterning. A photoresist film 25 is formed.

Next, after performing anisotropic dry etching of the tungsten silicide film 8 by RIE using CF ₄ gas, the photoresist film 25 is removed.
The gate electrode 26 is completed as shown in FIG. As described above, the gate structure in which the insulating film deposited on the semiconductor substrate is opened, the contact layer 4 having a low resistance is removed by etching, and then the gate metal is buried in the opening, has a parasitic resistance between the source and the gate. Since it is suitable for manufacturing an FET having a large transconductance value by reducing Rs,
This is a widely used structure.

After that, as shown in FIG. 6D, a source electrode 16 and a drain electrode 15 are formed to complete the device.

[0013]

When a gate metal is deposited by making a gate opening as in the above-described conventional example, defective filling of the metal tends to occur. In this conventional gate opening method, for example, a gate length Lg = 0.4 μm, an N-type GaAs layer (contact layer) thickness 0.1 μm, SiO
When the thickness of the film 19 is 0.3 μm, the aspect ratio (depth / width) of the gate opening is 1.0. For example, a tungsten silicide film is formed in an opening having such a shape in a thickness of 0.1 mm.
When deposited by a 4 μm-thick sputtering method, the opening 25 cannot be completely filled with tungsten silicide.

In this case, the thickness at the bottom portion of the opening 25 of the tungsten silicide film is 0.15 μm, and the thickness deposited on the inner wall portion is 0.1 μm at the lowermost portion, and the thickness increases toward the upper portion. There is a gap. In the field portion outside the opening, the tungsten silicide film has a thickness of 0.4 μm. The size of the gap is such that the width of the bottom surface is 0.2 μm and the depth is 0.8 μm, and the width decreases toward the top, and the width at the top is 0.05 μm. The aspect ratio (depth / top width) of the gap is 16.0.

The reason why the gate metal is not sufficiently buried is that as the sputtering proceeds, the metal deposited in the opening gradually narrows the entrance of the opening, and the deposition efficiency at the bottom of the opening decreases. Eventually, the entrance narrows without leaving a gap, and a gap is formed in the gate electrode.

It is considered that such poor filling of the gate metal is more likely to occur as the gate length is reduced and the aspect ratio of the gate opening is increased.

If the gate electrode has a gap as described above, the cross-sectional area of the gate electrode is reduced, so that there is a problem that the resistance Rg in the gate width direction increases.

Further, when there is a gap in the gate electrode, the mechanical strength is weakened, and the gate electrode is likely to peel off due to external factors such as mechanical vibration.

From the above viewpoint, it is important to improve the burying property of the gate.

Since various studies have been made on a technique for forming an electrode wiring in a contact hole with a good burying property in a silicon semiconductor device, it is conceivable to solve the above-mentioned problem by using such a technique. For example, a technique described in JP-A-63-51659 can be mentioned. That is, as shown in FIG. 7A, a flat silicon substrate 101 has a thickness of about 1 μm.
After the silicon oxide film 102 is deposited by the CVD method, an opening (contact hole) 103 having a diameter of 1 μm is formed by a normal photoresist process and a dry etching process.

Next, as shown in FIG. 7B, under the condition that the substrate temperature is 350 ° C., the degree of vacuum is 7 mTorr, and the flow rate of the tungsten hexafluoride gas to the flow rate of the hydrogen gas is 1:70, mixing of hydrogen of tungsten hexafluoride is performed. A tungsten film 104 is deposited to a thickness of about 0.5 μm only on the bottom surface of the contact hole where Si is exposed on the substrate by a low pressure CVD method using a gas.

Next, as shown in FIG. 7C, the aluminum target power is 1.0 kW, the substrate bias voltage is -6.
Under a condition of 00 V and an argon pressure of 3 mTorr, an aluminum film 105 is further deposited by about 0.5 μm by a via sputtering method. Under this condition, the thickness of the aluminum film 105 deposited on the bottom of the contact hole 103 is twice the thickness of the aluminum film deposited on the silicon oxide film 102, and the aluminum film on the silicon oxide film having the contact hole 103 is It becomes almost flat.

When this method is applied to the production of a GaAs FET, it cannot be used because the adhesion between tungsten and GaAs is low and the gate easily peels off.

Also, there is a method described in Japanese Patent Application Laid-Open No. 3-14333. This is because, as shown in FIG.
For example, a silicon oxide film 202 is formed on a substrate 201 of i or the like by a CVD method, a contact hole having an aspect ratio of 1.2 is opened, and then a thickness of about 50 nm is maintained while the temperature of the substrate 201 is kept below 450 ° C. Aluminum film 2
05A is formed. In this vapor deposition, the film is formed at a low temperature.
1 is suppressed, and a uniform aluminum film is formed.

Next, while this substrate is heated to 450 to 600 ° C., Al is vacuum-deposited to a thickness of about 5 mm.
FIG. 8 (b) further shows a 0 nm aluminum film 205A.
As shown in FIG. 7, a thick aluminum film 205B of about 750 nm is formed. At this time, unlike the case where heating is performed from the beginning of film formation, a uniform aluminum film 205A
Is present, island growth does not occur in the upper aluminum film 205B, and uniform growth is continued. In addition, since the substrate is deposited at a high temperature of 450 to 600 ° C., Al surface diffusion is active, so that Al uniformly flows into the contact holes, and filling without voids is achieved.

When the present invention is applied to the production of a GaAs FET, it cannot be used because Al and GaAs undergo remarkable mutual diffusion in the step of depositing Al while maintaining the substrate temperature at 450 ° C. or higher, which tends to cause characteristic deterioration.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a gate electrode with good embedding in an opening of an insulating film covering a compound semiconductor layer.

[0028]

According to a method of manufacturing a semiconductor device of the present invention, an insulating film is provided by covering a compound semiconductor layer on a surface portion of a semiconductor substrate, and the compound semiconductor layer penetrates the insulating film and is formed on a bottom surface. Providing a first opening to be exposed; depositing a first conductive film to a predetermined thickness on a portion including the first opening and the vicinity thereof; applying and solidifying a low-viscosity material; Forming a flattening film, performing etch-back by means capable of being selective with respect to the insulating film and removing the first conductive film at least at a speed substantially equal to that of the flattening film; Forming a second opening by filling a part of the first opening by reducing the aspect ratio by leaving the first conductive film only and removing the planarization film; A film is deposited on the portion including the second opening and its vicinity, and It is that a step of forming a gate electrode in contact with said compound semiconductor layer at a bottom of said first opening by grayed.

The compound semiconductor layer is a multilayer film including the uppermost contact layer, a carrier supply layer and a channel layer, and the first conductive film forms a Schottky barrier with the carrier supply layer or the channel layer. be able to.

Further, the contact layer is an N-type GaAs layer, the electron supply layer is an N-type Al _x Ga _{1 -x} As layer (0 <x <1),
The channel layer can be a high-purity GaAs layer, and the first conductive film can be a tungsten silicide film.

As the flattening film, any one of a resist film, a polyimide film and an SOG film can be used.

[0032]

After depositing the first conductive film to such a thickness that the upper portion of the first opening is not covered, a flattening film is formed and etched back to form a second opening having a small aspect ratio, and then the second opening is formed. Since the conductive film is deposited, the opening can be sufficiently filled with the conductive film without voids.

[0033]

Embodiments of the present invention will be described with reference to the drawings.

First, an embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG.
A 500 nm undoped high-purity GaAs layer (channel layer 2) on the surface ((100) plane) of the aAs substrate body 1, a 35 nm thick Si-doped (Nd = 2 × 10 ¹⁸ cm ⁻³ ) N
Type Al _0.3 Ga _0.7 As layer (electron supply layer 3), and 100 nm thick with Si doping (Nd = 3 × 10 ¹⁸ cm ⁻³ )
The N-type GaAs layer (contact layer 4) is grown epitaxially (substrate temperature is 600 ° C.) by metal organic chemical vapor deposition (MOCVD). By selectively implanting, for example, hydrogen ions into the semiconductor substrate prepared in this manner, an element isolation region (not shown) is formed, and an FET formation region (for example, a region having a rectangular planar shape) is partitioned.

Next, as shown in FIG. 1B, a silicon oxide film 6 is deposited on the entire surface by thermal CVD to a thickness of 300 nm, and then a gate electrode is formed by lithography and reactive dry etching (RIE). The silicon oxide film 6 at the portion to be formed is removed, and the N-type GaAs layer (4) is further removed by anisotropic selective dry etching, as shown in FIG. . For this anisotropic selective dry etching, for example, an EC using a mixed gas of BCl ₃ (boron trichloride) and SF ₆ (sulfur hexafluoride) is used.
This is performed by R (electron cyclotron resonance) plasma etching. Gas pressure is 1.3 Pa, microwave power is 1
It was set to 50W. Thus, the etching can be stopped when the surface of the N-type Al _0.5 Ga _0.7 As layer (3) is exposed due to the displacement of the N-type GaAs layer (4).

The dimensions of the first opening 7 thus formed are 0.4 μm in width and 0.4 μm in depth, and the aspect ratio (depth / width) is 1.0. Fig. 1
As shown in (d), the tungsten silicide film 8A (WS
ix, x is approximately 2) by sputtering. The thickness is 400 nm. When the sputtering is completed, a gap is formed in the embedded portion as shown in FIG. The thickness of the tungsten silicide film 8A at the bottom portion of the first opening 7 is 0.15 μm, the thickness at the inner wall portion is 0.1 μm at the lowermost portion, and the thickness increases toward the upper portion. In the field portion outside the opening, tungsten silicide film 8A has a thickness of 0.4 μm. The dimensions of the gap are such that the bottom has a width of 0.2 μm and a depth of 0.8 μm, and the gap is closer to the top, and the width is 0.05 μm at the top.
The aspect ratio of the gap (depth / width at the top) is 16.0
It is.

Next, as shown in FIG. 2A, a photoresist film is formed as a flattening film by applying a photoresist and performing baking. Any material other than the photoresist can be used as long as the material has a viscosity small enough to sufficiently enter the gap remaining in the first opening, and the flattening film can be a polyimide film or an SOG film.

Next, the photoresist film 9 and the tungsten silicide film 8A are etched back by dry etching (FIG. 2B). For the etch back, a reactive dry etching method using SF ₆ gas is used. The applied voltage is 0.1 kW and the gas pressure is 0.13 Pa. As a result, the etching selectivity to the silicon oxide film 6, the photoresist film, and the tungsten silicide film 8A is about 1: 2: 5. Etchback is performed for the time required to remove the tungsten silicide film in the first opening by 0.2 μm after the entire tungsten silicide film 8A (0.4 μm in thickness) in the field portion is removed. The thickness of the silicon oxide film 6 eroded by this etch-back is as small as about 0.04 μm, and there is no problem in device fabrication. Similarly, the photoresist film has a thickness of 0.2
Although it is shifted by 4 μm, there is no problem from the viewpoint of protecting the tungsten silicide film at the bottom of the opening from etch back.
When a polyimide film or an SOG film is used instead of the photoresist film, the etching selectivity slightly changes, but is basically the same.

After the etch-back, a tungsten silicide film remains below the first opening, the thickness of which is 0.2 μm at the end, and a depression at the center. The dimensions of the depression are 0.2 μm in width at the bottom and 0.05 μ in depth.
m, the width of the uppermost part is 0.19 μm, and the aspect ratio (depth / width of the uppermost part) is 0.26 compared with the gap formed in the first opening by the tungsten silicide film before the etch back. It is much smaller and the gap width at the top is 3.8 times wider. Since tungsten silicide is removed from the upper part of the opening, the width is 0.4 μm, the depth is 0.2 μm, and the aspect ratio is as small as 0.5.

Thereafter, the photoresist film remaining in the first opening is removed by a process such as organic cleaning, thereby completing the formation of the second opening having a small aspect ratio. Next, a tungsten film 11 is formed by a sputtering method with a thickness of 600 nm (FIG. 2C). Tungsten is sputtered into the second opening 10 having an aspect ratio smaller than that during sputtering of tungsten silicide by etching back using a photoresist, so that the second opening is sufficiently filled with a tungsten film. Thereafter, a photoresist film 12 is formed by a lithographic method, and the tungsten film 11a is shaped by a reactive ion etching method into a shape extending 0.3 μm laterally from the opening (FIG. 2D).

Next, as shown in FIG. 3, openings 13 and 14 are formed on the N-type GaAs layer 4 by photolithography, and an Au-Ge-Ni film is formed on the source electrode by vacuum evaporation and lift-off. 15 and the drain electrode 16 are shaped. Finally, in a H ₂ atmosphere at about 400 ° C.,
u-Ge-Ni film and N-type GaAs film (contact layer 4)
Are alloyed to form a low-resistance ohmic junction to form a source electrode 15 and a drain electrode 16.

In the field-effect transistor according to the present embodiment, the gate length Lg = 0.4 μm and the depth of the first opening is 0.36 μm, but the value of the gate electrode resistance Rg is set to a tungsten silicide film (thickness 0). .4 μm) and 400 ± 5 obtained when a tungsten film (thickness: 0.6 μm) is sequentially deposited in the first opening in this order in the conventional manner.
From 0 Ω / mm, 18
The average value was reduced to 220 Ω / mm, that is, 0 ± 20 Ω / mm, and the variation was greatly improved. Also, the peeling of the electrode metal due to the poor embedding property did not occur. As a result, the manufacturing yield was significantly improved.

In this embodiment, instead of forming the tungsten film 11, a titanium nitride film having a thickness of 100 nm may be formed, and then a gold film having a thickness of 400 may be formed. Others are the same as the one embodiment. Then,
As shown in FIG. 4, the tungsten silicide film 8Aa,
A gate electrode composed of the titanium nitride film 17 and the gold film 18 can be formed. The titanium nitride film 17 is a barrier film for preventing the diffusion of gold. According to the prior art, such 3
Layer structure (0.4μm thick tungsten silicide film,
When a gate electrode (formed of a 0.1 μm thick titanium film and a 0.4 μm thick gold film) is formed, the gate electrode resistance becomes 1
According to the present invention, it is 50 ± 20 Ω / mm, and according to the present invention, it is 70 ± 10 Ω / mm, which is 70 Ω / m on average.
m and the variation is greatly improved. Also, the peeling of the electrode metal due to the poor embedding property did not occur. As a result, the manufacturing yield was significantly improved.

In the above description, after the first opening 7 is formed, similarly to the conventional example described with reference to FIG. 5, at least the side surface of the contact layer is covered, and the side wall insulating film is formed. A silicide film may be formed.
Further, it is clear that the vertical relationship between the electron supply layer and the channel layer may be reversed, and the present invention is not limited to such a heterojunction FET but may be applied to a normal MESFET.

Further, as the kind of the compound semiconductor, G
Not limited to aAs and AlGaAs, InP and InGaAs
Other compound semiconductors can also be used.

Alternatively, a semiconductor substrate obtained by epitaxially growing a compound semiconductor layer on a Si semiconductor substrate can be used.

[0048]

According to the method of manufacturing a semiconductor device of the present invention, after depositing a first conductive film in a first opening above a semiconductor substrate, filling a gap at a central portion of a low-viscosity material, Since the entire surface is etched back to cut the first conductive film, reduce the aspect ratio of the gap, and then deposit the second conductive film, the gate electrode is formed by lithographic method. A gate electrode without voids can be manufactured, the value of the gate electrode resistance Rg can be greatly reduced, and the variation can be greatly improved. Further, the peeling of the gate electrode due to the poor filling property does not occur. As a result, the characteristics of the field effect transistor are improved, and the production yield is significantly improved.

[Brief description of the drawings]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (a) to FIG.
It is a process order sectional view divided and shown to (d).

FIG. 2 is a cross-sectional view in the order of steps, which is separated from (a) to (d) following FIG. 1;

FIG. 3 is a cross-sectional view shown after FIG. 2;

FIG. 4 is a cross-sectional view for explaining a modification of the embodiment.

FIGS. 5A to 5D are cross-sectional views in the order of steps, which are separately illustrated in FIGS.

FIG. 6 is a cross-sectional view in the order of steps, which is separated from (a) to (d) following FIG. 5;

FIGS. 7A to 7C are cross-sectional views in the order of steps, which are separately illustrated in FIGS.

FIGS. 8A and 8B are sectional views in the order of steps shown in FIGS. 8A and 8B for explaining a second related art of the related art.

[Explanation of symbols]

Reference Signs List 1 semi-insulating GaAs substrate 2 channel layer 3 electron supply layer 4 contact layer 5 two-dimensional electron gas 6 silicon oxide film 7 first opening 8, 8A, 8Aa tungsten silicide film 9, 9A photoresist film 10 second opening 11 , 11a tungsten film 12 a photoresist film 13 opening 14 opening 15 source electrode 16 drain electrode 17 titanium nitride film 18 gold film 19 SiON film 20 Al ₂ O ₃ film 21 opening 22 SiON film 23 sidewall insulating film 24 a photoresist film 25 an opening 26 Gate electrode 101, 201 Silicon substrate 102, 201 Silicon oxide film 103 Opening 104 Tungsten film 105, 205A, 205B Aluminum film

Claims (4)

(57) [Claims] A step of providing an insulating film by covering a compound semiconductor layer on a surface portion of a semiconductor substrate, and providing a first opening which penetrates the insulating film and exposes the compound semiconductor layer on a bottom surface;
A first conductive film is deposited to a predetermined thickness in a portion including the first opening and the vicinity thereof, and a low-viscosity material is applied and solidified to form a flattened film having a substantially flat surface. Etch-back by means capable of selectively removing the first conductive film at least at the same speed as the planarizing film, and leaving the first conductive film only in the first opening; Removing a planarizing film to fill a part of the first opening to reduce an aspect ratio to form a second opening; and forming a second conductive film between the second opening and its vicinity. Forming a gate electrode in contact with the compound semiconductor layer on the bottom surface of the first opening by depositing and patterning a portion containing the compound semiconductor layer. 2. The compound semiconductor layer is a multilayer film including an uppermost contact layer, a carrier supply layer, and a channel layer, and the first conductive film forms a Schottky barrier with the carrier supply layer or the channel layer. Item 2. A method for manufacturing a semiconductor device according to Item 1. Wherein the contact layer is N-type GaAs layer, the electron supply layer is N-type Al _x Ga _1-x As layer (0 <x <1), the channel layer is high purity GaAs layer, a first conductive film of tungsten 3. The method according to claim 2, wherein the method is a silicide film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein said planarizing film is a resist film, a polyimide film or an SOG film.