JP3362723B2 - Method for manufacturing field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a method for manufacturing a field effect transistor having a fine gate electrode using a compound semiconductor material.

[0002]

2. Description of the Related Art A field effect transistor (hereinafter referred to as FET) made of GaAs or the like as a semiconductor material is used in a microwave band or the like, and the cutoff frequency of the FET is proportional to the mobility of carriers and the gate length. Since it is inversely proportional to the square of, it is important to shorten the gate length for speeding up.

A technique for shortening the gate length of an FET using GaAs or the like as a semiconductor material is disclosed in Japanese Patent Laid-Open No. 63-000171. FIG. 6 is a sectional view of an essential part of the substrate for explaining the steps of the method for manufacturing an FET according to this technique. First, as shown in FIG. 6A, an active layer 72 made of a non-doped GaAs layer and a contact layer 73 made of a laminated film of an n-type AlGaAs layer and an n-type GaAs layer are sequentially formed on a semi-insulating substrate 71 made of GaAs or the like. After the epitaxial growth, an insulating film 74 such as a SiON layer is further deposited by the plasma CVD method or the like.

A gate pattern is formed on the insulating film 74 with the photoresist 30, and the insulating film 74 is dry-etched using the resist as a mask to form an opening 75.

Next, as shown in FIG. 6B, a Ti layer 76a, a Pt layer 76b, and an Au layer 76c are sequentially formed as a gate electrode layer by vapor deposition or the like, and then patterned by ion milling and dry etching to form a gate. The electrode 76 is formed. Next, as shown in FIG. 6C, the resist 77 is patterned, and the insulating film 74 on both sides of the gate electrode 76 is etched with a plasma gas such as NF3 using this as a mask. By this etching, Ti on the side surface of the gate electrode 76
The layer 76a is also etched, and the gate length is the Ti layer 76a.
It will be reduced by twice the thickness of a.

Next, as shown in FIG. 6D, Au, Ni,
A source / drain electrode 78 is formed by sequentially evaporating a metal such as AuGe and then lifting off. The gate electrode 76 is also covered with a metal film 78 'made of a laminated film of the same metal.

[0007]

In the above technique, as shown in FIG. 6 (c), when the insulating film 74 on both sides of the gate electrode 76 is etched with a plasma gas such as NF3, the side surface of the gate electrode 76 is etched. The Ti layer 76a is also etched and the gate length can be shortened by twice the thickness of the Ti layer.
The surface of 3 is easily damaged. Further, in the formation of the source / drain electrode of FIG. 6D, it is difficult to control the distance between the source / drain electrode 78 and the gate electrode 76, and there is a problem that the insulation between the source / drain electrode and the gate electrode is deteriorated. .

As a method of solving the above-mentioned problems of the prior art, a technique of forming a profile of a T-shaped gate electrode with a photoresist in advance has been proposed in Japanese Patent Laid-Open No. 298048/1992. A method of manufacturing an FET having a T-type gate electrode according to the present technology will be described with reference to FIG.

First, as shown in FIG.
An active layer 62 made of an n-type GaAs layer and a contact layer 63 made of an n ⁺ -type GaAs layer are formed on a semi-insulating substrate 61 made of, for example, MOCVD (Metal Organic Chemical Vapor Deposition).
position) method or MBE (Molecular Beam Epitaxy) method and the like, and a predetermined pattern is formed by a photoresist 30 or the like on the surface of the wafer sequentially formed by the epitaxial growth method. 64 is formed. Next, as shown in FIG. 5B, after the photoresist 30 is removed, an EB resist 65 that is exposed to an electron beam is applied, and then the EB resist 65 in the recess 64 is exposed by the electron beam 12.
Part of is removed by exposure and development to form the opening 66. The opening 66 has a stripe shape, and its size is the same as the gate size of the FET to be created.
The length (horizontal direction in FIG. 5 (b)) is about 0.05 μm to 0.3 μm, and the width (vertical direction to the paper surface in FIG. 5 (b)) is about 100 to 500 μm, although it varies depending on the use of T. Is. Thereafter, as shown in FIG. 5C, a photoresist 30a is applied, and this is exposed and developed to be patterned. The pattern of the photoresist 30a is formed so as to include the pattern of the EB resist 65 previously formed. As a result, a T-shaped resist opening 67 as shown in FIG. 5C is formed. Using the two-layer resist pattern thus formed, the gate electrode 68 is formed as shown in FIG. The gate electrode 68 is formed by vapor deposition and lift-off of a metal film which is an electrode material. As the material of the gate electrode 68, a material that forms a Schottky junction with the active layer 62 is used. As an example, FIG.
In (d), a laminated metal of Ti and Al is used for the gate electrode.

After that, a protective insulating film 69 is formed by the CVD method, and the protective insulating film 69 on the contact layers 63 on both sides of the gate electrode 68 is removed by using a predetermined pattern as shown in FIG. 5 (e). The opening is formed and the ohmic electrode 7 is formed.
After forming 0, the FET is completed through a wiring process.

In this technique, deterioration of the surfaces of the contact layer 63 and the active layer 62 at the time of forming the gate electrode 68 is prevented, but there are the following problems. That is, when forming the gate electrode 68, a fine lithography process using the EB resist 65 and the photoresist 30a and a lift-off process using the same as a mask are used, which complicates the manufacturing process. Further, in the lift-off process, since the metal film for electrodes is deposited by the vacuum evaporation method, the electrode formation position is offset with respect to the resist opening pattern particularly in the peripheral portion of the wafer as the diameter of the wafer becomes larger, and the outer peripheral side of the wafer is offset. Will shift to. Along with this, metal is also vapor-deposited on the side surface of the resist opening portion, and burrs and metal pieces are generated at the time of lift-off, causing problems such as short circuit between electrodes of the FET and reduction in gate breakdown voltage.

An object of the present invention is to provide a simple method for manufacturing an FET having a fine gate electrode, which solves the above problems of the prior art.

[0013]

A first structure of a method for manufacturing an FET according to the present invention is such that an active layer made of a first conductivity type compound semiconductor layer and a contact layer are sequentially formed on a semi-insulating substrate made of a compound semiconductor material. and epitaxially growing, reforming the steps of forming a recess reaching said active layer by etching the predetermined portions of the contact layer, by exposure to active species and the active layer surface within the recess of the contact layer surface The compound semiconductor nitride layer or phosphorus
Forming a surface modification layer composed of an oxide layer, irradiating the surface modification layer surface in the recess with an electron beam to form a first opening reaching the active layer, and Growing a columnar lower gate electrode having the first opening shape from the surface of the active layer of the opening; depositing an insulating film on the substrate including the recess, flattening the insulating film, and Exposing the upper end of the lower gate electrode, depositing a first metal film on the substrate including the upper end of the lower gate electrode, patterning the first metal film, and connecting to the upper end of the lower gate electrode; A second upper gate electrode is formed, and the insulating layer outside the recess on both sides of the upper gate electrode reaches the contact layer.
Forming the opening, and then depositing a second metal film in the second opening to form an ohmic electrode.

In the first structure of the present invention, after the surface modification layer is formed, the surface modification layer is further heat-treated before forming the first opening in the surface modification layer. During surface modification, free arsenic deposited near the interface between the surface modified layer and the active layer is removed. As a result, it is possible to reduce the influence of the fluctuation of the drain current (gate lag) during the FET operation due to the charge / discharge of the charge trap derived from free arsenic.

A second structure of the method of manufacturing an FET of the present invention comprises a step of sequentially epitaxially growing an active layer and a contact layer made of a first conductivity type compound semiconductor layer on a semi-insulating substrate made of a compound semiconductor material, Etching a predetermined portion of the contact layer to form a recess reaching the active layer; depositing a silicon layer on the substrate including the recess; and exposing the entire silicon layer to active species. forming a silicon nitride layer and quality, forming a first opening reaching the active layer by irradiating an electron beam to the silicon nitride layer in the recess, the active of the first opening A step of growing the lower gate electrode having the opening shape in a column shape from the layer surface to a height exceeding the height of the silicon nitride layer surface outside the recess,
Depositing an insulating film on the substrate including the recess, flattening the insulating film, and exposing an upper end portion of the lower gate electrode; and, on the substrate including the upper end portion of the lower gate electrode. After depositing a first metal film, patterning the first metal film to form an upper gate electrode connected to the upper end of the lower gate electrode; and forming an upper insulating film on both sides of the upper gate electrode outside the recess. Forming a second opening reaching the contact layer, and then depositing a second metal film in the second opening to form an ohmic electrode.

In the above-mentioned second structure of the present invention, in order to form the surface modification layer, a semiconductor layer (silicon layer) of a different type from the semiconductor substrate is epitaxially grown and modified to modify the surface. Form the layers. Thereby, the insulating property of the surface modified layer can be further improved.

In the first and second configurations of the present invention described above, a structure is formed in which the lower gate electrode is embedded in the active layer by forming the first opening so as to reach the inside of the active layer. Therefore, the interface between the surface modification layer and the insulating film and the current channel of the FET are separated from each other. As a result, it is possible to reduce the influence of drain current fluctuation (gate lag) during FET operation due to charge / discharge of charge traps existing at the interface between the surface modification layer and the insulating film.

[0018] The first nitride layer as the surface-modified layer in the configuration of the above-mentioned present invention, were or can be used phosphide layer,
A nitride layer can be used as the surface modification layer in the second configuration of the present invention.

In the first and second configurations of the present invention described above, as a method of flattening the insulating film and exposing the upper end portion of the lower gate electrode, a photoresist is applied onto the insulating film, A method of flattening the insulating film by etching the photoresist and the insulating film under the same etching rate condition and thinning the insulating film to expose the upper end portion of the lower gate electrode. Can be used.

In the method of manufacturing a compound semiconductor field effect transistor according to the present invention, the surface of a semiconductor substrate is modified to form a surface modification layer, and the surface modification layer is etched by an electron beam to expose the surface of the active layer. Then, the lower gate electrode can be selectively grown on the surface of the active layer using the surface modification layer as a mask,
A transistor with a short gate length can be easily created.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

1A to 1D are sectional views in order of steps for explaining a first embodiment of a method for manufacturing a field effect transistor (FET) according to the present invention. First, as shown in FIG. 1A, an active layer 2 made of an n-type GaAs layer having a thickness of about 200 nm and a thickness of about 100 nm are formed on a semi-insulating substrate 1 made of GaAs having a thickness of about 600 μm. A predetermined pattern is formed by a photoresist 30 or the like on the surface of the wafer in which the contact layer 3 made of an n ⁺ type GaAs layer or the like is sequentially laminated,
Using this as a mask, the contact layer 3 is etched to form a recess 4. As a method of forming a laminated structure, it is general to use epitaxial growth using MOCVD or MBE method for each layer.

Next, after removing the photoresist 30,
The surface of the wafer is exposed to the active species 11 and modified to form the surface modified layer 5. As an example, the case where the GaN surface modification layer is formed by nitrogen active species will be described below. Any gas species may be used as a source of nitrogen active species as long as it contains nitrogen as a constituent element. Examples of gases widely used in semiconductor processes include nitrogen (N ₂ ) gas and ammonia (N ₂ ) gas.
H ₃ ) and the like. Also, regarding the gas decomposition method, any method may be used as long as it produces active species of nitrogen,
In addition to glow discharge (plasma) and heat treatment in a gas atmosphere containing nitrogen, tungsten (W) and alumina (Al
It is possible to utilize a catalytic cracking reaction using ₂ O ₃ ) as a catalyst. As the nitriding temperature, a temperature (about 600 ° C. or lower) at which the GaAs crystal does not decompose is used. In the catalytic decomposition reaction by the catalytic body, the nitriding temperature can be lowered as compared with the plasma treatment, so that the damage to the wafer can be further reduced and the surface modification can be performed.

The optimum process conditions for nitriding are the shape of the device and the true
Varies depending on the vacancy and gas type, for example N₂Use gas
In this case, when the surface modification is performed by plasma treatment, N₂
Partial pressure 10^-Four-10^-2Torr, substrate temperature 250 ° C to 40
When modifying at 0 ° C for about 10 minutes or by heat treatment
Is N₂Partial pressure 10^-Five-10^-FourTorr, substrate temperature 500
About 10 minutes at ℃ ~ 600 ℃, catalytic decomposition by catalytic body
N if a reaction is used ₂Partial pressure 10^-Four-10^-2Tor
r, substrate temperature 250 ° C to 400 ° C, catalyst body temperature 500 ° C
The desired effect can be obtained in about 10 minutes at ~ 2000 ° C.
did it. When ammonia is used, under almost the same conditions
The desired effect can be obtained, but the substrate temperature and catalyst temperature
The lower limit is about 100 ° C lower than when using nitrogen.
Good, the condition range is further expanded.

The thickness of the surface modification layer is preferably in the range of several atomic layers to 5 nm. If it is thicker than this, processing in the next step becomes difficult, and if it is too thin, the selectivity when used as a selective growth mask in the later step is lowered.

The same effect by using a re-emission layer can be obtained in addition to the nitride layer as a surface modification layer. Further, as the reforming process for obtaining these modified layers, any of plasma treatment and heat treatment similar to nitriding and catalytic decomposition reaction by a catalyst can be used, and the process conditions are almost the same as those of nitriding. For example, in order to form an oxide layer by plasma treatment, the oxygen flow rate is 10 to 100 sccm and the pressure is 0.1.
˜1 Torr, substrate temperature 30˜200 ° C., plasma input power 10˜100 W, etc. can be used, and when forming an oxide layer by heat treatment, oxygen flow rate 100 sccm,
A substrate temperature of 300 ° C. can be used.

When the phosphide layer is formed by plasma treatment, the PH3 gas flow rate is 10 to 100 sccm,
A pressure of 0.1 to 1 Torr, a substrate temperature of 30 to 200 ° C., and an input power of 10 to 100 W can be used.
00 sccm, pressure 0.1 to 1 Torr, substrate temperature 30
The conditions of ~ 200 ° C and catalyst body temperature of 1,500 ~ 2,000 ° C can be used.

Thereafter, as shown in FIG. 1C, a part of the surface modification layer 5 in the recess 4 is removed by the electron beam 12 to form the opening 6. The opening 6 has a stripe shape, and its size is the same as the gate size of the FET to be created, and it varies depending on the use of the FET, but for example, the length (left and right direction in FIG. 1C) is 0. 05 μm to 0.3
μm, width (perpendicular to the paper surface of FIG. 1C) is 100 to 50
It is a fine pattern of about 0 μm.

Thereafter, as shown in FIG. 1D, an active layer 2 made of an n-type GaAs layer or the like in which a semiconductor or a metal is exposed at the bottom of the opening 6 is grown in the opening 6 using the surface modification layer 5 as a mask. It grows in a columnar shape as points, and the lower gate electrode 7 is selectively formed. When a semiconductor is used as the material of the lower gate electrode 7, a non-doped semiconductor or a semiconductor having a conductivity type different from that of the active layer can be used.

When a non-doped semiconductor is used, it is necessary to select a material having a band gap larger than that of the active layer in order to prevent deterioration of device characteristics due to excessive gate leak current. Non-doped AlGaAs can be used as an example of a non-doped semiconductor, and p-type GaAs or the like can be used as a material having a conductivity type different from that of the active layer. For the same reason, when a metal is used as the material of the lower gate, a material forming a Schottky junction with the active layer must be used. As a metal material for selective growth,
Tungsten (W) and tungsten silicide (WS
i) can be used.

As an example, in FIG. 1, non-doped AlG is used.
The case where aAs is used for the lower gate electrode is shown.

The lower gate electrode 7 may be formed by any method as long as it can be selectively formed in the opening using the surface modification layer as a mask, but in terms of uniformity and process speed,
Chemical vapor deposition (CVD), MOCVD and MOMB
It is convenient to use method E.

The thickness of the lower gate electrode 7 is preferably about 200 nm or more, and optimally about 500 nm.
Further, in the present embodiment, the formation of the opening 6 and the lower gate electrode 7 are performed by different devices. However, after the opening 6 is formed by irradiating an electron beam in the same device, the growth of the lower gate electrode is continued. You may go.

After that, as shown in FIG. 1 (e), an insulating film 13 is formed on the entire surface of the wafer, and a film having excellent flatness such as a photoresist is applied on the insulating film 13, and then the photoresist and the insulating film 13 are formed. The insulating film 13 is flattened and thinned by performing etching under the same etching rate to expose the upper end portion of the lower gate electrode 7. A SiO ₂ film having a thickness of about 1000 nm can be used as the insulating film 13,
The film is formed by the CVD method.

After that, a metal film is deposited on the insulating film 13,
This is processed into a predetermined pattern by an ion milling method or the like to form the upper gate electrode 8. It is desirable that the material of the upper gate electrode has a low reactivity with the lower gate electrode, such as Ti (thickness: about 20 nm) and Pt (thickness: about 20 nm).
(nm) and Au (thickness of 50 nm or more) are sequentially deposited.

After that, as shown in FIG. 1F, the insulating film 13 on the n ⁺ -type GaAs contact layer 3 on both sides of the gate electrode is removed by using a predetermined pattern to form the opening 10, and the ohmic electrode is formed. 9 is formed. After that, a field effect transistor is completed through a wiring process. As the ohmic electrode material, a Ni / AuGe laminated film or a NiGe alloy film can be used, and the opening 10 has a length of about 10 μm and a width of 100 to 500 μm. To form the opening 10, etching using a photoresist mask is used. When the insulating film is thin and the amount of etching of the insulating film necessary for forming the opening is small, it is convenient to use wet etching using hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF). If the insulating film is thick and the etching amount is large, a vertical processed shape can be obtained C
Reactive ion etching using F ₄ plasma (RI
It is preferable to use a dry etching process such as E). In addition, a lift-off process using a photoresist mask is generally used for forming the ohmic electrode, and an interface between the electrode and the semiconductor is formed by heat treatment after depositing an electrode material on the contact layer 3 made of an n ⁺ GaAs layer or the like. Used by alloying to reduce contact resistance. At this time, if the surface modification layer 5 is thick, the contact resistance between the ohmic electrode and the contact layer 3 may not be sufficiently reduced, so
At this time, if necessary, the surface modification layer 5 may be removed by acid treatment after forming the opening 10, and then the ohmic electrode may be formed.

When the gate electrode, especially the lower gate electrode is made of a metal material such as tungsten silicide and the process temperature at the time of formation is 450 ° C. or lower,
The formation of the gate electrode and the formation of the ohmic electrode can be interchanged regardless of the order of this embodiment. The order of the other steps can be changed without departing from the spirit of the present invention. In the present embodiment, a fine gate FET can be easily manufactured without using a complicated process such as a fine lithography process using an EB resist and a gate electrode formation by lift-off using the EB resist as a mask. Furthermore, since the surface modification layer 5 also functions as a passivation film on the surface of the device, the method of the present embodiment allows the gate formation and the passivation step to be carried out simultaneously, thus shortening the step. In the above-described embodiment, although using a single layer of n ⁺ GaAs contact layer, n ⁺ -type I
A layered film of nGaAs / n ⁺ type GaAs is used, and n ⁺ type I
A non-alloy metal ohmic electrode may be formed on nGaAs.

Next, a second embodiment of the FET manufacturing method of the present invention will be described with reference to the drawings. 2A to 2D are cross-sectional views in order of the steps, for explaining the second embodiment of the method for manufacturing the field effect transistor of the present invention.

Referring to FIG. 2, after the steps (FIGS. 2 (a) to 2 (b)) similar to those of the first embodiment described above, a surface modification layer 5 is formed, and then an electron beam is formed. After forming the opening 6 by 12, the step of forming the second recess 21 by etching the active layer 2 using the surface modification layer 5 as a mask is performed as shown in FIG. 2C. Subsequent steps (FIGS. 2D to 2F) are the same as those in the first embodiment.

In this embodiment, since the lower gate electrode 7 has a structure in which it is embedded in the active layer 2, the surface modification layer 5 is formed.
Therefore, the interface between the insulating film 13 and the current channel of the FET are separated from each other. Thereby, the surface modification layer 5 and the insulating film 13
There is a new effect that it is possible to reduce the influence of the fluctuation of the drain current (gate lag) during the FET operation due to the charging / discharging of the charge traps existing at the interface.

Next, a third embodiment of the method of manufacturing the FET of the present invention will be described. In the present embodiment, the heat treatment step is performed after the surface modification layer 5 is formed through the steps similar to those in the above-described first or second embodiment. The other element manufacturing processes are similar to those of the above-described first or second embodiment.

The purpose of the heat treatment in the present embodiment is to remove free arsenic deposited near the interface between the surface modification layer 5 and the active layer 2. Therefore, the atmosphere during the heat treatment is adjusted to the type of the surface modified layer. For example it is performed in a nitrogen or ammonia Kiri囲care when using nitride layer as a surface modification layer can be removed free arsenic without alteration of the surface modification layer. The processing time is about 10 minutes, and the substrate temperature is 300 ° C to 5 ° C.
It is about 00 ° C. Although efficient free arsenic than the heat treatment in nitrogen Motokiri <br/>囲気be subjected to heat treatment in the other radical treatment or a hydrogen atmosphere using an active species of hydrogen can be removed, in particular oxide layer in this case However, the processing time is limited to several minutes.

In the present embodiment, free arsenic deposited near the interface between the surface modification layer 5 and the active layer 2 at the time of surface modification is removed by heat treatment. As a result, there is a new effect that it is possible to reduce the influence of the fluctuation of the drain current (gate lag) during the FET operation due to the charge / discharge of the charge trap derived from free arsenic.

Next, a fourth embodiment of the FET manufacturing method of the present invention will be described with reference to the drawings. 3A to 3D are cross-sectional views in order of the steps, for explaining the fourth embodiment of the method for manufacturing the FET of the present invention. First, as shown in FIG. 3A, after the recess 4 is formed through the same steps as those in the first embodiment, the silicon layer 41 having a thickness of several atomic layers to 50 nm is formed as shown in FIG. To grow. Silicon layer 4
As the growth method of No. 1, an epitaxial growth method such as MBE or a catalytic CVD method using a tungsten catalyst,
Further, a plasma CVD method or the like can be used, but any other method can be used as long as it can deposit a thin silicon film.

[0045] Thereafter, as shown in FIG. 3 (c), <br/> Ru to the silicon layer 41 nitride turn into the same manner as in the first embodiment. For example, when nitrided, the surface modification layer 42 made of SiN is formed. The other element manufacturing processes are similar to those of the above-described first or third embodiment.

[0046] In this embodiment, the surface modification layer 42 is not a compound semiconductor, a silicon nitride layer, this is a insulation body, a leakage current between the surface modified layer and the lower gate electrode It doesn't flow at all. Therefore, there is a new effect that it is possible to obtain a field effect transistor having excellent characteristics with reduced gate leak current.

Next, a fifth embodiment of the method of manufacturing an FET of the present invention will be described with reference to the drawings. 4A to 4D are cross-sectional views in order of the process steps for explaining the fourth embodiment of the method for manufacturing the FET of the present invention. First, after forming the recess 4 through the same steps as those in the fourth embodiment,
Growing a silicon layer 41 of a few atomic layers up to 50 nm, then that turn into nitrogen the silicon layer 41 (FIG. 4 (a) ~ 4
(C)). For example, when nitrided, the surface modification layer 42 made of SiN is formed. The other element manufacturing process is similar to that of the second embodiment.

[0048] In this embodiment, the surface modification layer 42 is not a compound semiconductor, a silicon nitride layer, this is a insulation body, a leakage current between the surface modified layer and the lower gate electrode It doesn't flow at all. Therefore, a field effect transistor having excellent characteristics with reduced gate leakage current can be obtained, which is similar to the effect of the fourth embodiment described above, and further, the lower gate electrode 7 is embedded in the active layer 2. The structure described above can reduce the influence of the fluctuation of the drain current (gate lag) during the FET operation due to the charging and discharging of the charge traps existing at the interface between the surface modification layer 5 and the insulating film 13. It has the same effect as the embodiment.

[0049]

As described above, according to the present invention, the first semiconductor substrate surface in the configuration of the present invention were nitrided or to form a surface modified layer with phosphide, and etching the surface modification layer by electron beam By exposing the surface of the active layer by using the surface modified layer as a mask and selectively growing the lower gate electrode on the surface of the active layer, it is possible to easily manufacture a transistor having a short gate length.

[0050] In the second aspect of the present invention, in order to form a surface modification layer on the semiconductor substrate surface, and another type of semiconductor layer (silicon layer) epitaxially growing a semiconductor substrate, turned into nitrogen so formed The use of the surface modified layer improves the insulating property of the surface modified layer, and has the effect that a highly reliable transistor having a short gate length can be manufactured.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of steps, for explaining a first embodiment of a method for manufacturing a field effect transistor (FET) of the present invention.

2A to 2D are cross-sectional views in order of the steps, for explaining the second embodiment of the method for manufacturing the field-effect transistor (FET) of the present invention.

3A to 3D are cross-sectional views in order of the processes, for explaining a fourth embodiment of a method for manufacturing a field effect transistor (FET) of the present invention.

4A to 4C are cross-sectional views in order of the processes, for explaining a fifth embodiment of a method for manufacturing a field effect transistor (FET) of the present invention.

5A to 5D are cross-sectional views in order of the processes, for explaining an example of a method for manufacturing a conventional field effect transistor (FET).

6A to 6C are cross-sectional views in order of the processes, for explaining another example of the conventional method for manufacturing a field effect transistor (FET).

[Explanation of symbols]

1, 61, 71 substrate 2,62,72 Active layer 3,63,73 Contact layer 4,64 recesses 5,42,52 Surface modification layer 6,10,66,75 Opening 7 Lower gate electrode 8 Upper gate electrode 9,70 Ohmic electrode 11 active species 12 electron beam 13,74 insulating film 21 Second recess 30 photoresist 41,51 Silicon layer 42 Surface modification layer 65 EB resist 68,76 Gate electrode 69 Protective insulation film 76a Ti layer 76b Pt layer 76c Au layer 77 Resist 78 Source / drain electrodes 78 'metal film

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Claims (13)

(57) [Claims] 1. A step of sequentially epitaxially growing an active layer made of a compound semiconductor layer of the first conductivity type and a contact layer on a semi-insulating substrate made of a compound semiconductor material, and etching a predetermined portion of the contact layer to make the active layer active. A step of forming a recess reaching the layer, and a surface modification layer formed of a nitride layer or a phosphide layer of the compound semiconductor by modifying the surface of the active layer and the surface of the contact layer in the recess by exposing to the active species. Forming, a step of irradiating the surface of the surface modification layer in the recess with an electron beam to form a first opening reaching the active layer, and a step of forming the first opening from the surface of the active layer in the first opening. 1 to grow the lower gate electrode having the opening shape into a columnar shape, and after the insulating film is deposited on the substrate including the recess, the insulating film is planarized and the lower gate is formed. Exposing the upper end of the electrode,
Depositing a first metal film on the substrate including the upper end of the lower gate electrode, patterning the first metal film, and forming an upper gate electrode connected to the upper end of the lower gate electrode; Forming a second opening in the insulating film outside the recess on both sides of the gate electrode to reach the contact layer, and then depositing a second metal film in the second opening to form an ohmic electrode; A method of manufacturing a field effect transistor, comprising: 2. The electric field according to claim 1, further comprising heat-treating the surface modification layer after forming the surface modification layer and before forming the first opening in the surface modification layer. Method of manufacturing an effect transistor. 3. A step of sequentially epitaxially growing an active layer made of a first conductivity type compound semiconductor layer and a contact layer on a semi-insulating substrate made of a compound semiconductor material, and etching the predetermined portion of the contact layer to form the active layer. Forming a recess reaching a layer, depositing a silicon layer on the substrate including the recess, and exposing the active layer to modify the entire silicon layer to form a silicon nitride layer, Forming a first opening reaching the active layer by irradiating the silicon nitride layer in the recess with an electron beam; and the surface of the silicon nitride layer outside the recess from the surface of the active layer in the first opening. A step of growing the lower gate electrode having the opening shape in a columnar shape to a height exceeding the height of, and depositing an insulating film on the substrate including the recess, and then forming the insulating film. Planarizing and exposing the upper end of the lower gate electrode, depositing a first metal film on the substrate including the upper end of the lower gate electrode, and patterning the first metal film to form the lower gate electrode A step of forming an upper gate electrode connected to the upper end of the second opening, and forming a second opening reaching the contact layer in the insulating film outside the recess on both sides of the upper gate electrode, and then forming the second opening. And a step of depositing a second metal film therein to form an ohmic electrode therein. 4. The process for producing the first opening is any one of a field effect transistor according to claim 1 to 3, wherein a is formed so as to reach the active layer. Wherein said method of any one of the field effect transistor according to claim 1-4, wherein the semi-insulating the substrate is characterized in that it consists of GaAs. 6. The method of any one of the field-effect transistor of the active layer according to claim 1 to 5, wherein the n-type GaAs layer. 7. The contact layer is an n + type GaAs layer or the lower layer is an n + type GAs layer and the upper layer is an n + type InGaAs.
Claim 1-6 any one of a method of manufacturing a field effect transistor according to, characterized in that a laminated film of layers. 8. claims 1-7 or according one, characterized in that the use of large non-doped semiconductor or the active layer and the different conductivity type semiconductor of the band gap than the active layer as a lower gate electrode material Of manufacturing two field effect transistors. 9. The method of manufacturing a field effect transistor according to claim 8, wherein the active layer is an n-type GaAs layer, and the lower gate electrode material is non-doped AlGaAs. 10. The active layer is an n-type GaAs layer,
Claim 9, wherein the lower gate electrode material is a p-type GaAs
A method for manufacturing the field effect transistor described. 11. The active layer is an n-type GaAs layer,
Claim 1-7 any one of a method of manufacturing a field effect transistor, wherein the lower gate electrode material is tungsten (W) or tungsten silicide (WSi). 12. Ti as a material of the upper gate electrode
Claim 1-7 any one of a method of manufacturing a field effect transistor, wherein that the layer and the lower layer using a multilayer film obtained by sequentially depositing a Pt layer and an Au layer thereto. 13. The step of planarizing the insulating film and exposing the upper end portion of the lower gate electrode applies a photoresist onto the insulating film, and the photoresist and the insulating film are etched at substantially the same etching rate. any of the insulating film planarized, and the insulating film and thinning characterized by exposing the upper portion of the lower gate electrode according to claim 1 to 1 1 wherein by etching with the conditions Method of manufacturing one field effect transistor.