CN114334906A - Method for preparing overlay mark - Google Patents
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- CN114334906A CN114334906A CN202011058736.6A CN202011058736A CN114334906A CN 114334906 A CN114334906 A CN 114334906A CN 202011058736 A CN202011058736 A CN 202011058736A CN 114334906 A CN114334906 A CN 114334906A
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Abstract
The invention discloses a method for preparing an overlay mark, and belongs to the technical field of integrated circuit preparation processes. The method comprises providing a substrate with a metal layer formed thereon; patterning the metal layer to obtain an overlay mark region on the surface of the substrate; forming a mask layer on the metal layer, wherein a suspended pattern window is formed in the mask layer at a position corresponding to the overlay mark region, and the pattern window is consistent with the shape of the overlay mark to be prepared; evaporating a marking material in the overlay marking area through the pattern window by taking the mask layer as a mask; the mask layer is removed, and the marking material on the alignment marking area forms an alignment marking, so that the problems of black spots, corrosion traces and the like generated when the alignment marking is manufactured by directly evaporating noble metal Au and the like on the metal surface of an aluminum film and the like on a Wafer (Wafer) in the prior art are solved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit preparation processes, and particularly relates to a preparation method of an overlay mark.
Background
In the fabrication process of the superconducting quantum chip, an aluminum film is generally plated on a Wafer (Wafer), then photoresist is sequentially coated, exposed, developed, etched and stripped to form a control circuit, a coplanar waveguide transmission line and the like, and finally a josephson junction is formed through the processes of photoresist coating, exposure, development, evaporation, stripping and the like. In the above preparation process, as a very important link, photolithography (photolithography) transfers a Mask pattern on a Mask (Mask) to a Wafer (Wafer) through a series of steps such as alignment, exposure, and the like, and the fabrication of the superconducting quantum chip can be completed through multiple photolithography processes, even a multi-layer photolithography process.
In the patterning process, in order to achieve good performance of the chip, the lithography pattern on the wafer not only needs to have a precise feature line width size, but also needs to align the positions of the upper and lower layers of patterns by means of the Overlay mark, that is, the alignment between the positions of the current layer lithography pattern (pattern on the wafer) and the previous layer lithography pattern (pattern on the wafer) needs to meet the requirement of Overlay Accuracy. The overlay accuracy refers to the position alignment error of the photoetching patterns of the layers of the wafer, and the size of the overlay accuracy reflects the size of the position alignment deviation of the photoetching patterns among different layers.
The shape of the overlay mark is related to the equipment used for overlay, EBPG overlay often uses squares of 20 μm, JEOL6300 and laser direct write overlay often use crosses of 3 μm in width and 20 μm or more in length. At present, the method for preparing the overlay mark generally comprises the step of directly evaporating a noble metal Au and the like on the surface of a sample to prepare the overlay mark. However, the applicant finds that when an overlay mark is made on the surface of an aluminum film on a Wafer (Wafer) by depositing a noble metal Au and the like by the method, a lot of black spots and corrosion traces are generated on the aluminum film, and a byproduct is generated to pollute the surface of a sample. Therefore, the current method for preparing the overlay mark is not suitable for the preparation process of the superconducting quantum chip.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a preparation method of an overlay mark, which not only solves the problem that the surface of a sample is polluted by black spots and corrosion traces generated when the overlay mark is manufactured by evaporating marking materials such as noble metal Au on the surface of a metal layer such as an aluminum film on a Wafer (Wafer) at present.
The application provides a preparation method of an overlay mark, which comprises the following steps:
providing a substrate, wherein a metal layer is formed on the substrate;
patterning the metal layer to obtain an overlay mark region on the surface of the substrate;
forming a mask layer on the metal layer, wherein an overhanging pattern window is formed on the mask layer at a position corresponding to the overlay mark region, and the pattern window is consistent with the shape of an overlay mark to be prepared;
evaporating a marking material in the overlay marking area through the pattern window by taking the mask layer as a mask;
and removing the mask layer, wherein the marking material on the alignment marking area forms an alignment marking.
Preferably, the patterning the metal layer to obtain an overlay mark region on the surface of the substrate includes:
forming a patterned resist layer on the metal layer, the patterned resist layer having an overlay mark region pattern formed thereon;
and etching the metal layer by taking the patterned etching resistant layer as a mask to obtain an etching pattern, wherein the etching pattern comprises an alignment mark area positioned on the surface of the substrate.
The production method as described above, wherein, preferably, the patterned resist layer is further formed with a josephson junction preparation region pattern and a control wiring pattern; the etching pattern further comprises a Josephson junction preparation region and a control line on the surface of the substrate.
The production method as described above, wherein preferably, an undercut is formed between the patterned resist layer and the overlay mark region.
The manufacturing method as described above, wherein preferably, the forming a mask layer on the metal layer, the mask layer having an overhanging pattern window formed at a position corresponding to the overlay mark region, comprises:
and forming a mask layer on the patterned etching-resistant layer, wherein a pattern window is formed on the mask layer at a position corresponding to the pattern of the overlay mark region, and the pattern window is in an overhang shape relative to the overlay mark region.
The manufacturing method as described above, wherein, preferably, the removing the mask layer and the marking material on the overlay mark region form an overlay mark, includes:
removing the mask layer;
and removing the patterned anti-corrosion layer, wherein the marking material on the overlay mark area forms an overlay mark.
Preferably, the forming a mask layer on the metal layer, wherein an overhanging pattern window is formed on the mask layer at a position corresponding to the overlay mark region, and the pattern window is in accordance with the shape of the overlay mark to be prepared, and includes:
providing a mask layer, wherein the mask layer is consistent with the shape of the substrate;
forming a pattern window on the mask layer at a position corresponding to the overlay mark region, wherein the window area of the pattern window is smaller than the area of the overlay mark region, and the pattern window is consistent with the shape of the overlay mark to be prepared;
and placing the mask layer on the metal layer and enabling the overlay mark region to correspond to the overhanging pattern window.
The method for manufacturing a semiconductor device as described above, wherein preferably, a first alignment structure is formed on the substrate, a second alignment structure matched with the first alignment structure is formed on the mask layer, and the mask layer is disposed on the metal layer and has the overhanging pattern window corresponding to the overlay mark region, comprising:
placing the mask layer on the metal layer and aligning the second alignment structure and the first alignment structure such that the pattern window corresponds in position to the overlay mark region and the pattern window overhangs with respect to the overlay mark region.
The manufacturing method as described above, wherein preferably, the placing the mask layer on the metal layer and aligning the second alignment structure and the first alignment structure such that the pattern window corresponds to the overlay mark region in position and the pattern window is overhanging with respect to the overlay mark region, comprises:
providing a containing device, wherein the containing device is provided with a containing cavity, and the containing cavity comprises a third alignment structure matched with the first alignment structure and the second alignment structure;
placing the substrate in the accommodating cavity, wherein the first alignment structure is aligned with the third alignment structure;
and placing the mask layer on the metal layer, and aligning the second alignment structure with the third alignment structure so that the pattern window corresponds to the overlay mark region in position and is suspended relative to the overlay mark region.
Preferably, the evaporating a marking material through the pattern window onto the overlay mark region by using the mask layer as a mask includes:
with the mask layer as a mask, evaporating titanium on the overlay mark region through the pattern window to form an overlay mark base;
and taking the mask layer as a mask, and evaporating gold on the base part of the overlay mark through the pattern window to form the top part of the overlay mark.
Compared with the prior art, the method comprises the steps of exposing the surface of the substrate through the metal layer on the patterned substrate to obtain an overlay mark area; then forming a mask layer on the metal layer, and forming an overhanging pattern window on the mask layer at a position corresponding to the overlay mark region; then, the mask layer is used as a mask, and a marking material is evaporated on the alignment marking area by utilizing the pattern window; and finally, removing the mask layer, and forming an overlay mark by overlaying the mark material on the mark region. In the embodiment of the invention, the marking material is directly evaporated on the surface of the substrate and is gathered in the area right below the pattern window and does not adhere to or contact with the metal layer, so that the possibility of electrochemical reaction and the like between the overlay mark and the metal layer in the manufacturing process of the superconducting quantum chip is reduced, and the problems of black spots, corrosion marks and the like generated when the overlay mark is manufactured by directly evaporating noble metals such as Au and the like on the surface of the metal layer such as an aluminum film and the like on a Wafer (Wafer) in the prior art are avoided. In addition, the invention integrates the glue coating, exposing, developing, etching, removing glue process flow and the glue coating, exposing, developing, evaporating and plating marking material, removing glue process flow, which is beneficial to improving the chip preparation efficiency and shortening the chip preparation process period.
Drawings
FIG. 1 is a schematic view of a substrate according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a method for preparing an overlay mark according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram corresponding to the steps of the process shown in FIG. 2 according to an embodiment of the present invention;
fig. 4 shows (1) a schematic view of a structure of a mask layer 3 according to an embodiment of the present invention, and (2) a partially enlarged schematic view of (1);
FIG. 5 is a sectional view taken along line A-A' in FIG. 3 (c);
FIG. 6 is a schematic diagram of another structure corresponding to the steps of the process of FIG. 2 according to an embodiment of the present invention;
FIG. 7 shows (1) a sectional view taken along line B-B 'in FIG. 6 (B'), and (2) a sectional view taken along line C-C 'in FIG. 6 (C');
fig. 8 is a schematic structural diagram of a receiving device according to an embodiment of the invention.
Description of reference numerals: 1-substrate, 11-chip region, 12-first alignment structure, 2-metal layer, 21-overlay mark region, 22-josephson junction preparation region, 23-first control line, 24-second control line, 32-second alignment structure, 3-mask layer, 31-pattern window, 4-resist layer, 41-overlay mark region pattern, 42-josephson junction preparation region pattern, 43-first control line pattern, 44-second control line pattern, 5-overlay mark, 6-undercut, 7-accommodation device, 71-accommodation cavity, 72-third alignment structure, 74-clamping part.
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The overlay mark according to the embodiments of the present invention is used as a reference for pattern alignment in a patterning process of an integrated circuit manufacturing process, that is, the overlay mark enables accurate alignment of the positions of the lithography patterns generated on the substrate 1 (wafer) by multiple lithography processes. Fig. 1 is a schematic structural diagram of a substrate in an embodiment of the present invention, where the substrate 1 in the embodiment of the present invention may be a silicon wafer, a sapphire wafer, or the like, a plurality of chip regions 11 are divided on the substrate 1 according to the preparation and design requirements, and after the chip regions 11 on the substrate 1 are subjected to photolithography, oxidation, doping, deposition, metallization, and other process flows, the substrate 1 is cut into a plurality of chips according to the dividing region boundary lines of the chip regions 11.
Fig. 2 is a schematic flow chart of a method for preparing an overlay mark according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram corresponding to the flow steps in fig. 2 in an embodiment of the present invention, that is, (a) to (e) in fig. 3 correspond to steps S101 to S105 in fig. 2 one to one.
Fig. 4 (1) is a schematic structural diagram of the mask layer 3 in the embodiment of the present invention, and (2) is a partially enlarged schematic diagram of (1).
FIG. 5 is a sectional view taken along line A-A' in FIG. 3 (c).
Referring to fig. 2 and fig. 3(a) to (e), an embodiment of the present invention provides a method for preparing an overlay mark, including steps S101 to S105, wherein:
s101, with reference to fig. 3(a), providing a substrate 1, on which a metal layer 2, such as an Al layer, a Ni layer, etc., is formed, in a specific implementation, a material selected for the metal layer 2 is not limited thereto, and other metal materials may be selected according to a preparation process and a purpose. In some embodiments of the quantum chip manufacturing process, the substrate 1 is selected from a high-resistance silicon wafer and a sapphire wafer.
S102, with reference to fig. 3(b), patterning the metal layer 2 to obtain an overlay mark region 21 on the surface of the substrate 1, that is, etching and removing the metal layer 2 in the designated region by using a patterning process to form a groove, and forming the overlay mark region 21 on the surface of the substrate 1 exposed after the metal layer 2 in the designated region is removed.
S103, with reference to fig. 3(c), forming a mask layer 3 on the metal layer 2, wherein a position of the mask layer 3 corresponding to the overlay mark region 21 is formed with an overhanging pattern window 31, as shown in fig. 3(c), fig. 4 and fig. 5, that is, a position right above the overlay mark region 21, and the pattern window 31 is in accordance with the shape of the overlay mark 5 to be prepared. In this step, the overhanging pattern window 31, as shown by the dotted circle in fig. 5, is suspended at the edge of the pattern window 31 above the overlay mark 21, so that the notch area of the groove formed after removing the metal layer 2 in the designated area by etching is larger than the window area of the pattern window 31. The pattern window 31 is formed at a position on the mask layer 3 corresponding to the overlay mark region 21, and is mainly used to accurately deposit and gather the marking material at a position on the overlay mark region 21 corresponding to the pattern window 31, for example, directly under the pattern window 31, and the shape of the pattern window 31 is required to be consistent with the shape of the overlay mark 5 in order to obtain the overlay mark 5 having a specific shape.
S104, with reference to fig. 3(d), using the mask layer 3 as a mask, evaporating a marking material through the pattern window 31 in the overlay mark region 21, wherein the edge of the formed pattern window 31 is suspended, the metal layer 2 is covered by the mask layer 3 when evaporating the marking material, the evaporated marking material is gathered at a position on the overlay mark region 21 corresponding to the pattern window 31, as shown in fig. 5, that is, the evaporated marking material is gathered at a region right below the pattern window 31, and the evaporated marking material and the metal layer 2 are not in adhesive contact.
S105, with reference to fig. 3(e), the mask layer 3 is removed, and the mark material on the overlay mark region 21 forms an overlay mark 5.
In the implementation of the invention, the surface of a substrate 1 is exposed through a metal layer 2 on a patterned substrate 1 to obtain an overlay mark area 21; then forming a mask layer 3 on the metal layer 2, and forming an overhanging pattern window 31 on the mask layer 3 at a position corresponding to the overlay mark region 21; then, the mask layer 3 is used as a mask, and a marking material is evaporated on the overlay marking region 21 by using the pattern window 31; finally, the mask layer 3 is removed and the marking material on the overlay mark region 21 is etched to form an overlay mark 5. In the embodiment of the invention, the marking material is directly evaporated on the surface of the substrate 1, and due to the shielding and masking effect of the suspended pattern window 31, the marking material is gathered in the area right below the pattern window 31 and does not adhere to or contact the metal layer 2, so that the possibility of electrochemical reaction and the like between the overlay mark 5 and the metal layer 2 is reduced, and the problems of black spots and corrosion marks generated when the overlay mark is directly evaporated on the surface of the metal layer such as an aluminum film and the like on a Wafer (Wafer) to form the overlay mark in the prior art are avoided.
Fig. 6 is another schematic structural diagram corresponding to each flow step in fig. 2 in an embodiment of the present invention, and it should be noted that (b '), (c ') and (d ') in fig. 6 are schematic structural diagrams corresponding to different embodiments, compared to (b), (c) and (d) in fig. 3.
In FIG. 7, (1) is a sectional view taken along line B-B 'in FIG. 6 (B'), and (2) is a sectional view taken along line C-C 'in FIG. 6 (C').
Referring to fig. 6 (b'), fig. 7(1), in some embodiments of the present invention, for step S102, the patterning the metal layer 2 to obtain an overlay mark region 21 on the surface of the substrate 1 includes steps S102-1 to S102-2:
s102-1, forming a patterned resist layer 4 on the metal layer 2, wherein the patterned resist layer 4 has an overlay mark region pattern 41 formed thereon, and it can be understood that the overlay mark region pattern 41 conforms to the shape of the overlay mark region 21 to be obtained, and wherein, as an example, the forming of the patterned resist layer 4 on the metal layer 2 includes: coating photoresist on the metal layer, and exposing and developing to form a patterned resist layer;
s102-2, etching the metal layer 2 by using the patterned corrosion resistant layer 4 as a mask to obtain an etching pattern, wherein the etching pattern comprises an alignment mark region 21 located on the surface of the substrate 1.
More preferably, as shown in (b') in fig. 6, in order to improve the efficiency of quantum chip preparation and shorten the quantum chip preparation process cycle, the patterned resist layer 4 in step S102-1 is further formed with a josephson junction preparation region pattern 42 and a control line pattern including a first control line pattern 43 and a second control line pattern 44, and a coplanar waveguide transmission line pattern; in step S102-2, the etching pattern further includes a josephson junction preparation region 22 and a control line on the surface of the substrate and a coplanar waveguide transmission line, the control line includes a first control line 43 and a second control line 44, i.e., the process of preparing the alignment mark and the process of preparing the quantum chip device are integrated, in this step, an overlay mark region pattern 41, a josephson junction preparation region pattern 42 and a control line pattern are formed in one patterning process, and the overlay mark region pattern 41, the josephson junction preparation region pattern 42 and the control line pattern are formed in a manner of being different from that of a plurality of patterning processes, so that the chip preparation period is greatly shortened. Specifically, the process flow "glue coating, exposing, developing, etching, removing glue" required for preparing the josephson junction preparation region 22 and the control circuit pattern and the process flow "glue coating, exposing, developing, evaporating and coating a marking material, removing glue" required for preparing the overlay mark 5 can be integrated together, so that the process steps repeated for many times are saved, thereby being beneficial to improving the chip preparation efficiency and shortening the chip preparation process period.
As shown in fig. 7, more preferably, in order to further avoid adhesion and contact between the evaporated marking material and the metal layer 2, a lower cut 6 is formed between the patterned resist layer 4 and the overlay mark region 21 in step S102-1, where the lower cut 6 is a notch formed by recessing the edge of the metal layer 2 above the overlay mark region 21 to one side with respect to the edge of the resist layer 4 under the action of the etching medium when the metal layer 2 in the designated region is removed by etching.
Referring to fig. 6 (c'), 7(2), more preferably, in order to further shorten the process cycle, after steps S102-1 to S102-2 are completed, a mask layer 3 is directly formed on the resist layer 4, that is, for step S103, the mask layer 3 is formed on the metal layer 2, and an overhanging pattern window 31 is formed on the mask layer 3 at a position corresponding to the overlay mark region 21, including:
forming a mask layer 3 on the patterned resist layer 4, wherein a pattern window 31 is formed on the mask layer 3 at a position corresponding to the overlay mark region 21, and the pattern window 31 is in an overhang shape with respect to the overlay mark region 21, as shown by a dotted circled portion in fig. 7(2), that is, an edge of the formed pattern window 31 is suspended.
If the mask layer 3 is directly formed on the resist layer 4, and then, referring to fig. 6 (d'), a marking material is deposited on the overlay mark region 21 through the pattern window 31 using the mask layer 3 as a mask, and in step S106, the removing the mask layer and the marking material on the overlay mark region forming the overlay mark 5 includes:
removing the mask layer 3, wherein the mask layer 3 and the residual marking material on the surface of the mask layer are removed together;
the patterned resist layer 4 is removed, the mark material on the overlay mark region 21 forms the overlay mark 5, as shown in fig. 6 (e), because the edge of the formed pattern window 31 is suspended, the pattern window 31 can also play a role of shielding and masking when the mark material is evaporated, so that the mark material gathered on the overlay mark region 21 is not adhered to the resist layer 4, and the appearance of the formed overlay mark 2 is not damaged when the resist layer 4 is removed.
Referring to fig. 4, fig. 6 (c'), and fig. 7(2), in another embodiment of the present invention, in step S103, the forming a mask layer 3 on the metal layer 2, a pattern window 31 overhanging the mask layer 3 at a position corresponding to the overlay mark region 21 is formed, and the pattern window 31 conforms to the shape of the overlay mark 4 to be prepared, including steps S103-1 to S103-3:
s103-1, providing a mask layer 3, wherein the mask layer 3 is consistent with the substrate 1 in shape, so that the mask layer 3 is aligned with the substrate 1 by utilizing shape features;
s103-2, forming a pattern window 31 at a position, corresponding to the overlay mark region 21, on the mask layer 3, wherein the window area of the pattern window 31 is smaller than the area of the overlay mark region 21, and the pattern window 31 is consistent with the shape of an overlay mark 5 to be prepared;
s103-3, placing the mask layer 3 on the metal layer 2 and making the overlay mark region 21 correspond to the overhanging pattern window 31, as shown by the dashed circle in fig. 7 (2).
Fig. 8 is a schematic structural diagram of a receiving device according to an embodiment of the invention.
Referring to fig. 3, 6 and 8, in an embodiment of the present invention, in order to facilitate alignment between a mask layer 3 and a substrate 1 so as to form an overlay mark 4 in a designated area, a first alignment structure 12 is formed on the substrate 1, a second alignment structure 32 matched with the first alignment structure 12 is formed on the mask layer 3, and the mask layer 3 is disposed on the metal layer 2 so that the overlay mark area 21 is correspondingly provided with an overhanging pattern window 31, including:
the mask layer 3 is placed on the metal layer 2 and the first alignment structure 12 and the second alignment structure are aligned 32 such that the pattern window 31 corresponds in position to the overlay mark region 21 and the pattern window 31 overhangs with respect to the overlay mark region 21.
As a specific example, in step S103-3, the placing the mask layer 3 on the metal layer 2 and aligning the second alignment structure 32 and the first alignment structure 12 so that the pattern window 31 corresponds to the overlay mark region 21, and the pattern window 31 is overhanging with respect to the overlay mark region 21 includes:
103-3-1, providing a containing device 7, wherein the containing device is provided with a containing cavity 71 and a rotatable clamping part 73, and a third alignment structure 73 matched with the first alignment structure 12 and the second alignment structure 32 is arranged in the containing cavity 71;
103-3-2, placing the substrate 1 in the accommodating cavity 71, and aligning the first alignment structure 12 with the third alignment structure 73;
103-3-3, placing the mask layer 3 on the metal layer 2, aligning the second alignment structure 32 with the third alignment structure 73, so that the pattern window 31 corresponds to the overlay mark region 21, and the pattern window 31 overhangs relative to the overlay mark region 21, and then rotating the clamping portion 73 to fix the mask plate 3 and the substrate 1 in the accommodating cavity 71.
In some embodiments of the present invention, in order to overcome the defect of poor adhesion between gold and the substrate 1, in step S104, evaporating a marking material in the overlay mark region 21 through the pattern window 31 by using the mask layer 3 as a mask, including:
s104-1, with the mask layer 3 as a mask, evaporating titanium on the overlay mark region 21 through the pattern window 31 to form an overlay mark base;
s104-2, with the mask layer 3 as a mask, evaporating gold on the base of the overlay mark through the pattern window 31 to form the top of the overlay mark.
After the mask layer 3 is removed, the mark material on the overlay mark region 21 forms an overlay mark 5, that is, the overlay mark comprises an overlay mark base and an overlay mark top located on the overlay mark base, and the adhesion of the substrate 1 to titanium used for the overlay mark base is better than that of gold.
The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.
Claims (10)
1. A method of making an overlay mark, comprising:
providing a substrate, wherein a metal layer is formed on the substrate;
patterning the metal layer to obtain an overlay mark region on the surface of the substrate;
forming a mask layer on the metal layer, wherein an overhanging pattern window is formed on the mask layer at a position corresponding to the overlay mark region, and the pattern window is consistent with the shape of an overlay mark to be prepared;
evaporating a marking material in the overlay marking area through the pattern window by taking the mask layer as a mask;
and removing the mask layer, wherein the marking material on the alignment marking area forms an alignment marking.
2. The method according to claim 1, wherein the patterning the metal layer to obtain an overlay mark region on the surface of the substrate comprises:
forming a patterned resist layer on the metal layer, the patterned resist layer having an overlay mark region pattern formed thereon;
and etching the metal layer by taking the patterned etching resistant layer as a mask to obtain an etching pattern, wherein the etching pattern comprises an alignment mark area positioned on the surface of the substrate.
3. The production method according to claim 2, wherein the patterned resist layer is further formed with a josephson junction preparation region pattern and a control wiring pattern; the etching pattern further comprises a Josephson junction preparation region and a control line on the surface of the substrate.
4. A method of manufacturing as claimed in claim 2, wherein an undercut is formed between the patterned resist layer and the overlay mark region.
5. The method according to claim 2, wherein the forming a mask layer on the metal layer, the mask layer having an overhanging pattern window formed at a position corresponding to the overlay mark region comprises:
and forming a mask layer on the patterned etching-resistant layer, wherein a pattern window is formed on the mask layer at a position corresponding to the pattern of the overlay mark region, and the pattern window is in an overhang shape relative to the overlay mark region.
6. The method of claim 5, wherein the removing the mask layer and the marking material on the overlay mark region form an overlay mark comprises:
removing the mask layer;
and removing the patterned anti-corrosion layer, wherein the marking material on the overlay mark area forms an overlay mark.
7. The method according to claim 1, wherein the forming a mask layer on the metal layer, wherein an overhanging pattern window is formed on the mask layer at a position corresponding to the overlay mark region, and the pattern window conforms to a shape of an overlay mark to be prepared, comprises:
providing a mask layer, wherein the mask layer is consistent with the shape of the substrate;
forming a pattern window on the mask layer at a position corresponding to the overlay mark region, wherein the window area of the pattern window is smaller than the area of the overlay mark region, and the pattern window is consistent with the shape of the overlay mark to be prepared;
and placing the mask layer on the metal layer and enabling the overlay mark region to correspond to the overhanging pattern window.
8. The method of claim 7, wherein the substrate has a first alignment structure formed thereon, the mask layer has a second alignment structure formed thereon that mates with the first alignment structure, and the placing the mask layer on the metal layer and the overlay mark region has the overhanging pattern window thereon comprises:
placing the mask layer on the metal layer and aligning the second alignment structure and the first alignment structure such that the pattern window corresponds in position to the overlay mark region and the pattern window overhangs with respect to the overlay mark region.
9. The method of claim 8, wherein the placing the mask layer on the metal layer and aligning the second alignment structure and the first alignment structure such that the pattern window corresponds in position to the overlay mark region and the pattern window overhangs the overlay mark region comprises:
providing a containing device, wherein the containing device is provided with a containing cavity, and the containing cavity comprises a third alignment structure matched with the first alignment structure and the second alignment structure;
placing the substrate in the accommodating cavity, wherein the first alignment structure is aligned with the third alignment structure;
and placing the mask layer on the metal layer, and aligning the second alignment structure with the third alignment structure so that the pattern window corresponds to the overlay mark region in position and is suspended relative to the overlay mark region.
10. The method according to claim 1, wherein the step of evaporating a marking material through the pattern window onto the overlay mark region by using the mask layer as a mask comprises:
with the mask layer as a mask, evaporating titanium on the overlay mark region through the pattern window to form an overlay mark base;
and taking the mask layer as a mask, and evaporating gold on the base part of the overlay mark through the pattern window to form the top part of the overlay mark.
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