KR100356014B1 - Fabrication method for align mark - Google Patents

Abstract

It is an object of the present invention to provide a method for smoothly aligning a semiconductor device by making it possible to manufacture an alignment mark for improving alignment accuracy in a wafer backside process.

According to the present invention, there is provided a method for manufacturing a back alignment mark, comprising: a first step of cross forming a first alignment mark with a front metal film on a semiconductor substrate in a front surface process; A second step of forming a second alignment mark having the same shape in up, down, left, and right symmetry with the first alignment mark as the symmetry point using the front pattern formed in the first step; Forming a third alignment mark for the rear via hole pattern, which is the same shape as the cross-shaped first alignment mark formed in the first step and is narrower in width and longer than the first alignment mark, on the resultant of the second step. Provided is a method for producing a back alignment mark, comprising a third step.

Description

Fabrication method for align mark

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an alignment mark, and more particularly, to a method for manufacturing a rear alignment mark in a rear process, which is important in an ultra high frequency ultra high speed semiconductor device process.

The conventional rear alignment mark manufacturing method has a problem in that it is difficult to determine how much the alignment precision is, by making the shape of the mark square when forming the rear alignment mark, and in particular, it is difficult to find the alignment mark.

Looking at such a conventional alignment mark manufacturing method is as follows.

Looking at the prior patent whose right holder is Nippon Denki Kabushiki Kaisha, inventor is Keihashi Kaeishiro, and the patent name is 'method for forming alignment mark and manufacturing semiconductor device' (Registration No. 0266190). Same as

This prior patent proposes the following method to increase the degree of alignment.

After the etching PR portion is formed on the first insulating layer, a second insulating layer is formed on the first insulating layer to cover the etching PR portion. The second insulating layer is then selectively etched using the first patterned lithographic PR film as a mask to form a recess that exposes the etch PR portion. In this etching fixation, the first insulating layer is prevented from being etched in the recess of the second insulating layer by the etching PR portion.

A layer to be patterned is then formed on the second insulating layer, and a second patterned lithographic PR film is formed on the layer to be patterned. The second patterned lithographic PR film has a shape such that a portion of the second lithographic PR film remains in a recess of the second insulating layer. The portion of the second lithographic PR film in the recess has a height difference approximately equal to or less than the thickness of the second insulating layer with the other portion of the second lithographic PR film outside the recess. With this arrangement, the alignment error of the pattern of the second lithographic PR film with respect to the pattern of the second insulating layer is accurately measured.

That is, forming a first insulating layer on the surface of the semiconductor structure, forming an etching PR portion on the first insulating layer, forming a second insulating layer on the first insulating layer to form the etching PR portion Covering the substrate, forming a first lithographic PR film on the second insulating layer, patterning the first lithographic PR film to have a window, and using the first lithographic PR film as a mask to selectively select the second insulating layer. Etching to form a recess in the second insulating layer, the recess being at a position corresponding to the window of the first lithographic PR film, the bottom of the recess being formed by the etching PR portion. Removing the first lithographic PR film, forming a layer to be patterned on the second insulating layer, and a second lithographic PR film on the layer to be patterned. Forming a second lithographic PR film such that a portion of the second lithographic PR film remains in the recess of the second insulating layer, wherein the second lithographic PR film is patterned. The portion of the second lithographic PR film remaining in the set is characterized by acting as an alignment mark for measuring the alignment error of the pattern of the second lithographic PR film with respect to the pattern of the second insulating layer.

Such alignment marks have an effect of improving the degree of alignment, but as described above, when forming the rear alignment marks, it is difficult to check how much the alignment precision is due to the square shape of the marks, and in particular, it is difficult to find the alignment marks. .

Accordingly, the present invention is to solve the problems of the prior art as described above, an object of the present invention is to increase the alignment accuracy during the wafer backside process, and to easily adjust the shape and size of the alignment from the design of the alignment mark It is to provide a method for forming a rear alignment mark to facilitate the actual alignment.

1 is a plan view showing a configuration of a rear alignment mark according to an embodiment of the present invention,

2A to 2C are views illustrating a method of manufacturing the rear alignment mark shown in FIG. 1.

※ Explanation of main parts of drawing ※

1: Rear alignment mark on the front

2: Rear alignment mark for rear via hole alignment

3: rear via hole alignment mark

According to the present invention for achieving the above object, a method for manufacturing a rear alignment mark, comprising: a first step of cross forming a first alignment mark for rear alignment with a front metal film on a semiconductor substrate in a front surface process; A second step of forming a second alignment mark having the same shape in up, down, left, and right symmetry with the first alignment mark as the symmetry point using the front pattern formed in the first step; Forming a third alignment mark for the rear via hole pattern, which is the same shape as the cross-shaped first alignment mark formed in the first step and is narrower in width and longer than the first alignment mark, on the resultant of the second step. There is provided a method for producing an alignment mark, comprising a third step.

Hereinafter, a method of manufacturing rear alignment marks according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view showing an alignment mark used in the method for manufacturing a rear alignment mark according to an embodiment of the present invention, Figures 2a to 2c schematically illustrates a method for manufacturing a rear alignment mark according to an embodiment of the present invention As shown, it will be described in detail as follows.

The rear alignment mark shown in FIG. 1 consists of a rear alignment mark 1 at the front, a rear alignment mark 2 for rear via hole alignment and a rear via hole alignment mark 3. A detailed manufacturing method thereof is shown in FIGS. 2A and 2C, which will be described below.

The structure of the alignment mark will be described first in detail as follows. The structure of the rear alignment mart (hereinafter referred to as alignment mark 1 in FIG. 1), which is engraved on the front side, is shown in FIG. 2A, which is an alignment mark (a) 30 microns wide and 580 microns long and 30 microns wide. The alignment marks b, which are 280 microns in length, are intersected with each other.

A rear alignment mark (referred to as 2 in FIG. 1, hereinafter referred to as alignment mark 2 in FIG. 1) for rear via hole alignment is placed on the alignment mark 1 shown in FIG. 2A, which is a diagram showing FIG. 2B.

The size of the alignment mark 2 shown in FIG. 2B is symmetrically placed on the right and left (c) and the patterns are arranged symmetrically (e, f) again so that the width of the alignment mark 2 is widened from 10 to 150 microns. After that, the pattern (c) above is rotated 90 degrees to the right and placed one (g), and rotated to the left 90 degrees (h).

A rear via hole alignment mark (3 in FIG. 1, hereinafter referred to as alignment mark 3) is placed on the alignment mark 2 shown in FIG. 2C, which is shown in FIG. 2C.

The alignment mark 3 shown in FIG. 2C is a mark for the via hole, and is configured such that an alignment mark k having a width of 10 microns and a length of 600 microns and an alignment mark 1 having a width of 10 microns and a length of 300 microns intersect. As shown in Fig. 2C, alignment marks (k, l) are placed at the center of each alignment pattern shown in Fig. 2A, and the alignment marks (k, l) are used to determine the degree of alignment. The top, bottom, left and right sides were each 10 microns long. Here, the x- and y-axes can be fitted with 0-10 micron inclination patterns to increase the alignment accuracy to 0-150 microns and can be confirmed with a microscope.

Meanwhile, in order to form the alignment pattern illustrated in FIG. 2A, Ti / Pt / Au is deposited by 400 A / 200 A / 4000 A, respectively, during the front metal process to form a metal lift-off process. In order to protect the front element and the integrated circuit, a protective layer is formed of a photoresist film. The protective layer is attached to the sapphire substrate and the back surface of the wafer is wrapped to a desired thickness.

In order to form the alignment pattern shown in FIG. 2B, the rear surface is cleaned, then a photosensitive film is applied and heat treated, and a rear alignment mark is formed using a contact alignment device. At this time, the front pattern should be aligned while looking at the rear part. Therefore, an alignment exposure machine with an IR lamp should be used so that the light transmittance on the metal and the substrate is different during the alignment.

At this time, the pattern of the front metal should be transferred as it is to the mask on the back, but the shape of the pattern is not clear due to the thickness of the substrate, the thickness of the substrate support, and the surface roughness. Thus, the use of a conventional alignment mark causes a problem that the open area on the mask is small (20 microns), making it difficult to find a pattern.

Therefore, when using the alignment mark according to an embodiment of the present invention, since the open area (200 microns) on the mask is large, it is very easy to find the front mark, and the time is shortened. When the alignment is performed using the marks presented in the embodiment of the present invention, the alignment can be performed using the same mark at the same time on the x and y axes, and the alignment can be more precisely aligned since the stepped misalignment checking method is used. .

In order to form the alignment pattern shown in FIG. 2C, when the alignment is completed, the photosensitive layer is developed and formed to form the pattern. Using this pattern, Ti / Au metals are deposited by 400 A / 2000 A, respectively, to form alignment marks. The alignment marks thus formed can continue to be used in the backside process. This alignment mark is used to form the rear via hole pattern. The back via hole pattern is formed by applying a 10 micron photosensitive film to the heat treatment, and using the rear via hole mask to align and expose the light. Using this pattern, the back via hole is etched, cleaned and plated to complete the back process.

The proposed method is not only applicable to the formation of rear alignment marks such as HEMT, HBT, MESFET devices, but also for the fabrication of devices using precise processes requiring rear alignment in the manufacture of ultra-high frequency devices. have.

While the invention has been described above based on the preferred embodiments thereof, these embodiments are intended to illustrate rather than limit the invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments can be made without departing from the spirit of the invention. Therefore, the protection scope of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

As described above, the present invention provides a method of manufacturing a rear alignment mark, thereby increasing alignment accuracy in a wafer rear surface process, making it easy to control, and smoothing alignment of a semiconductor device rear surface process.

In addition, the present invention has an effect that can easily adjust the shape and size of the alignment mark when the alignment mark is made, and the actual alignment is easy. Therefore, the present invention can be used to fabricate the back electrode of the device operating at high speed, high frequency, there is an effect that can be manufactured to produce a fine gate production and high reliability device.

In other words, the present invention, according to the experiment, can be aligned less than 1 to 2 microns in terms of alignment precision, the time required for alignment also takes more than 30 minutes per sheet in the existing method, according to the present invention, about 5 minutes per sheet By taking time, the productivity is improved.

Claims (9)

In the manufacturing method for the rear alignment mark, A first step of cross forming a first alignment mark for rear alignment with a front metal film on a semiconductor substrate in a front surface process; A second step of forming a second alignment mark having the same shape in up, down, left, and right symmetry with the first alignment mark as the symmetry point using the front pattern formed in the first step; Forming a third alignment mark for the rear via hole pattern, which is the same shape as the cross-shaped first alignment mark formed in the first step and is narrower in width and longer than the first alignment mark, on the resultant of the second step. And a third step. The method of claim 1, The first step is, Performing a metal lift-off process by depositing tin (Ti) / platinum (Pt) / gold (Au); Forming a protective layer with a photosensitive film to protect the front device and the integrated circuit; And And a sub step of lapping the wafer back side to a desired thickness. The method according to claim 1 or 2, The first step is, And the first alignment mark is wider than the rear third alignment mark. The method of claim 1, The second step, After cleaning the back side, the photosensitive film is apply | coated and heat-processed, and the 2nd alignment mark is formed using a contact alignment apparatus, The manufacturing method of the alignment mark characterized by the above-mentioned. The method according to claim 1 or 4, The second step, The second alignment mark is an alignment mark, characterized in that for making the alignment with the first alignment mark easy to make a symmetrical slope, to create a step, and to form a size larger than the first alignment mark. Manufacturing method. The method of claim 1, The second step, And forming the second alignment pattern by inserting an inclined pattern in order to increase alignment accuracy. The method of claim 1, The second step, And a second alignment mark using an alignment exposure machine with an IR lamp attached so that light transmittance on the metal and the substrate is different. The method of claim 1, The third step, The third alignment mark has a width smaller than the etch depth so as not to be over-etched during the etching of the rear via hole, and a heat treatment is performed by applying a photoresist film. Alignment mark manufacturing method. The method according to claim 1 or 8, The third step, And forming a width of the third alignment mark smaller than that of the first alignment mark.