JPH04142726A - Manufacture of thin film circuit substrate - Google Patents
Manufacture of thin film circuit substrateInfo
- Publication number
- JPH04142726A JPH04142726A JP26670290A JP26670290A JPH04142726A JP H04142726 A JPH04142726 A JP H04142726A JP 26670290 A JP26670290 A JP 26670290A JP 26670290 A JP26670290 A JP 26670290A JP H04142726 A JPH04142726 A JP H04142726A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- conductor
- photoresist
- film
- recognition mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010409 thin film Substances 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims abstract description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 14
- 230000031700 light absorption Effects 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000003909 pattern recognition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 7
- 238000010521 absorption reaction Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 2
- 230000007261 regionalization Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜回路基板の製造方法に関し、特に導体パタ
ーンと抵抗膜の抵抗パターンとの位置合わせを正確に行
うことができる薄膜回路基板の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a thin film circuit board, and in particular to a method for manufacturing a thin film circuit board in which a conductor pattern and a resistance pattern of a resistive film can be accurately aligned. Regarding the method.
従来、この種の薄膜回路基板の製造方法は、第4図(a
)、(b)の側断面図、平面図のように、アルミナセラ
ミック等の絶縁基板1の表面に、第1工程として抵抗膜
による抵抗パターン2と認識マーク7Aを形成する。第
2工程として認識マーク7Aから目合わせて基準を決め
、選択めっき用導体膜4と導体パターン8C,8Dとを
形成していた。Conventionally, a method for manufacturing this type of thin film circuit board is shown in FIG. 4(a).
), (b), a resistance pattern 2 made of a resistance film and a recognition mark 7A are formed on the surface of an insulating substrate 1 made of alumina ceramic or the like as a first step. As a second step, a reference was determined by aligning from the recognition mark 7A, and a conductor film 4 for selective plating and conductor patterns 8C and 8D were formed.
上述した従来の薄膜回路基板の製造方法は、抵抗膜を利
用した任意の大きさで認識マークを形成し、その後導体
パターンの位置決めに使用される導体マスクを目合わせ
により認識マークと位置合わせしているので、この導体
マスクを基準に形成された導体パターンと抵抗パターン
との相対的な位置ずれが発生する欠点がある。The conventional thin film circuit board manufacturing method described above involves forming a recognition mark of any size using a resistive film, and then aligning the conductor mask used for positioning the conductor pattern with the recognition mark by eye alignment. Therefore, there is a drawback that a relative positional shift occurs between the conductor pattern and the resistor pattern formed using the conductor mask as a reference.
本発明の薄膜回路基板の製造方法は、絶縁基板上に光吸
収率の大きい抵抗膜となる金属を被着し、フォトレジス
ト処理で抵抗パターンおよび認識用マークバタンを形成
する第1の製造工程と、選択めっきを可能とする導体膜
を被着し、導体パターン形成をフォトレジスト処理でパ
ターン化し、光吸収率の小さい金属をめっきで導体パタ
ーニングを行い、かつ、導体内に前記認識用マークパタ
ーンの部分に開口部を設けた第2の製造工程と、導体パ
ターン以外のフォトレジスト除去及びフォトレジスト下
部の選択めっき用導体膜を除去して膜回路形成と同時に
パターン認識マークを形成する第3の製造工程を有する
。The method for manufacturing a thin film circuit board of the present invention includes a first manufacturing step in which a metal serving as a resistive film with a high light absorption rate is deposited on an insulating substrate, and a resistive pattern and a recognition mark button are formed by photoresist processing. , a conductor film that enables selective plating is applied, a conductor pattern is formed by photoresist processing, a conductor pattern is formed by plating a metal with a low light absorption rate, and the recognition mark pattern is formed within the conductor. A second manufacturing process in which an opening is formed in a portion, and a third manufacturing process in which a pattern recognition mark is formed at the same time as film circuit formation by removing the photoresist other than the conductor pattern and removing the conductive film for selective plating under the photoresist. Has a process.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)、(b)は本発明の一実施例の側断面図と
平面図であり、本実施例により製造された薄膜回路基板
の完成図である。第2図(a)。FIGS. 1(a) and 1(b) are a side sectional view and a plan view of an embodiment of the present invention, and are a completed view of a thin film circuit board manufactured according to this embodiment. Figure 2(a).
(b)および第3図(a)、(b)は、それぞれ本実施
例における第1工程および第2工程の製造工程を説明す
る側断面図と平面図である。3(b) and FIGS. 3(a) and 3(b) are a side sectional view and a plan view, respectively, illustrating the manufacturing steps of the first step and the second step in this example.
次に本実施例の製造工程を説明する。Next, the manufacturing process of this example will be explained.
第1工程、第2図に示すように、絶縁基板1に光吸収率
の高い抵抗膜を被着し、フォトレジスト処理及びエツチ
ングにより抵抗パターン2およびマーク用パターン3を
所定の位置に形成する。In the first step, as shown in FIG. 2, a resistive film having a high light absorption rate is deposited on an insulating substrate 1, and a resistive pattern 2 and a mark pattern 3 are formed at predetermined positions by photoresist processing and etching.
第2工程、第3図に示すように、選択めっきを可能とす
る導体膜4を被着し、マーク用パターン3より小さめの
形で導体の内部に開口部5を設けた導体パターン6A、
6Bの形成をフォトレジスト処理でパターン化する。導
体パターンの材料は光吸収率の抵い金属をめっきでパタ
ーニングし、フォトレジストを除去したものである。In the second step, as shown in FIG. 3, a conductor pattern 6A is coated with a conductor film 4 that enables selective plating, and has an opening 5 inside the conductor that is smaller than the mark pattern 3;
The formation of 6B is patterned by photoresist processing. The conductor pattern material is made by patterning a metal with low light absorption rate by plating, and then removing the photoresist.
第3工程、第1図に示すように、導体パターン6A、6
B以外の抵抗パターン2と認識マーク7ノ抵抗ハターン
を露出するために、フォトレジスト下層の選択めっき用
導体膜4をエツチングにより除去することで抵抗パター
ン2の導体パターン6A、6Bの膜回路形成と導体内部
のパターン認識マーク7が形成される。Third step, as shown in FIG.
In order to expose the resistor pattern 2 other than B and the resistor pattern of the recognition mark 7, the conductor film 4 for selective plating under the photoresist is removed by etching, thereby forming the film circuit of the conductor patterns 6A and 6B of the resistor pattern 2. A pattern recognition mark 7 inside the conductor is formed.
以上説明したように本発明は、導体パターン形成時吸収
率の低い導体パターンの内部に開口部を設け、開口部が
吸収率の高い抵抗膜の認識マークとすることにより、認
識マークと導体パターンの位置ずれが防止できる効果が
ある。したがって組立時のワイヤボンディング位置の精
度がよくなり、高精度デバイスが供給できる。As explained above, the present invention provides an opening inside a conductor pattern with a low absorption rate when forming a conductor pattern, and by using the opening as a recognition mark of a resistive film with a high absorption rate, the recognition mark and the conductor pattern can be separated. This has the effect of preventing misalignment. Therefore, the precision of the wire bonding position during assembly is improved, and a high precision device can be provided.
第1図(a)、(b)は本発明の一実施例の側断面図と
平面図、第2図(a)y (b) 、および第3図(
a)、(b)は本実施例の製造工程を説明する側断面図
と平面図、第4図は従来の薄膜回路基板の製造方法を説
明する側断面図と平面図である。
1・・・絶縁基板、2・・・抵抗パターン、3・・・マ
ーク用パターン、4・・・選択めっき用導体膜、5・・
・開口部、8A、8B・・・導体パターン、7・・・認
識マーク。FIGS. 1(a) and (b) are a side sectional view and a plan view of an embodiment of the present invention, FIGS. 2(a) and 3(b), and FIG.
a) and (b) are a side sectional view and a plan view illustrating the manufacturing process of this embodiment, and FIG. 4 is a side sectional view and a plan view illustrating a conventional method for manufacturing a thin film circuit board. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Resistance pattern, 3... Mark pattern, 4... Conductor film for selective plating, 5...
- Opening, 8A, 8B... Conductor pattern, 7... Recognition mark.
Claims (1)
被着し、フォトレジスト処理で抵抗パターンおよび認識
用マークパタンを形成する第1の製造工程と、選択めっ
きを可能とする導体膜を被着し、導体パターン形成をフ
ォトレジスト処理でパターン化し、光吸収率の小さい金
属をめっきで導体パターニングを行い、かつ、導体内に
前記認識用マークパターンの部分に開口部を設けた第2
の製造工程と、導体パターン以外のフォトレジスト除去
及びフォトレジスト下部の選択めっき用導体膜を除去し
て膜回路形成と同時にパターン認識マークを形成する第
3の製造工程を有することを特徴とする薄膜回路基板の
製造方法。2、前記開口部が前記認識マークパターンの
大きさよりわずかに小さく形成し、前記導体パターンと
前記抵抗パターンとの相対位置を設定する認識マークと
することを特徴とする請求項1記載の薄膜回路基板の製
造方法。1. The first manufacturing process of depositing a metal that will become a resistive film with high light absorption on an insulating substrate and forming a resistive pattern and recognition mark pattern by photoresist treatment, and a conductive film that enables selective plating. a conductor pattern formed by photoresist processing, conductor patterning performed by plating a metal with low light absorption rate, and an opening provided in the conductor at the portion of the recognition mark pattern.
and a third manufacturing step of removing the photoresist other than the conductor pattern and removing the conductive film for selective plating under the photoresist to form a pattern recognition mark at the same time as film circuit formation. Method of manufacturing circuit boards. 2. The thin film circuit board according to claim 1, wherein the opening is formed to be slightly smaller than the size of the recognition mark pattern, and serves as a recognition mark for setting a relative position between the conductor pattern and the resistor pattern. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26670290A JPH04142726A (en) | 1990-10-04 | 1990-10-04 | Manufacture of thin film circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26670290A JPH04142726A (en) | 1990-10-04 | 1990-10-04 | Manufacture of thin film circuit substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04142726A true JPH04142726A (en) | 1992-05-15 |
Family
ID=17434497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26670290A Pending JPH04142726A (en) | 1990-10-04 | 1990-10-04 | Manufacture of thin film circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04142726A (en) |
-
1990
- 1990-10-04 JP JP26670290A patent/JPH04142726A/en active Pending
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