JPH0487392A - Manufacture of wiring board - Google Patents

Manufacture of wiring board

Info

Publication number
JPH0487392A
JPH0487392A JP20146090A JP20146090A JPH0487392A JP H0487392 A JPH0487392 A JP H0487392A JP 20146090 A JP20146090 A JP 20146090A JP 20146090 A JP20146090 A JP 20146090A JP H0487392 A JPH0487392 A JP H0487392A
Authority
JP
Japan
Prior art keywords
resist
wiring
board
resist layer
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20146090A
Other languages
Japanese (ja)
Other versions
JP2897365B2 (en
Inventor
Toshio Tamura
田村 俊夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP20146090A priority Critical patent/JP2897365B2/en
Publication of JPH0487392A publication Critical patent/JPH0487392A/en
Application granted granted Critical
Publication of JP2897365B2 publication Critical patent/JP2897365B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

PURPOSE:To enhance the precision property and stability of a resist layer and to make possible the formation of circuits, which are high in accuracy and density, by a method wherein an exposure and development type second resist is applied on the whole surface of a board and this second resist is exposed and developed according to wiring patterns. CONSTITUTION:Wiring patterns 2 are formed on a board 1 and thereafter, the peripheries of connecting terminal parts 2a are reliably removed in consideration of printing accuracy, thermosetting ink for resist use is partially applied by a technique, such as a screen printing technique or the like, is thermoset and a weatherable, chemical- resistant, insulative and solder-resistant first resist film 3 is formed on wiring circuits 2b on the board 1, on which the wiring patterns exist in a high density. An exposure and developing type resist is applied and semicured on the whole surface of the board 1. An exposure is performed via a mask and thereafter, the mask is removed and the resist is developed. The resist on the parts 2a is removed, the resist other than the removed resist is completely curd by a posture process and a second resist layer 4 is formed. Accordingly, the wiring circuits 2b can be protected from contamination, disconnection and the like by the wiring board and it becomes possible that components are respectively soldered reliably on the parts 2a.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、微細なレジストパターンを精密に形成し得る
配線基板の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a wiring board in which a fine resist pattern can be precisely formed.

〔発明の概要〕[Summary of the invention]

本発明は、配線パターンの形成された基板上に熱硬化性
の第1のレジストによって部分的にレジスト層を形成し
たのち、露光現像型の第2のレジストによって上記配線
パターンに応したレジスト層を形成することにより、精
密で且つ安定性の高いレジスト層の形成を可能にし、配
線回路の密度。
In the present invention, a resist layer is partially formed using a thermosetting first resist on a substrate on which a wiring pattern is formed, and then a resist layer corresponding to the wiring pattern is formed using an exposure and development type second resist. This enables the formation of a precise and highly stable resist layer, increasing the density of wiring circuits.

精度を高めることができる配線基板の製造方法を提供し
ようとするものである。
The present invention aims to provide a method for manufacturing a wiring board that can improve precision.

(従来の技術〕 配線基板において、配線回路の形成された基板上に形成
されるレジスト層は、印刷配線に浸漬法で部品をはんだ
付けする際に、不必要な部分にはんだが付くのを防ぐた
めに形成される絶縁被膜である。このレジスト層は耐は
んだ性とともに配線回路を断線や汚染から保護する効果
も有しており、信転性の高い配線基板を形成する上で不
可欠である。
(Prior Art) In a wiring board, a resist layer formed on a board on which a wiring circuit is formed is used to prevent solder from adhering to unnecessary parts when soldering components to printed wiring using the dip method. This resist layer has solder resistance as well as the effect of protecting wiring circuits from disconnection and contamination, and is essential for forming wiring boards with high reliability.

最近、配線基板においては、益々配線回路の高密度化、
高精度化が進み、それに伴なって、このようなレジスト
層にも微細なパターンが要求されるようになってきた。
Recently, in wiring boards, the density of wiring circuits has become higher and higher.
As precision increases, finer patterns are also required for such resist layers.

このため、微細なパターンのレジスト層が精密に形成で
き、しかもその形成されたレジスト層がめつき液にさら
されたり、高湿度な環境に置かれても配線回路上に安定
に維持され得るレジスト層の形成方法の開発が、配線基
板の信顧性、高精度性を維持する上で必要になってきて
いる。
For this reason, a resist layer with a fine pattern can be precisely formed, and the resist layer can be stably maintained on the wiring circuit even if the formed resist layer is exposed to a plating solution or placed in a high humidity environment. It has become necessary to develop a method for forming wiring boards in order to maintain reliability and high precision of wiring boards.

ところで、これまでこのようなレジスト層を基板上に形
成する方法としては、マスキング部分にゾルを形成した
メノンユ状のスクリーンを用いて熱硬化性のレジストを
基板上に印刷するスクリーン印刷法が採用されてきた。
By the way, as a method to form such a resist layer on a substrate so far, a screen printing method has been adopted in which a thermosetting resist is printed on the substrate using a menonue-shaped screen with sol formed on the masking part. It's here.

このスクリーン印刷法で使用される熱硬化性のレジスト
は化学的に安定であるため、この方法によれば耐候性、
耐薬品性、絶縁性に優れたレジスト層を形成することが
できる。
The thermosetting resist used in this screen printing method is chemically stable, so this method provides weather resistance,
A resist layer with excellent chemical resistance and insulation properties can be formed.

しかしながら、このスクリーン印刷法で、微細なパター
ンを形成しようとすると、スクリーンからレジスト用の
インクをローラーで押し出す際にスクリーンが歪み、配
線回路とレジストの位置合セが困難であったり、レジス
ト層が配線回路上に正確に形成されなかったりしていた
。また、スクリーンに形成されたマスキング用のゾル下
部にレジストが回り込み、レジスト層が滲んでしまう等
の不都合が生していた。このため、この方法では、微細
なパターンのレジスト層を形成することができず、高密
度な配線基板を製造する場合には対応できなかった。
However, when attempting to form fine patterns using this screen printing method, the screen is distorted when the resist ink is pushed out from the screen with a roller, making it difficult to align the wiring circuit and the resist, or the resist layer is distorted. Sometimes they were not formed accurately on the wiring circuit. Further, the resist wraps around the lower part of the masking sol formed on the screen, causing problems such as the resist layer bleeding. Therefore, this method cannot form a resist layer with a fine pattern, and cannot be used to manufacture a high-density wiring board.

そこで、スクリーン印刷性以外のレジスト層の形成方法
として、感光性のレジストを使用するフォ(・法が最近
採用されるようになってきている。
Therefore, as a method for forming a resist layer other than screen printing, the photo-method using a photosensitive resist has recently been adopted.

この方法は、スクリーン法、ローラーコート法、スプレ
ー法、カーテンコーター法により感光性のレジストを基
板全面に塗布し、レジスト層形成部分のみを選択的に露
光し光硬化させる方法である。
This method is a method in which a photosensitive resist is applied to the entire surface of a substrate by a screen method, a roller coating method, a spray method, or a curtain coater method, and only the portion where the resist layer is to be formed is selectively exposed to light and photocured.

この方法は、パターン形成にスクリーンやローラーを使
用しないので、レジスト層にずれや滲みがなく、上述の
スクリーン印刷法よりも微細なレジストパターンを形成
することが可能である。
Since this method does not use a screen or roller for pattern formation, the resist layer does not shift or bleed, and it is possible to form a finer resist pattern than the above-mentioned screen printing method.

しかし、この方法で使用される感光性レジストは、紫外
線によって部分硬化するための反応性の高い構造を有し
ており、化学的に不安定である。
However, the photosensitive resist used in this method has a highly reactive structure that is partially cured by ultraviolet rays, and is chemically unstable.

したがって、この方法で形成されるレジスト層は耐候性
、耐薬品性、絶縁性等に乏しく、例えばレジスト層形成
後にめっきを行おうとすると問題が生ずる広れがある。
Therefore, the resist layer formed by this method is poor in weather resistance, chemical resistance, insulation, etc., and has a wide spread that causes problems if, for example, plating is attempted after the resist layer is formed.

〔発明が解決しようとする課題] このように、従来の技術でレジスト層を形成しようとす
ると、微細なパターンが精密に形成されなかったり、ま
た微細なパターンは形成されるがレジスト層の安定性が
十分でなかったり等問題が多く、配線回路の高密度化、
高精度化に限界がある。
[Problems to be Solved by the Invention] As described above, when attempting to form a resist layer using conventional techniques, fine patterns may not be formed accurately, or fine patterns may be formed but the stability of the resist layer may not be stable. There are many problems such as insufficient wiring, high density wiring circuits,
There is a limit to high precision.

そこで本発明は、このような従来の実情を鑑みて提案さ
れたものであって、レジスト層の精密性。
Therefore, the present invention was proposed in view of such conventional circumstances, and it is important to improve the precision of the resist layer.

安定性を高めることにより、精度及び密度の高い回路形
成が可能な配線基板の製造方法を提供することを目的と
する。
It is an object of the present invention to provide a method for manufacturing a wiring board that enables circuit formation with high accuracy and density by increasing stability.

上述の目的を達成するために本発明の配線基板の製造方
法は、基板上に配線パターンを形成し、熱硬化性の第1
のレジストを部分的に塗布した後、露光現像型の第2の
レジストを全面に塗布し、上記配線パターンに応じてこ
の第2のレジストを露光現像することを特徴とする。
In order to achieve the above-mentioned object, the method for manufacturing a wiring board of the present invention includes forming a wiring pattern on a substrate, and forming a thermosetting first
After partially applying the resist, a second resist of an exposure and development type is applied to the entire surface, and the second resist is exposed and developed in accordance with the wiring pattern.

〔作用〕[Effect]

本発明の配線基板の製造方法においては、配線パターン
の形成された基板上に熱硬化性の第1のレジストを部分
的に塗布するので、第1のレジストが塗布された基板上
には、耐候性、耐薬品性。
In the method for manufacturing a wiring board of the present invention, the thermosetting first resist is partially applied onto the substrate on which the wiring pattern is formed, so that the weather-resistant chemical resistance.

絶縁性を備えた耐はんだ性レジスト層が形成゛される6
また、第1のレジストを塗布した後、露光現像型の第2
のレジストを全面に塗布し、上記配線パターンに応じて
この第2のレジストを露光現像するので、基板全面には
、耐はんだ性レジスト層が配線パターンに応して精密に
形成される。
A solder-resistant resist layer with insulation properties is formed 6
In addition, after applying the first resist, a second resist of exposure and development type is applied.
A resist is applied to the entire surface of the substrate, and this second resist is exposed and developed in accordance with the wiring pattern, so that a solder-resistant resist layer is precisely formed on the entire surface of the substrate in accordance with the wiring pattern.

〔課題を解決するための手段〕[Means to solve the problem]

〔実施例〕 以下、本発明の具体的な実施例について、図面を参照し
ながら説明する。
[Example] Hereinafter, specific examples of the present invention will be described with reference to the drawings.

まず、配線基板を製造するには、絶縁性の基板(1)に
銅箔をラミネートする。そして、銅箔上に所望の配線パ
ターンに応してエツチングレジストを形成し、さらに第
1図A及び第1図Bで示すように工、チングを行って、
所定の接続端子部(2a)及び配線回路(2b)からな
る配線パターン(2)を形成する。なお、このときエツ
チングレジストは通常のフォトリソ技術によってバター
ニングすればよく、また銅箔のエツチングの手法も湿式
エツチング、ドライエツチング等任意である。
First, to manufacture a wiring board, copper foil is laminated onto an insulating board (1). Then, an etching resist is formed on the copper foil according to a desired wiring pattern, and etching is performed as shown in FIGS. 1A and 1B.
A wiring pattern (2) consisting of a predetermined connection terminal portion (2a) and a wiring circuit (2b) is formed. At this time, the etching resist may be patterned by ordinary photolithography, and the copper foil may be etched by any method such as wet etching or dry etching.

このようにして基板(1)上に配線パターン(2)を形
成した後、さらにこの基板(1)上番こレジスト層を形
成する。
After the wiring pattern (2) is thus formed on the substrate (1), a resist layer is further formed on the substrate (1).

レジスト層の形成に際しては、第2図A及び第2図Bで
示すように、まず印刷精度を考慮して接続端子部(2a
)周辺を確実に除き得る範囲で基板(1)面に第1のレ
ジストとなる熱硬化性のレジスト用のインクをスクリー
ン印刷等の手法で部分的に塗布し、これを熱硬化して第
1のレジスト層(3)を形成する。すなわち、第2図B
で示すように配線パターンが高密度に存在する配線回路
(2b)上に第1のレジスト層が形成される。なお、こ
こで使用される熱硬化性のレジスト用インクは、たとえ
ばエポキシ樹脂のような、通常熱硬化性レジスト用イン
クとして使用されているものであればいずれでもよく、
特に限定されるものではない。
When forming the resist layer, as shown in FIGS. 2A and 2B, first, the connection terminal portion (2a
) A thermosetting resist ink that will become the first resist is partially applied to the surface of the substrate (1) by a method such as screen printing to the extent that the periphery can be reliably removed, and this is thermoset to form the first resist. A resist layer (3) is formed. That is, Figure 2B
As shown in , a first resist layer is formed on a wiring circuit (2b) in which wiring patterns are present at high density. The thermosetting resist ink used here may be any ink that is normally used as a thermosetting resist ink, such as epoxy resin.
It is not particularly limited.

次に、第2のレジストとなる露光現像型のレジストを基
板(1)全面に塗布しセミキュアーする。
Next, an exposure and development type resist serving as a second resist is applied to the entire surface of the substrate (1) and semi-cured.

次いでマスクを介して露光後、マスクを除去し、前記レ
ジストを現像する。そして第3図A及び第3図Bに示す
ように接続端子部(2a)上のレジストを除去し、ポス
トキュアー工程によって完全に硬化して、第2のレジス
ト層(4)を形成する。すなわち、第3図Bで示すよう
に、第1のレジスト層の上にさらに第2のレジスト層が
接続端子部を除いた基板全面に形成される。なお、ここ
で、露光現像型のレジストとしてはポジティブ型であっ
てもネガティブ型であってもいずれでもよい。本実施例
では、紫外線照射によって硬化する名ガティブ型レジス
トを使用した。
Next, after exposure through a mask, the mask is removed and the resist is developed. Then, as shown in FIGS. 3A and 3B, the resist on the connection terminal portion (2a) is removed and completely cured by a post-cure process to form a second resist layer (4). That is, as shown in FIG. 3B, a second resist layer is further formed on the first resist layer over the entire surface of the substrate except for the connection terminal portions. Note that here, the exposure and development type resist may be either a positive type or a negative type. In this example, a negative type resist that is cured by ultraviolet irradiation was used.

このように製造された配線基板においては、接続端子部
(2a)周辺を除いた部分、すなわち配線回路(2b)
が高密度に存在する部分には、耐候性、耐薬品性5絶縁
性を備えた耐はんだ性の第1のレジスト層(3)が形成
された。また、基板(1)全面には配線パターン(2)
に応して耐はんだ性の第2のレジスト層(4)が精密な
形状の開口部(4a)を有して形成された。したがって
、このように製造された配線基板は、配線回路(2b)
を汚染、断線等から保護することができ、また、接続端
子部(2a)に確実に部品をはんだ付けすることが可能
となることが示された。
In the wiring board manufactured in this way, the portion excluding the area around the connection terminal portion (2a), that is, the wiring circuit (2b)
A solder-resistant first resist layer (3) having weather resistance, chemical resistance, and insulation properties was formed in the area where . In addition, there is a wiring pattern (2) on the entire surface of the board (1).
Accordingly, a solder-resistant second resist layer (4) was formed with precisely shaped openings (4a). Therefore, the wiring board manufactured in this way has a wiring circuit (2b)
It has been shown that it is possible to protect the terminal from contamination, disconnection, etc., and it is also possible to reliably solder components to the connection terminal portion (2a).

また、さらに、本発明に係る製造方法においては、接続
端子部(2a)にめっきを施す必要があれば、第1のレ
ジスト層(3)形成後に、めっき処理を行うこともでき
る。レジスト層形成前のめっき処理は、配線パターン(
2)の横方向にもめっきが析出してしまい、また配線回
路(2b)が高密度に形成されている部分において配線
同志の絶縁性が低下する可能性か高い。したがって、こ
の第1のレジスト層形成後にめっき処理を行えば第1の
レジスト層(3)は上述の如く耐薬品性、耐候性、絶縁
性に優れているので、配線回路の精度を低下させること
なくめっきを施すことが可能である。
Furthermore, in the manufacturing method according to the present invention, if it is necessary to plate the connection terminal portion (2a), the plating treatment can be performed after forming the first resist layer (3). The plating process before forming the resist layer is performed on the wiring pattern (
2), there is a high possibility that the plating will be deposited in the lateral direction, and that the insulation between the wirings will deteriorate in the area where the wiring circuits (2b) are formed in high density. Therefore, if the plating treatment is performed after the formation of this first resist layer, the first resist layer (3) has excellent chemical resistance, weather resistance, and insulation properties as described above, so that the accuracy of the wiring circuit will not be reduced. It is possible to apply plating without any need for plating.

〔発明の効果) 以上の説明からも明らかなように、本発明の配線基板の
製造方法においては、配線パターンの形成された基板上
に熱硬化性の第1のレジストを部分的に塗布するので、
基板上の大部分が、耐薬品性、耐めっき性を備えた耐は
んだ性レジスト層によって保護される。また、第1のレ
ジストを塗布した後、露光現像型の第2のレジストを全
面に塗布し、上記配線パターンに応じてこの第2のレジ
ストを露光現像するので、精密な開口部形状を有する耐
はんだ性レジスト層が配線パターンに応して形成される
[Effects of the Invention] As is clear from the above explanation, in the method for manufacturing a wiring board of the present invention, the thermosetting first resist is partially applied on the board on which the wiring pattern is formed. ,
Most of the substrate is protected by a solder-resistant resist layer that has chemical resistance and plating resistance. In addition, after applying the first resist, a second resist of an exposure and development type is applied to the entire surface, and this second resist is exposed and developed according to the wiring pattern, so that the resistor has a precise opening shape. A solderable resist layer is formed according to the wiring pattern.

したがって、本発明によれば、信転性が高く、しかも高
精度な配線基板を製造することが可能となる。
Therefore, according to the present invention, it is possible to manufacture a wiring board with high reliability and high precision.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3回は本発明を適用した一実施例を工程順
に示すものであり、第1図Aは配線パターンの形成工程
を示す要部概略平面図、第1図Bは第1図AのA−A線
における要部概略断面図、第2図Aは第1のレジスト層
形成工程を示す要部概略平面図、第2図Bは第2図Aの
A−A線における要部概略断面図、第3図Aは第2のレ
ジスト層の形成工程を示す要部概略平面図、第3図Bは
第3図AのA−Awaにおける要部概略断面図をそれぞ
れ示す。 2・・・配線パターン 3・・・第1のレジスト層 4・・・第2のレジスト層
1 to 3 show an embodiment to which the present invention is applied in the order of steps, FIG. 1A is a schematic plan view of the main part showing the process of forming a wiring pattern, and FIG. 1B is a diagram of FIG. FIG. 2A is a schematic plan view of the main part showing the first resist layer forming step, and FIG. 2B is a main part taken along the A-A line of FIG. 2A. A schematic cross-sectional view, FIG. 3A is a schematic plan view of a main part showing the process of forming the second resist layer, and FIG. 3B is a schematic cross-sectional view of a main part along A-Awa in FIG. 3A. 2... Wiring pattern 3... First resist layer 4... Second resist layer

Claims (1)

【特許請求の範囲】  基板上に配線パターンを形成し、熱硬化性の第1のレ
ジストを部分的に塗布した後、 露光現像型の第2のレジストを全面に塗布し、上記配線
パターンに応じてこの第2のレジストを露光現像するこ
とを特徴とする配線基板の製造方法。
[Claims] After forming a wiring pattern on a substrate and partially applying a first thermosetting resist, a second resist of an exposure and development type is applied to the entire surface, and a wiring pattern is formed according to the wiring pattern. A method for manufacturing a wiring board, comprising exposing and developing a second resist of the lever.
JP20146090A 1990-07-31 1990-07-31 Manufacturing method of wiring board Expired - Fee Related JP2897365B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20146090A JP2897365B2 (en) 1990-07-31 1990-07-31 Manufacturing method of wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20146090A JP2897365B2 (en) 1990-07-31 1990-07-31 Manufacturing method of wiring board

Publications (2)

Publication Number Publication Date
JPH0487392A true JPH0487392A (en) 1992-03-19
JP2897365B2 JP2897365B2 (en) 1999-05-31

Family

ID=16441459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20146090A Expired - Fee Related JP2897365B2 (en) 1990-07-31 1990-07-31 Manufacturing method of wiring board

Country Status (1)

Country Link
JP (1) JP2897365B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108449A (en) * 2004-10-06 2006-04-20 Nitto Denko Corp Wiring circuit board and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108449A (en) * 2004-10-06 2006-04-20 Nitto Denko Corp Wiring circuit board and its manufacturing method
JP4588405B2 (en) * 2004-10-06 2010-12-01 日東電工株式会社 Wiring circuit board and manufacturing method thereof

Also Published As

Publication number Publication date
JP2897365B2 (en) 1999-05-31

Similar Documents

Publication Publication Date Title
JP3666955B2 (en) Method for manufacturing flexible circuit board
KR19990072084A (en) Solder Masks for Printed Circuit Board Manufacturing
JP3624423B2 (en) Printed wiring board and manufacturing method thereof
KR100351923B1 (en) method for fabricating PCB
JP2897365B2 (en) Manufacturing method of wiring board
JP2586745B2 (en) Manufacturing method of printed wiring board
JPH06268355A (en) Printed wiring board and manufacture thereof
JP2910261B2 (en) Printed wiring board and its manufacturing method
JP2587544B2 (en) Manufacturing method of printed wiring board
JPH03196691A (en) Formation of insulating layer of printed wiring board
JP3185345B2 (en) Printed circuit board manufacturing method
JPH06318774A (en) Manufacturing method of printed-wiring board
JPH11289151A (en) Surface protection layer forming method for circuit substrate
JPH0567871A (en) Printed-wiring board and manufacture thereof
JPH04326588A (en) Manufacture of printed wiring board
KR950000293B1 (en) Printed wiring board and manufacturing method thereof
JP2003324168A (en) Printed wiring board for mounting semiconductor integrated circuit
JPS586316B2 (en) Manufacturing method of printed wiring board
JPS58210693A (en) Printed circuit board
JPS6334937A (en) Manufacture of film carrier
JPS5821839B2 (en) printed board
JPH0354873B2 (en)
JP2000277900A (en) Manufacture of solder-coated composite circuit board
JPH05243709A (en) Manufacture of printed wiring board
JPH0730233A (en) Manufacture of printed wiring board

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080312

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090312

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees