JPH04326588A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH04326588A JPH04326588A JP9600891A JP9600891A JPH04326588A JP H04326588 A JPH04326588 A JP H04326588A JP 9600891 A JP9600891 A JP 9600891A JP 9600891 A JP9600891 A JP 9600891A JP H04326588 A JPH04326588 A JP H04326588A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- ink
- mask film
- printed wiring
- etching resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000005530 etching Methods 0.000 claims abstract description 22
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052802 copper Inorganic materials 0.000 claims abstract description 8
- 239000010949 copper Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 238000007747 plating Methods 0.000 claims description 7
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims description 2
- 238000007790 scraping Methods 0.000 claims description 2
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000000576 coating method Methods 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 101100205892 Caenorhabditis elegans taf-2 gene Proteins 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000016 photochemical curing Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、印刷配線板の製造方法
に関し、特に高密度の配線回路を有するスルーホール印
刷配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing printed wiring boards, and more particularly to a method for manufacturing through-hole printed wiring boards having high-density wiring circuits.
【0002】0002
【従来の技術】一般に、スルーホール印刷配線板(以下
、T/H PWBと記す)の製造には、図4(a)〜
(d)及び図5(a)〜(d)のごとく、テンティング
工法が多く用いられており、この方法によれば、図4(
a)のごとく、絶縁基板2上に銅めっき層を含む導体層
1とスルーホール1aを形成した絶縁基板2に図4(b
)のごとく、感光性ドライフィルム3aを貼付し、この
上から図4(c)のごとく、第1のマスクフィルム4a
を介して所定の回路パターンを紫外線で焼き付けた後、
図4(d)の如く、現像液で不要部分の感光性ドライフ
ィルム3aを除去する。[Prior Art] Generally, in the production of through-hole printed wiring boards (hereinafter referred to as T/H PWB),
As shown in (d) and Figures 5 (a) to (d), the tenting method is often used, and according to this method, Figure 4 (
As shown in a), a conductive layer 1 including a copper plating layer and a through hole 1a are formed on an insulating substrate 2, and the insulating substrate 2 shown in FIG.
), a photosensitive dry film 3a is attached, and from above, as shown in FIG.
After burning the predetermined circuit pattern with ultraviolet light through
As shown in FIG. 4(d), unnecessary portions of the photosensitive dry film 3a are removed using a developer.
【0003】次に、塩化第2銅溶液などによるエッチン
グ処理を行い図5(a)の導体回路1bを得た後、エッ
チングレジスト5aを剥離除去する。さらに、図5(b
)のごとく、感光性ソルダレジストインク6を全面に塗
布したのち、図5(c)のごとく、所定のソルダレジス
トパターンを有する第2のマスクフィルム4bを用いて
露光焼付けし、最後に、図5(d)の如く、現像処理で
未露光部分の感光性ソルダレジストインク6を溶解除去
して、T/H PWBを得る。Next, an etching process using a cupric chloride solution or the like is performed to obtain the conductor circuit 1b shown in FIG. 5(a), and then the etching resist 5a is peeled off. Furthermore, Fig. 5(b)
), the photosensitive solder resist ink 6 is applied to the entire surface, and then exposed and baked using a second mask film 4b having a predetermined solder resist pattern, as shown in FIG. As shown in (d), the photosensitive solder resist ink 6 in the unexposed areas is dissolved and removed by a development process to obtain a T/H PWB.
【0004】尚、図5(a)及び図5(a)からエッチ
ングレジスト5aを剥離除去したT/H PWBを得
るにはこの他に公知の次のような製造方法がある。[0004] In addition, there are other known manufacturing methods to obtain the T/H PWB from which the etching resist 5a is peeled off and removed as shown in FIGS. 5(a) and 5(a).
【0005】(1)穴埋め工法
(2)パネル−パターン工法
(3)パターンめっき工法
(4)ポジ型感光性樹脂塗膜の電着コーティング工法(
5)ネガ型感光性樹脂塗膜の電着コーティング工法(6
)TAF−2工法
(7)AP−2工法
(8)フルアディティブ工法(1) Hole-filling method (2) Panel-pattern method (3) Pattern plating method (4) Electrodeposition coating method for positive photosensitive resin coating (
5) Electrodeposition coating method for negative photosensitive resin coating (6
) TAF-2 construction method (7) AP-2 construction method (8) Full additive construction method
【発明が解決しようとする課題】しかし、従来のフォト
SR印刷法では、次に述べる課題があった。[Problems to be Solved by the Invention] However, the conventional photo SR printing method has the following problems.
【0006】すなわち、フォトSR印刷法では、ソルダ
レジストインクを選択的に残存させる為にマスクフィル
ムを用い光硬化させる工程で絶縁基板に所定の回路パタ
ーンを形成した後マスクフィルムを位置合わせするため
、絶縁基板の寸法伸縮のばらつきにより回路パターンと
ソルダレジストパターンとの位置不整合が生じ、表面実
装用のパッド部にソルダレジストインクが残存し部品実
装の信頼性が確保できないという課題があった。That is, in the photo SR printing method, a mask film is used to selectively leave solder resist ink, and after forming a predetermined circuit pattern on an insulating substrate in a photocuring process, the mask film is aligned. There was a problem in that positional misalignment between the circuit pattern and the solder resist pattern occurred due to variations in the dimensional expansion and contraction of the insulating substrate, and solder resist ink remained on the pad portion for surface mounting, making it impossible to ensure the reliability of component mounting.
【0007】更に、近年、配線回路が高密度化するに伴
い、SMT化が進み高位置精度の印刷配線板の製造が困
難になってきた。Furthermore, in recent years, with the increase in the density of wiring circuits, the use of SMT has progressed, making it difficult to manufacture printed wiring boards with high positional accuracy.
【0008】本発明の目的は、部品実装の信頼性が高く
、SMT高位置精度印刷配線板に対応できる印刷配線板
の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a printed wiring board that has high component mounting reliability and is compatible with SMT high positional precision printed wiring boards.
【0009】[0009]
【課題を解決するための手段】本発明は、スルーホール
を有する印刷配線板に於て、銅張り絶縁基板に穴あけす
る工程と、前記絶縁基板の穴及び該絶縁基板表面に銅め
っき層を形成する工程と、該銅めっき層表面に感光性ド
ライフィルムを熱圧着し所定の回路パターンを有する第
1のマスクフィルムを用いて露光焼付けした後、更に感
光性ドライフィルムを重ねて熱圧着する工程と、前記第
1のマスクィルムの回路パターンの内スルーホールラン
ドとパッド部のみのパターンを有する第2のマスクフィ
ルムを用いて露光焼付けする工程と、現像により未露光
部分の前記感光性ドライフィルムを選択的に除去しエッ
チングレジストを形成する工程と、露出した銅部分をエ
ッチングで除去する工程と、更に残存する前記エッチン
グレジストの内、上層部分のエッチングンレジストのみ
を選択的に除去し、下層部分のエッチングレジストを残
存させる工程と、感光性ソルダレジストインクを基板の
全面に塗布し、乾燥させる工程と、エッチングレジスト
上に重ねられた部分の前記ソルダレジストインクを選択
的に削り除去する工程と、紫外線を全面に照射し焼付け
する工程と、残存する前記エッチングレジストを除去す
る工程とを含む。[Means for Solving the Problems] The present invention provides a printed wiring board having through holes, including the step of drilling holes in a copper-clad insulating substrate, and forming a copper plating layer on the holes in the insulating substrate and on the surface of the insulating substrate. A step of thermocompression bonding a photosensitive dry film on the surface of the copper plating layer, exposing and baking using a first mask film having a predetermined circuit pattern, and then further superimposing a photosensitive dry film and bonding the photosensitive dry film by thermocompression. , a step of exposing and baking using a second mask film having a pattern of only through-hole lands and pad portions of the circuit pattern of the first mask film, and selectively removing the unexposed portions of the photosensitive dry film by developing. a step of removing the exposed copper portion by etching, and a step of selectively removing only the upper layer of the remaining etching resist and etching the lower layer. A step of leaving the resist remaining, a step of applying photosensitive solder resist ink to the entire surface of the substrate and drying it, a step of selectively scraping away the solder resist ink in the portion overlaid on the etching resist, and a step of applying ultraviolet rays. The method includes a step of irradiating and baking the entire surface, and a step of removing the remaining etching resist.
【0010】0010
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments Next, embodiments of the present invention will be described with reference to the drawings.
【0011】図1(a)〜(d),図2(a)〜(d)
及び図3(a)〜(c)は本発明の一実施例を説明する
工程順に示した断面図である。FIGS. 1(a) to (d), FIGS. 2(a) to (d)
3(a) to 3(c) are sectional views showing an embodiment of the present invention in the order of steps.
【0012】まず、図1(a)のごとく、公知のパネル
めっき工法により銅張り絶縁基板2にめっきにて導体層
1とスルーホール1aを形成した後、図1(b)のよう
に感光性ドライフィルム3aを1〜4m/分,80〜1
20℃,2〜4kg/cm2 で絶縁基板2表面に熱圧
着させる。First, as shown in FIG. 1(a), a conductive layer 1 and through holes 1a are formed on a copper-clad insulating substrate 2 by plating using a known panel plating method, and then a photosensitive layer 1a is formed as shown in FIG. 1(b). Dry film 3a at 1-4 m/min, 80-1
It is thermocompression bonded to the surface of the insulating substrate 2 at 20° C. and 2 to 4 kg/cm 2 .
【0013】次に、図1(c)のごとく、所定の回路パ
ターンを有する配線回路印刷用の第1のマスクフィルム
4aを感光性ドライフィルム3a上に当接し、1平方セ
ンチメートル当り50〜300ミリジュールの紫外線を
照射し所定の回路パターンを印刷した後、図1(d)の
ごとく、再度1〜4m/分,50〜80℃,2〜4kg
/cm2 で感光性ドライフィルム3bを重ねて熱圧着
する。Next, as shown in FIG. 1(c), a first mask film 4a for wiring circuit printing having a predetermined circuit pattern is brought into contact with the photosensitive dry film 3a, and 50 to 300 millijoules per square centimeter is applied. After irradiating with ultraviolet rays and printing a predetermined circuit pattern, as shown in Figure 1(d), 1~4m/min, 50~80℃, 2~4kg
The photosensitive dry film 3b is overlapped and bonded by thermocompression at a thickness of /cm2.
【0014】更に、図2(a)のごとく、第1のマスク
フィルムの回路パターンの内、スルーホールランドとパ
ッド部のみのパターンを有するソルダレジストインク印
刷用の第2のマスクフィルム4cを用いて、露光焼付け
した後、図2(b)のように、20〜40℃の1〜2%
の炭酸ナトリウム水溶液で未露光部分の感光性ドライフ
ィルム3a,3bを除去しエッチングレジスト5a,5
bを形成させて、図2(c)のように、露出した銅部分
を塩化第二銅溶液などによるエッチング処理を行い配線
回路1bを得た後、図2(d)のごとく、30〜50℃
の1〜2%の水酸化ナトリウム水溶液で上層部分のエッ
チングレジスト5bのみを除去する。Furthermore, as shown in FIG. 2(a), a second mask film 4c for printing solder resist ink having a pattern of only through-hole lands and pad portions in the circuit pattern of the first mask film is used. , After exposure and baking, as shown in Figure 2(b), 1-2% at 20-40℃
The unexposed portions of the photosensitive dry films 3a, 3b are removed with a sodium carbonate aqueous solution of
b, and as shown in FIG. 2(c), the exposed copper portion is etched with a cupric chloride solution to obtain a wiring circuit 1b. ℃
Only the upper layer portion of the etching resist 5b is removed using a 1 to 2% aqueous sodium hydroxide solution.
【0015】その後、図3(a)のように、全面に感光
性ソルダレジストインク6を塗布し、スキージングによ
り、図3(b)のごとく、エッチングレジスト5a上の
ソルダレジストインク6を除去し、全面に紫外線を照射
し焼付けて、ソルダレジストインク6を硬化させる。こ
の際、エッチングレジスト5a上のソルダレジストイン
ク6を除去する方法には、ソルダレジストインク6を硬
化させた後、バフ研磨材により研磨除去してもよい。最
後に、図3(c)のごとく、30〜50℃の3〜4%の
水酸化ナトリウム水溶液で、残存しているエッチングレ
ジスト5aを除去して本実施例の印刷配線板を得る。Thereafter, as shown in FIG. 3(a), a photosensitive solder resist ink 6 is applied to the entire surface, and the solder resist ink 6 on the etching resist 5a is removed by squeezing as shown in FIG. 3(b). , the entire surface is irradiated with ultraviolet rays and baked to harden the solder resist ink 6. At this time, the solder resist ink 6 on the etching resist 5a may be removed by curing the solder resist ink 6 and then polishing it with a buffing material. Finally, as shown in FIG. 3(c), the remaining etching resist 5a is removed with a 3-4% sodium hydroxide aqueous solution at 30-50° C. to obtain the printed wiring board of this example.
【0016】[0016]
【発明の効果】以上から明らかなように本発明によれば
、2層のエッチングレジストを選択的に除去することに
より次の効果がある。As is clear from the above, according to the present invention, the following effects can be achieved by selectively removing two layers of etching resist.
【0017】(1)配線回路とソルダレジストパターン
を、絶縁基板の寸法伸縮の影響を排除して形成できる為
、高位置精度の印刷配線板がえられる。(1) Since the wiring circuit and the solder resist pattern can be formed while eliminating the influence of dimensional expansion and contraction of the insulating substrate, a printed wiring board with high positional accuracy can be obtained.
【0018】(2)SMT高位置精度印刷配線板がえら
れる。(2) An SMT high positional precision printed wiring board is obtained.
【図面の簡単な説明】[Brief explanation of the drawing]
【図1】本発明の一実施例を説明する工程順に示した断
面図である。FIG. 1 is a cross-sectional view showing an example of the present invention in the order of steps.
【図2】本発明の一実施例を説明する工程順に示した断
面図である。FIG. 2 is a cross-sectional view showing an example of the present invention in the order of steps.
【図3】本発明の一実施例を説明する工程順に示した断
面図である。FIG. 3 is a cross-sectional view showing an example of the present invention in the order of steps.
【図4】従来の印刷配線板の製造方法の一例を説明する
工程順に示した断面図である。FIG. 4 is a cross-sectional view showing an example of a conventional printed wiring board manufacturing method in order of steps.
【図5】従来の印刷配線板の製造方法の一例を説明する
工程順に示した断面図である。FIG. 5 is a cross-sectional view showing an example of a conventional printed wiring board manufacturing method in order of steps.
1 導体層
1a スルーホール
1b 配線回路
1c スルーホールランド
2 絶縁基板
3a,3b 感光性ドライフィルム4a,4c
マスクフィルム1 Conductor layer 1a Through hole 1b Wiring circuit 1c Through hole land 2 Insulating substrate 3a, 3b Photosensitive dry film 4a, 4c
mask film
Claims (1)
て、銅張り絶縁基板に穴あけする工程と、前記絶縁基板
の穴及び該絶縁基板表面に銅めっき層を形成する工程と
、該銅めっき層表面に感光性ドライフィルムを熱圧着し
所定の回路パターンを有する第1のマスクフィルムを用
いて露光焼付けした後、更に感光性ドライフィルムを重
ねて熱圧着する工程と、前記第1のマスクィルムの回路
パターンの内スルーホールランドとパッド部のみのパタ
ーンを有する第2のマスクフィルムを用いて露光焼付け
する工程と、現像により未露光部分の前記感光性ドライ
フィルムを選択的に除去しエッチングレジストを形成す
る工程と、露出した銅部分をエッチングで除去する工程
と、更に残存する前記エッチングレジストの内、上層部
分のエッチングンレジストのみを選択的に除去し、下層
部分のエッチングレジストを残存させる工程と、感光性
ソルダレジストインクを基板の全面に塗布し、乾燥させ
る工程と、エッチングレジスト上に重ねられた部分の前
記ソルダレジストインクを選択的に削り除去する工程と
、紫外線を全面に照射し焼付けする工程と、残存する前
記エッチングレジストを除去する工程とを含むことを特
徴とする印刷配線板の製造方法。1. In a printed wiring board having through holes, the steps include: drilling a hole in a copper-clad insulating substrate; forming a copper plating layer on the hole in the insulating substrate and on the surface of the insulating substrate; A step of thermocompression bonding a photosensitive dry film on the surface and exposing and baking using a first mask film having a predetermined circuit pattern, and then further stacking and thermocompression bonding a photosensitive dry film, and a circuit of the first mask film. A process of exposing and baking using a second mask film having a pattern of only through-hole lands and pad portions in the pattern, and selectively removing the photosensitive dry film in unexposed areas by development to form an etching resist. a step of removing the exposed copper portion by etching, a step of selectively removing only the upper layer of the etching resist of the remaining etching resist and leaving the lower layer of the etching resist; a step of applying a transparent solder resist ink to the entire surface of the substrate and drying it; a step of selectively scraping off the solder resist ink in the portion overlaid on the etching resist; and a step of irradiating the entire surface with ultraviolet rays and baking it. . A method for manufacturing a printed wiring board, comprising the steps of: removing the remaining etching resist.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9600891A JPH04326588A (en) | 1991-04-26 | 1991-04-26 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9600891A JPH04326588A (en) | 1991-04-26 | 1991-04-26 | Manufacture of printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04326588A true JPH04326588A (en) | 1992-11-16 |
Family
ID=14153153
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9600891A Pending JPH04326588A (en) | 1991-04-26 | 1991-04-26 | Manufacture of printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04326588A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100734051B1 (en) * | 2006-04-21 | 2007-07-02 | 한국단자공업 주식회사 | Via-hole choke preventing method for printed circuit board |
JP2014191318A (en) * | 2013-03-28 | 2014-10-06 | Asahi Kasei E-Materials Corp | Method for forming resist pattern |
JP2018005250A (en) * | 2017-09-21 | 2018-01-11 | 旭化成株式会社 | Method for forming resist pattern |
-
1991
- 1991-04-26 JP JP9600891A patent/JPH04326588A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100734051B1 (en) * | 2006-04-21 | 2007-07-02 | 한국단자공업 주식회사 | Via-hole choke preventing method for printed circuit board |
JP2014191318A (en) * | 2013-03-28 | 2014-10-06 | Asahi Kasei E-Materials Corp | Method for forming resist pattern |
JP2018005250A (en) * | 2017-09-21 | 2018-01-11 | 旭化成株式会社 | Method for forming resist pattern |
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