KR20230152433A - Method of manufacturing printed circuit board with fine pitch - Google Patents
Method of manufacturing printed circuit board with fine pitch Download PDFInfo
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- KR20230152433A KR20230152433A KR1020220052191A KR20220052191A KR20230152433A KR 20230152433 A KR20230152433 A KR 20230152433A KR 1020220052191 A KR1020220052191 A KR 1020220052191A KR 20220052191 A KR20220052191 A KR 20220052191A KR 20230152433 A KR20230152433 A KR 20230152433A
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- KR
- South Korea
- Prior art keywords
- copper foil
- plating layer
- base copper
- hole
- circuit board
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 66
- 238000007747 plating Methods 0.000 claims abstract description 40
- 239000011889 copper foil Substances 0.000 claims abstract description 35
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 33
- 229910052802 copper Inorganic materials 0.000 claims abstract description 31
- 239000010949 copper Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 7
- 239000000945 filler Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 2
- 238000003889 chemical engineering Methods 0.000 claims 1
- 238000005553 drilling Methods 0.000 claims 1
- 239000000654 additive Substances 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000000996 additive effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- RYGMFSIKBFXOCR-AHCXROLUSA-N copper-60 Chemical compound [60Cu] RYGMFSIKBFXOCR-AHCXROLUSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/09—Treatments involving charged particles
- H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
본 발명은 CCL 코어의 베이스 동박 위에 니켈 도금을 피복해서 후속 동도금 식각 단계에서 베이스 동박이 식각되지 아니하도록 하는 데 기술적 특징이 있다. 이와 같이 외층 표면에 남아 있는 베이스 동박을 바탕으로 MSAP(modified semi-additive process)을 진행할 수 있게 된다.The present invention has a technical feature in that it covers the base copper foil of the CCL core with nickel plating to prevent the base copper foil from being etched in the subsequent copper plating etching step. In this way, MSAP (modified semi-additive process) can be performed based on the base copper foil remaining on the outer layer surface.
Description
본 발명은 회로기판(printed circuit board; PCB) 제조방법에 관한 것으로, 특히 미세회로기판(fine pitch circuit board) 가공을 위한 인쇄회로기판 제조 공법에 관한 것이다.The present invention relates to a method of manufacturing a printed circuit board (PCB), and particularly to a method of manufacturing a printed circuit board for processing a fine pitch circuit board.
전자부품의 고밀도화에 따라 인쇄회로기판(PCB) 표면 처리에 관한 기술이 다양해지고 있다. 고밀도화되어가고 있는 PCB 제품들의 시대적 요구에 따라 회로가 점점 미세하게 변화되고 있다.As the density of electronic components increases, technologies for printed circuit board (PCB) surface treatment are becoming more diverse. In accordance with the needs of the times for PCB products with increasing density, circuits are changing more and more minutely.
일반적으로 인쇄회로기판에 회로를 형성하기 위해서는, 동박을 선택적으로 식각해서 회로패턴을 구현하는 텐팅 공법(tenting process), 또는 회로패턴을 구현한 마스크를 기판 위에 올려놓고 동도금을 진행해서 마스크 패턴에 따라 회로를 구현하는 부가공법(additive process) 등이 적용된다. In general, to form a circuit on a printed circuit board, a tenting process is used to implement a circuit pattern by selectively etching copper foil, or a mask embodying a circuit pattern is placed on the board and copper plating is performed according to the mask pattern. Additive processes to implement the circuit are applied.
도1 및 도2는 각각 종래기술에 따른 텐팅공법과 부가공법의 양호한 실시예를 설명한 도면이다. 도1을 참조하여 텐팅공법을 설명하면, 패턴 형성된 코어에 CCL(copper-cladded laminate)을 라미네이션하고 비아를 형성한 후, 동도금을 진행한다. 그리고 나면, 드라이필름(D/F)를 밀착하고 노광, 현상 등의 이미지 공정을 진행해서 회로패턴을 형성하여 노출된 동박을 식각함으로써 동박회로를 형성한다.Figures 1 and 2 are diagrams illustrating preferred embodiments of the tenting method and the additional processing method according to the prior art, respectively. When explaining the tenting method with reference to Figure 1, CCL (copper-cladded laminate) is laminated to the patterned core, vias are formed, and copper plating is performed. Then, dry film (D/F) is adhered closely, image processes such as exposure and development are performed to form a circuit pattern, and the exposed copper foil is etched to form a copper foil circuit.
도2를 참조하여 부가공법을 설명하면, 패턴 형성된 코어에 CCL(copper-cladded laminate)을 라미네이션하고 비아를 형성한 후, 드라이필름(D/F)를 밀착하고 노광, 현상 등의 이미지 공정을 진행해서 회로패턴을 형성한 후, 노출된 베이스 동박 위에 동도금을 진행해서 회로를 형성한다. When explaining the additional processing method with reference to Figure 2, CCL (copper-cladded laminate) is laminated to the patterned core and vias are formed, dry film (D/F) is adhered, and image processes such as exposure and development are performed. After forming the circuit pattern, copper plating is performed on the exposed base copper foil to form the circuit.
도1과 도2를 비교해 보면, 동도금된 동박을 식각하여 패턴을 전사하는 공법의 경우에는 식각과정에서 발생하는 측면 패턴손상으로 인하여, 마스크 패턴에 따라 선택적으로 동도금을 올려 회로를 형성하는 공법에 비해 미세회로패턴 구현이 어렵다. Comparing Figures 1 and 2, in the case of the method of transferring the pattern by etching the copper-plated copper foil, damage to the side pattern occurs during the etching process, compared to the method of forming the circuit by selectively applying copper plating according to the mask pattern. It is difficult to implement fine circuit patterns.
따라서 미세회로를 구현하기 위해서는 텐팅 공법보다는 부가공법(Additive process) 또는 세미부가공법(SAP), MSAP(Modified SAP) 등 다양한 변형된 부가공법을 적용하는 것이 바람직하다. 그런데, 현재까지 PTH(punch through hole)을 구비한 FCBGA(Flip Chip Ball Grid Array) 기판의 내층은 에칭 공법으로 패턴을 구현하는 텐팅공법이 적용되고 있으며, 이로 인하여 미세 패턴을 구현하는 것이 용이하지 않다. Therefore, in order to implement a fine circuit, it is desirable to apply various modified additive processing methods such as additive processing, semi-additive processing (SAP), and MSAP (Modified SAP) rather than the tenting method. However, to date, the inner layer of the FCBGA (Flip Chip Ball Grid Array) substrate with PTH (punch through hole) is using a tenting method to create a pattern using an etching method, which makes it difficult to create a fine pattern. .
따라서, 본 발명의 제1 목적은 코어와 외층의 CCL을 PTH를 통해 연결한 인쇄회로기판에 있어서 외층에 미세회로 패턴을 구현하기 위한 제조공법을 제공하는 데 있다. Therefore, the first object of the present invention is to provide a manufacturing method for implementing a fine circuit pattern on the outer layer of a printed circuit board in which the CCL of the core and the outer layer are connected through PTH.
본 발명의 제2 목적은, 상기 제1 목적에 부가하여, 외층의 CCL 베이스 동박을 손상하지 않기 위한 회로기판 제조공법을 제공하는데 있다.The second object of the present invention, in addition to the first object, is to provide a circuit board manufacturing method for preventing damage to the CCL base copper foil of the outer layer.
본 발명의 제3 목적은, 상기 제1 및 제2 목적에 부가하여, 코어와 외층의 CCL을 PTH를 통해 연결한 인쇄회로기판에 있어서 MSAP 공법을 적용한 회로기판 제조공법을 제공하는데 있다. The third object of the present invention, in addition to the first and second objects, is to provide a circuit board manufacturing method applying the MSAP method to a printed circuit board in which the CCL of the core and the outer layer are connected through PTH.
본 발명은 CCL 코어의 베이스 동박 위에 니켈 도금을 피복해서 후속 동도금 식각 단계에서 베이스 동박이 식각되지 아니하도록 하는 데 기술적 특징이 있다. 이와 같이 외층 표면에 남아 있는 베이스 동박을 바탕으로 MSAP(modified semi-additive process)을 진행할 수 있게 된다.The present invention has a technical feature in that it covers the base copper foil of the CCL core with nickel plating to prevent the base copper foil from being etched in the subsequent copper plating etching step. In this way, MSAP (modified semi-additive process) can be performed based on the base copper foil remaining on the outer layer surface.
본 발명은 CCL(Copper Cladded Laminate; 동박적층판) 코어(core)의 베이스 동박(base copper) 위에 니켈 도금을 피복해서 후속 동도금 식각 단계에서 베이스 동박이 식각되지 아니하도록 하는 데 기술적 특징이 있다. 이와 같이 외층 표면에 남아 있는 베이스 동박을 바탕으로 MSAP(modified semi-additive process)을 진행함으로써, 기존의 텐팅 공법에 비해 미세 패턴을 제작할 수 있게 된다. 본 발명은 고밀도화되어가고 있는 FCBGA 기판의 미세화를 가능하게 한다.The technical feature of the present invention is to cover the base copper of the CCL (Copper Cladded Laminate) core with nickel plating to prevent the base copper foil from being etched in the subsequent copper plating etching step. In this way, by performing MSAP (modified semi-additive process) based on the base copper foil remaining on the outer layer surface, it is possible to produce fine patterns compared to the existing tenting method. The present invention enables miniaturization of FCBGA substrates, which are becoming more dense.
도1은 종래기술에 따른 텐팅공법을 나타낸 도면.
도2는 종래기술에 따른 수정부가(MSAP)공법을 나타낸 도면.
도3a 내지 도3l은 본 발명에 따른 회로기판 제조방법을 순차적으로 설명한 도면.Figure 1 is a diagram showing a tenting method according to the prior art.
Figure 2 is a diagram showing the modified addition (MSAP) method according to the prior art.
3A to 3L are diagrams sequentially explaining the circuit board manufacturing method according to the present invention.
본 발명은 CCL(Copper Cladded Laminate; 동박적층판) 코어(core)의 베이스 동박(base copper) 위에 니켈 도금을 피복해서 후속 동도금 식각 단계에서 베이스 동박이 식각되지 아니하도록 하는 데 기술적 특징이 있다. 이와 같이 외층 표면에 남아 있는 베이스 동박을 바탕으로 MSAP(modified semi-additive process)을 진행함으로써, 기존의 텐팅 공법에 비해 미세 패턴을 제작할 수 있게 된다.The technical feature of the present invention is to cover the base copper of the CCL (Copper Cladded Laminate) core with nickel plating to prevent the base copper foil from being etched in the subsequent copper plating etching step. In this way, by performing MSAP (modified semi-additive process) based on the base copper foil remaining on the outer layer surface, it is possible to produce fine patterns compared to the existing tenting method.
이하에서는 첨부 도면 도3a 내지 도3l을 참조해서 본 발명에 따른 미세 패턴의 회로기판을 제조하는 공법을 소개한다.Hereinafter, a method for manufacturing a fine patterned circuit board according to the present invention will be introduced with reference to the accompanying drawings, FIGS. 3A to 3L.
도3a 내지 도3l은 본 발명에 따른 회로기판 제조공법을 나타낸 도면이다. 도3a를 참조하면, 흔히 사용하는 동박적층판(CCL; 10)을 시작 재료로 사용할 수 있다. CCL(10)은 에폭시 수지 절연층(10b) 양측에 동박(10b, 10c)이 피복된 구조로서, 구리 포일(Copper foil)을 제거하고 남아 있는 동박(10b, 10b)을 이하에서 '베이스 동박'이라 칭한다. 통상적으로 베이스 동박은 수 마이크로미터 정도의 두께이다. 보다 바람직하게는 1 ~ 2 ㎛ 두께이다. Figures 3A to 3L are diagrams showing a circuit board manufacturing method according to the present invention. Referring to Figure 3a, a commonly used copper clad laminate (CCL; 10) can be used as a starting material. The CCL (10) is a structure in which copper foil (10b, 10c) is coated on both sides of the epoxy resin insulating layer (10b). The copper foil (Copper foil) is removed and the remaining copper foil (10b, 10b) is hereinafter referred to as 'base copper foil'. It is called. Typically, the base copper foil has a thickness of several micrometers. More preferably, it is 1 to 2 ㎛ thick.
도3b를 참조하면, 베이스 동박(10b, 10c) 위에 니켈 도금층(20)을 형성한다. 니켈 도금층(20)은 무전해 도금 방식으로 형성할 수 있으며, 니켈 도금층(20)은 배리어(barrier) 역할을 한다. Referring to Figure 3b, a nickel plating layer 20 is formed on the base copper foils 10b and 10c. The nickel plating layer 20 can be formed using an electroless plating method, and the nickel plating layer 20 serves as a barrier.
도3c를 참조하면, 상층과 하층의 회로를 서로 연결하기 위한 PTH(punch through hole; 관통홀; 30)을 형성한다. PTH는 CNC 드릴을 이용해서 형성할 수 있다. Referring to Figure 3c, a PTH (punch through hole) 30 is formed to connect the upper and lower layer circuits to each other. PTH can be formed using a CNC drill.
도3d를 참조하면, 동도금을 실시한다. 이때에 형성되는 동도금층(40)은 니켈 도금층(20) 위와 PTH(30)의 홀 내벽면 위에 형성된다. 도3e를 참조하면, 동도금으로 피복된 PTH(30) 홀 속을 절연잉크 등 충진재(50)를 사용해서 홀 플러깅(Hole Plugging)을 하여 충진한다.Referring to Figure 3d, copper plating is performed. At this time, the copper plating layer 40 is formed on the nickel plating layer 20 and on the inner wall of the hole of the PTH 30. Referring to Figure 3e, the hole of the PTH (30) covered with copper plating is filled by hole plugging using a filler (50) such as insulating ink.
도3f를 참조하면, 코어 기판의 외층 표면에 두껍게 피복된 동도금층(40)을 식각 제거함으로써, 홀 내벽에만 동도금을 남기고 회로를 형성할 부위 위에서는 MSAP 공정이 적용 가능하도록 준비한다. 이때에 본 발명에 따른 베이스 동박(10b, 10c)은 니켈층(20)이 식각액으로부터 보호하고 있는 특징이 있다.Referring to Figure 3f, the thick copper plating layer 40 on the outer surface of the core substrate is removed by etching, leaving copper plating only on the inner wall of the hole and preparing for the MSAP process to be applied on the area where the circuit is to be formed. At this time, the base copper foil (10b, 10c) according to the present invention has the characteristic of being protected from the etchant by the nickel layer (20).
도3g를 참조하면, 표면 연마 및 플라즈마 식각 공정을 진행해서, 돌출되어 있던 홀 충진재(50)를 평탄화한다. 도3h를 참조하면, 배리어로 사용하였던 니켈 도금층(20)을 제거한다. 그 결과, PTH 내벽 동도금과 접속된 베이스 동박(10b, 10c)가 노출되고 MSAP 공정이 개시된다. Referring to Figure 3g, surface polishing and plasma etching processes are performed to flatten the protruding hole filler 50. Referring to Figure 3h, the nickel plating layer 20 used as a barrier is removed. As a result, the base copper foils 10b and 10c connected to the PTH inner wall copper plating are exposed and the MSAP process is initiated.
도3i를 참조하면, 화학동을 실시해서 코어 기판 표면에 전해동도금을 위한 씨드(seed; 60)를 형성한다. 이제, 설계된 미세 회로 패턴을 기판에 전사(transfer)하기 위하여 드라이필름(Dry film; D/F; 70)을 피복하고, 통상적인 사진, 현상, 식각 등 일련의 이미지 프로세스를 진행해서 회로패턴을 D/F(70)에 전사한다. Referring to Figure 3i, chemical copper is performed to form a seed 60 for electrolytic copper plating on the surface of the core substrate. Now, in order to transfer the designed fine circuit pattern to the substrate, a dry film (D/F; 70) is covered, and a series of image processes such as conventional photography, development, and etching are performed to produce the circuit pattern in D. Transcribed to /F(70).
도3j는 미세 회로 패턴이 D/F(70)에 전사된 모습을 나타낸 도면이다. 도3k를 참조하면, 70)을 도금 마스크로 이용해서, 즉 D/F(70)이 덮이지 않은 화학동(60) 위에만 전기도금이 진행되어 동도금층(80)이 형성된다. 이렇게 함으로써 MSAP 방식으로 미세 회로패턴이 형성되는 것이다. Figure 3j is a diagram showing a microcircuit pattern transferred to the D/F (70). Referring to Figure 3k, using 70 as a plating mask, that is, electroplating is performed only on the chemical copper 60 that is not covered with the D/F 70, thereby forming the copper plating layer 80. In this way, a fine circuit pattern is formed using the MSAP method.
도3l을 참조하면, 최종적으로 D/F(70) 마스크를 스트립 오프하고 소프트 에칭을 진행함으로써 베이스 동박(10b, 10c)를 벗겨내면 MSAP 공정으로 형성된 미세 패턴의 동박회로를 얻게 된다. 여시서 소프트에칭이란 식각용액에 짧은 시간 노출시켜 식각하는 것을 의미한다. Referring to Figure 3l, when the D/F (70) mask is finally stripped off and soft etching is performed to peel off the base copper foil (10b, 10c), a fine patterned copper foil circuit formed by the MSAP process is obtained. Here, soft etching means etching by exposing the material to an etching solution for a short period of time.
전술한 내용은 후술할 발명의 특허 청구 범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술 될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다. The foregoing has somewhat broadly refined the features and technical advantages of the present invention to enable a better understanding of the scope of the patent claims of the invention described below. Additional features and advantages constituting the scope of the patent claims of the present invention will be described in detail below. It should be recognized by those skilled in the art that the disclosed concepts and specific embodiments of the present invention can be readily used as a basis for the design or modification of other structures for carrying out purposes similar to the present invention.
또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다. Additionally, the inventive concept and embodiments disclosed in the present invention may be used by those skilled in the art as a basis for modifying or designing other structures to carry out the same purpose of the present invention. In addition, such modified or changed equivalent structures by a person skilled in the art may be subject to various evolutions, substitutions, and changes without departing from the spirit or scope of the invention described in the patent claims.
본 발명은 CCL(Copper Cladded Laminate; 동박적층판) 코어(core)의 베이스 동박(base copper) 위에 니켈 도금을 피복해서 후속 동도금 식각 단계에서 베이스 동박이 식각되지 아니하도록 하는 데 기술적 특징이 있다. 이와 같이 외층 표면에 남아 있는 베이스 동박을 바탕으로 MSAP(modified semi-additive process)을 진행함으로써, 기존의 텐팅 공법에 비해 미세 패턴을 제작할 수 있게 된다. 본 발명은 고밀도화 되어가고 있는 FCBGA 기판의 미세화를 가능하게 한다. The technical feature of the present invention is to cover the base copper of the CCL (Copper Cladded Laminate) core with nickel plating to prevent the base copper foil from being etched in the subsequent copper plating etching step. In this way, by performing MSAP (modified semi-additive process) based on the base copper foil remaining on the outer layer surface, it is possible to produce fine patterns compared to the existing tenting method. The present invention enables miniaturization of FCBGA substrates, which are becoming more dense.
10 : CCL
20 : 니켈 도금층
30 : PTH
40 : 동도금층
50 : 홀 플러깅 충진재
60 : 화학동
70 : 드라이필름10:CCL
20: Nickel plating layer
30:PTH
40: Copper plating layer
50: Hole plugging filler
60: Chemical building
70: dry film
Claims (3)
(a) 상기 베이스 동박 위에 니켈 도금층을 형성하는 단계;
(b) 드릴 공정을 진행해서 관통홀을 형성하는 단계;
(c) 관통홀의 내벽과 상기 니켈 도금층 위에 동도금층을 형성하는 단계;
(d) 상기 관통홀에 충진재로 홀 플러깅을 하는 단계; 및
(e) 표면이 노출된 동을 식각함으로써 양면의 베이스 동박은 홀 내벽 동도금층에 의해 접속되고, 니켈 도금층 위의 동도금층은 제거하는 단계;
를 포함함으로써, 상기 니켈 도금층 하부의 베이스 동박을 단계(e)의 식각 단계 과정 중에 보호하는 것을 특징으로 하는 회로기판 제조방법.Regarding the core board covered with base copper foil on both sides of the insulating layer
(a) forming a nickel plating layer on the base copper foil;
(b) performing a drilling process to form a through hole;
(c) forming a copper plating layer on the inner wall of the through hole and the nickel plating layer;
(d) plugging the through hole with a filler; and
(e) etching the exposed copper to connect the base copper foil on both sides by a copper plating layer on the inner wall of the hole and removing the copper plating layer on the nickel plating layer;
A circuit board manufacturing method comprising protecting the base copper foil under the nickel plating layer during the etching step of step (e).
(a) 표면 연마하여 기판 표면을 평탄화하는 단계;
(b) 니켈 도금층을 식각 제거하여 베이스 동박을 노출하는 단계;
(c) 화학동을 실시하는 단계;
(d) 드라이필름을 피복하고 회로패턴을 전사하는 단계;
(e) 회로패턴이 전사된 드라이플름을 도금 마스크로 해서 동도금을 실시하는 단계; 및
(f) 드라이필름을 박리하고 소프트에칭을 실시해서 베이스 동박을 식각하는 단계
를 포함하는 회로기판 제조방법.For circuit boards manufactured according to paragraph 1,
(a) flattening the substrate surface by surface polishing;
(b) exposing the base copper foil by etching away the nickel plating layer;
(c) carrying out chemical engineering;
(d) covering the dry film and transferring the circuit pattern;
(e) performing copper plating using the dry flame onto which the circuit pattern is transferred as a plating mask; and
(f) Peeling off the dry film and performing soft etching to etch the base copper foil.
A circuit board manufacturing method comprising:
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| KR1020220052191A KR20230152433A (en) | 2022-04-27 | 2022-04-27 | Method of manufacturing printed circuit board with fine pitch |
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| KR1020220052191A KR20230152433A (en) | 2022-04-27 | 2022-04-27 | Method of manufacturing printed circuit board with fine pitch |
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|---|---|
| KR20230152433A true KR20230152433A (en) | 2023-11-03 |
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ID=88745570
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090087154A (en) | 2008-02-12 | 2009-08-17 | 대덕전자 주식회사 | Full-additive process for a fine-pitch printed circuit board |
| KR20110023925A (en) | 2009-09-01 | 2011-03-09 | 대덕전자 주식회사 | Semi-additive process with improved contact strength of electroplating copper layer for printed circuit board |
| KR20110031675A (en) | 2009-09-21 | 2011-03-29 | 주식회사 심텍 | Pcb having embedded chip and manufacturing method for the same |
| KR20180129002A (en) | 2017-05-24 | 2018-12-05 | 대덕전자 주식회사 | Method of manufacturing the circuit board |
-
2022
- 2022-04-27 KR KR1020220052191A patent/KR20230152433A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090087154A (en) | 2008-02-12 | 2009-08-17 | 대덕전자 주식회사 | Full-additive process for a fine-pitch printed circuit board |
| KR20110023925A (en) | 2009-09-01 | 2011-03-09 | 대덕전자 주식회사 | Semi-additive process with improved contact strength of electroplating copper layer for printed circuit board |
| KR20110031675A (en) | 2009-09-21 | 2011-03-29 | 주식회사 심텍 | Pcb having embedded chip and manufacturing method for the same |
| KR20180129002A (en) | 2017-05-24 | 2018-12-05 | 대덕전자 주식회사 | Method of manufacturing the circuit board |
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