KR100327705B1 - Method of producing a multi-layer printed-circuit board - Google Patents
Method of producing a multi-layer printed-circuit board Download PDFInfo
- Publication number
- KR100327705B1 KR100327705B1 KR1019990028624A KR19990028624A KR100327705B1 KR 100327705 B1 KR100327705 B1 KR 100327705B1 KR 1019990028624 A KR1019990028624 A KR 1019990028624A KR 19990028624 A KR19990028624 A KR 19990028624A KR 100327705 B1 KR100327705 B1 KR 100327705B1
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- South Korea
- Prior art keywords
- substrate
- circuit board
- printed circuit
- multilayer printed
- via hole
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 27
- 229920005989 resin Polymers 0.000 claims abstract description 34
- 239000011347 resin Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000010949 copper Substances 0.000 claims abstract description 28
- 229910052802 copper Inorganic materials 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000000126 substance Substances 0.000 claims abstract description 15
- 238000009713 electroplating Methods 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims description 16
- 229920001187 thermosetting polymer Polymers 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000000839 emulsion Substances 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 230000032683 aging Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000002344 surface layer Substances 0.000 abstract description 3
- 238000013007 heat curing Methods 0.000 abstract description 2
- 238000001962 electrophoresis Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 38
- 239000004593 Epoxy Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1208—Pretreatment of the circuit board, e.g. modifying wetting properties; Patterning by using affinity patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
Abstract
노트북 PC, HDD 등의 정보기기 또는 휴대전화 등의 소형 통신기기, 디지털 비디오 카메라 등에 사용될 수 있는 빌드업 다층 인쇄회로기판의 제조방법이 개시된다. 본 발명에 따르면, 회로가 형성된 절연기판의 전면에 화학동 또는 도전성 물질을 부착시키고 그위에 감광성 수지를 도포하고 도통홀부만 전기동도금을 하여 도통 수직회로를 형성하며, 절연수지로 양면에 인쇄 또는 도포처리후 완전 자외선 조사 또는 열경화 처리후 샌딩 연마처리로 도통회로의 랜드를 형성 노출시켜 그위에 조도형성과 화학동 및 전기동을 전착 도금한다. 따라서, 도통홀에 대한 신뢰성이 향상되고, 기존 도통홀부의 면적을 활용할 수 있어서 고밀도화 및 소형화가 가능하다. 또한, 다층 인쇄회로기판의 전체 제조공정이 단축되고, 표층 회로상의 블라인드 비어홀부 위에 부품을 실장할 수 있어서 부품의 실장밀도가 증가한다.Disclosed is a method of manufacturing a build-up multilayer printed circuit board that can be used in an information device such as a notebook PC, an HDD, or a small communication device such as a mobile phone, a digital video camera, or the like. According to the present invention, a chemical copper or conductive material is attached to the entire surface of the insulating substrate on which the circuit is formed, and a photosensitive resin is applied thereon, and only the conductive hole is electroplated to form a conductive vertical circuit, and printed or coated on both sides with insulating resin. After treatment, complete ultraviolet irradiation or heat curing treatment is followed by sanding polishing to form and expose lands of the conductive circuits, followed by electroplating of roughness forming, chemical copper, and electrophoresis. Therefore, the reliability of the through-holes is improved, and the area of the existing through-holes can be utilized, so that the density and size can be reduced. In addition, the entire manufacturing process of the multilayer printed circuit board is shortened, and the component can be mounted on the blind via hole portion on the surface layer circuit, thereby increasing the mounting density of the component.
Description
본 발명은 다층 인쇄회로기판의 제조에 관한 것으로, 더욱 상세하게는 기존 비어홀(via hole)의 면적을 활용함으로써 소형화가 가능하여 고밀도회로에 적용될 수 있고 비어홀에 대한 신뢰성이 향상된 빌드업 다층 인쇄회로기판의 제조방법에 관한 것이다.The present invention relates to the manufacture of a multilayer printed circuit board, and more particularly, it is possible to miniaturize by utilizing the area of an existing via hole, which can be applied to a high density circuit, and a build-up multilayer printed circuit board having improved reliability for the via hole. It relates to a manufacturing method of.
일반적으로, 인쇄회로기판은 각종 열경화성 합성수지로 이루어진 보드의 일면 또는 양면에 동선으로 배선한후 보드 상에 IC 또는 전자부품들을 배치 고정하고 이들간의 전기적 배선을 구현하여 절연체로 코팅한 것이다.In general, a printed circuit board is wired to one side or both sides of a board made of various thermosetting synthetic resins, and then the ICs or electronic components are disposed and fixed on the boards, and electrical wiring therebetween is coated with an insulator.
전자부품의 발달로 회로도체를 중첩하여 만드는 다층 인쇄회로기판이 개발된이래, 최근에는 다층 인쇄회로기판의 고밀도화에 관한 연구가 활발하게 진행되고 있으며, 그중에서도 빌드업(build-up) 다층 인쇄회로기판이 개발되어 널리 사용되고 있다.Since the development of electronic components, multilayer printed circuit boards made of overlapping circuit conductors have been developed, and recently, researches on the high density of multilayer printed circuit boards have been actively conducted, and among them, build-up multilayer printed circuit boards have been actively studied. Has been developed and widely used.
종래기술에 따른 빌드업 다층 인쇄회로기판의 제조방법은 절연층인 에폭시 글래스(epoxy glass)나 프리프레그(prepreg) 대신에 감광성 절연수지를 사용하여 절연층과 회로도체를 순차적으로 적층해서 다층회로를 형성하는 방법이다. 빌드업에 의한 다층 인쇄회로기판은 층간회로를 연결하는 비어홀 형성과 극소경(極小經)의 비어홀 형성이 가능할 뿐만아니라 회로두께가 얇아서 미세회로 형성이 용이하여 고밀도 회로를 구성할 수 있다. 또한, 종래의 절연층인 에폭시 글래스의 경우는 최소 0.1mm를 사용하였으나, 빌드업 다층 인쇄회로기판에서는 0.05mm 두께의 절연층을 형성할 수 있어서 경박화가 가능하다.In the method of manufacturing a build-up multilayer printed circuit board according to the prior art, a multilayer circuit is formed by sequentially stacking an insulating layer and a circuit conductor by using photosensitive insulating resin instead of epoxy glass or prepreg. How to form. The multi-layer printed circuit board by the build-up can not only form via holes connecting the interlayer circuits and via holes of very small diameters, but also have a thin circuit thickness, so that fine circuits can be easily formed to form high-density circuits. In the case of epoxy glass, which is a conventional insulating layer, a minimum thickness of 0.1 mm is used. However, in the build-up multilayer printed circuit board, a thickness of 0.05 mm may be formed, thereby making it thin.
도 2는 종래 기술에 따른 빌드업 다층 인쇄회로기판의 제조 공정을 도식적으로 나타낸 도면이다.2 is a diagram schematically illustrating a manufacturing process of a build-up multilayer printed circuit board according to the prior art.
도 2를 참조하면, 먼저 감광성 절연수지 또는 에폭시 열경화성 수지를 일정크기로 재단한후, 양면상에 감광성 필름을 부착시킨 상태로 식각처리를 하여 내층 회로를 형성시킨다(단계 SS1).Referring to FIG. 2, first, the photosensitive insulating resin or the epoxy thermosetting resin is cut to a certain size, and then the inner layer circuit is formed by performing an etching process with the photosensitive film attached on both surfaces thereof (step SS1).
다음에는, 내층 회로가 형성된 기판을 전처리 또는 표면연마과정을 수행한후, 기판의 양면상에 회로부의 배선패턴이 인쇄된 절연수지층을 1차 및 2차에 걸쳐서 도포한다(단계 SS2). 이때, 기판의 일면에 먼저 절연수지층을 도포하고 다음에 기판의 타면에 절연수지층을 도포한다.Next, after the substrate on which the inner layer circuit is formed is subjected to a pretreatment or surface polishing process, the insulating resin layer on which the wiring pattern of the circuit part is printed is applied on both sides of the substrate over the first and second stages (step SS2). At this time, the insulating resin layer is first applied to one surface of the substrate, and then the insulating resin layer is applied to the other surface of the substrate.
그런후에는, 절연수지층이 도포된 절연판을 예비 건조시킨후 감광성 필름을 부착하여 자외선 노광 및 현상과정을 거쳐서 회로가 접속될 도체라인과 도통 비어홀을 형성시킨다(단계 SS3). 이와는 달리, 에폭시 열경화성 수지를 이용할 경우에는 예비건조, 노광 및 현상공정을 생략하고 컴퓨터 수치제어(Computer Numeric Control; CNC) 방식으로 레이저를 이용하여 도체라인과 도통 비어홀을 형성할 수도 있다. 도통 비어홀이 형성된 절연판은 추후의 공정을 위해서 완전건조시킨후 표면 연마처리를 수행한다.Thereafter, the insulating plate on which the insulating resin layer is applied is preliminarily dried, and then the photosensitive film is attached to form a conductive line and a conductive via hole to which the circuit is connected through ultraviolet exposure and development (step SS3). On the other hand, when the epoxy thermosetting resin is used, the preliminary drying, the exposure and the development process may be omitted, and the conductor line and the conductive via hole may be formed by using a laser using a computer numerical control (CNC) method. The insulating plate on which the conductive via hole is formed is completely dried for later processing and then subjected to surface polishing.
그런데, 도통 비어홀 형성후 완전건조와 표면 연마처리를 거친 절연판에서 도통 비어홀 내에는 스컴(scum)이 잔류하여 비어홀에 대한 신뢰성이 저하될 수 있다. 따라서, 소프트 식각액을 이용하여 도통 비어홀 내에 남아있는 스미어(smear)를 제거시킨다. 그런후에는, 무전해 화학동을 전면에 석출시켜서 기판에 도전성을 부여한다(SS4).However, scum may remain in the conductive via hole in the insulating plate after the conductive via hole is completely dried and subjected to surface polishing, thereby reducing the reliability of the via hole. Therefore, the soft etchant is used to remove smear remaining in the through via hole. Thereafter, electroless chemical copper is deposited on the entire surface to impart conductivity to the substrate (SS4).
화학동 도금이 완료된 후에는, 도금 처리된 비어홀을 보강하고 회로패턴을 보강하기 위해서, 절연체의 표면에 도금처리되어 있는 동의 표면에 일정두께로 전기동 도금을 실시한다(SS5).After the completion of the chemical copper plating, in order to reinforce the plated via hole and to reinforce the circuit pattern, electrolytic plating is performed on the surface of the copper plated on the surface of the insulator at a predetermined thickness (SS5).
전기도금을 완료한 후에는, 동배선의 산화 및 동배선의 쇼트현상을 방지하기 위하여 필요한 부분, 즉 부품이 실장되는 부분의 도금층 이외에 절연 코팅막을 형성시키고, 에칭을 실시하여 절연 코팅막 외부로 동 도금을 박리 제거시켜서 회로를 형성한다(SS6).After the electroplating is completed, an insulating coating film is formed in addition to the plating layer necessary for preventing oxidation of the copper wiring and short circuit of the copper wiring, that is, the part on which the component is mounted, and etching is performed to copper plating the outside of the insulating coating film. Is removed to form a circuit (SS6).
다음에는, 상기 단계(SS2)에서와 마찬가지로, 회로가 형성된 기판을 전처리또는 표면연마과정을 수행한후, 절연수지층을 도포하여 비어홀을 막는다(SS7). 그런후에는, 상기 단계(SS3)에서 설명한 것과 동일한 방법으로 회로가 접속될 도체라인과 도통 비어홀을 형성시킨다(단계 SS8).Next, as in the step (SS2), after performing the pre-treatment or surface polishing process of the substrate on which the circuit is formed, the insulating resin layer is applied to prevent the via hole (SS7). Thereafter, a conductive via hole and a conductor line to which a circuit is connected are formed in the same manner as described in the step SS3 (step SS8).
다시 그위에 상기 단계(SS4) 내지 단계(SS8)과 동일한 과정을 거쳐서 각각의 배선패턴이 형성된 인쇄회로기판을 상호 적층하고, 적층된 다층 인쇄회로기판의 비어홀 내벽간에 도금하는 도금단계를 거쳐 다층 인쇄회로기판을 제조하고 있다(단계 SS9). 이때, 최외층에서는 부품이 실장되는 블라인드(Blind) 도통 비어홀부에 별도의 수지를 이용하여 플러깅(Plugging)처리를 한다.Then, through the same process as in steps SS4 to SS8, the printed circuit boards on which the respective wiring patterns are formed are laminated to each other, and the multi-layer printing is performed through the plating step of plating the inner walls of the via holes of the stacked multilayer printed circuit boards. A circuit board is manufactured (step SS9). At this time, in the outermost layer, a plugging process is performed using a separate resin in a blind conductive via hole in which the component is mounted.
그런데, 전술한 바와 같은 종래의 빌드업 다층 인쇄회로기판 제조과정에서는, 절연층 재료상의 감광성 수지계 사용으로 열경화성 수지에 비하여 전기적 특성 및 물성이 저하하고, 에폭시 열경화성 수지를 사용할 때에는 막대한 시설투자와 2회의 레이저를 이용한 홀가공 작업이 필요하며, 가공부위의 수지 스컴(scum)에 의한 도체간의 도통상의 신뢰문제가 야기된다. 또한, 전기 동도금시 마이크로 비어홀에 의한 전류밀도 분포의 불균일로 인하여 스로잉 파워(throwing power)가 낮아 신뢰성이 저하되고, 회로의 집적화에 있어서의 홀속 막음작업 및 레벨링 작업이 필요한 문제점이 있었다.본 명세서에서 사용되는 용어는 다음과 같은 의미로 사용된다.샌딩(Sanding) 연마처리 : Sandpaper를 이용하여 표면을 원하는 두께로 균일하게 깎아내는 것, 조도형성은 표면에 요철을 화학적 또는 기계적으로 가공하여 표면적을 증가시켜 접착력을 향상시키는 것을 나타내고, 블라인드 비어홀(Blind Via-hole)은 기판을 관통시키지 않고 일부 도체층까지만 가공하는 구멍을 의미하며, 비어홀은 전기적인 도통구멍을 나타낸다. 또한 프리프레그(Prepreg)는 유리, 섬유에 열경화성 수지를 도포하여 반경화시킨 것을 의미하고, 전처리는 기판에 절연수지를 도포하기전에 기판에 형성된 도체회로(내층회로) 표면에 0.5 ~ 1.5㎛가량의 요철을 가공하고 기타 이물질을 세척하여 절연수지와의 접착력을 강화시켜주는 공정을 의미한다. 또한 플러깅(Plugging)은 가공된 구멍을 절연수지, 도전성 페이스트, 도전체 등으로 메꾸어 주는 공정을 나타내고, 스로잉 파워(Through Power)는 구멍이 가공된 기판에 동도금을 입힐경우 기판표면과 기판에 가공된 구멍벽면과의 도금두께를 비율로 나타낸 것을 의미한다. 또한 디스미어(Desmear)는 절연수지 표면을 약 1㎛ 가량 깎아내고(KMnO4를 이용) 찌꺼기들을 제거하여 화학동도금시 절연수지와의 접착력을 향상시켜주는 공정을 의미하며, 에이징(Aging)처리는 기판이 가공되면서 생기는 수분과 휘발성분등을 제거하고 기판에 가해진 스트레스를 없애주므로써 이후 공정에서 생기는 응력의 영향을 최소화 하기위해 기판을 일정한 온도에서 일정시간 보관하는 것을 나타낸다.However, in the conventional build-up multilayer printed circuit board manufacturing process as described above, the use of the photosensitive resin based on the insulating layer material, the electrical properties and physical properties are lower than that of the thermosetting resin, and when using the epoxy thermosetting resin, enormous facility investment and two times Hole processing using a laser is required, and there is a problem of reliability of conduction between conductors due to resin scum at the processing site. In addition, due to the nonuniformity of the current density distribution due to the micro via hole during electroplating, the throwing power is low and the reliability is lowered, and there is a problem that the hole blocking operation and the leveling operation are required in the integration of the circuit. The term used is used in the following meanings: Sanding Polishing: The use of sandpaper to cut the surface evenly to the desired thickness. Roughness formation increases the surface area by chemically or mechanically processing irregularities on the surface. To improve adhesion, and blind via-holes refer to holes that do not penetrate the substrate but only a portion of the conductor layer, and via holes represent electrical through holes. In addition, prepreg means that the glass and the fiber are coated with a thermosetting resin and semi-cured. The pretreatment is about 0.5 to 1.5 μm on the surface of the conductor circuit (inner layer circuit) formed on the substrate before the insulating resin is applied to the substrate. It means the process of strengthening the adhesive strength with insulating resin by processing irregularities and cleaning other foreign substances. In addition, plugging refers to a process of filling a processed hole with an insulating resin, a conductive paste, and a conductor, and a throwing power is applied to the substrate surface and the substrate when copper plating is applied to the processed substrate. It means that the plating thickness with the hole wall surface is expressed as a ratio. Desmear refers to a process of cutting the surface of the insulating resin by about 1 μm (using KMnO 4 ) and removing debris to improve adhesion to the insulating resin during chemical copper plating. By removing the moisture and volatile components generated during processing and eliminating the stress applied to the substrate, it indicates that the substrate is stored at a constant temperature for a certain time in order to minimize the influence of the stress generated in the subsequent process.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 고밀도화 및 소형화가 가능하고 회로에 대한 신뢰성이 향상되며 부품의 실장밀도가 증가하는 빌드업 다층 인쇄회로기판의 제조방법을 제공하는데 있다.The present invention has been made to solve the conventional problems as described above, the object of the present invention is to manufacture a build-up multi-layer printed circuit board capable of increasing the density and miniaturization, improve the reliability of the circuit and increase the mounting density of the components To provide a method.
도 1은 본 발명에 따른 빌드업(build-up) 다층 인쇄회로기판의 제조 공정을 도식적으로 나타낸 도면이고,1 is a diagram schematically illustrating a manufacturing process of a build-up multilayer printed circuit board according to the present invention;
도 2는 종래 기술에 따른 빌드업 다층 인쇄회로기판의 제조 공정을 도식적으로 나타낸 도면이다.2 is a diagram schematically illustrating a manufacturing process of a build-up multilayer printed circuit board according to the prior art.
상기와 같은 목적을 달성하기 위해서, 본 발명은,In order to achieve the above object, the present invention,
구리피복 라미네이트를 일정크기로 재단한후, 감광성 유제를 도포하고 식각처리를 수행하여 내층 회로를 형성시키는 단계(S1);After cutting the copper clad laminate to a certain size, by applying a photosensitive emulsion and performing an etching process to form an inner layer circuit (S1);
상기 내층 회로가 형성된 기판의 양면상에 도전성 물질을 적층시키는 단계(S2);Stacking a conductive material on both surfaces of the substrate on which the inner layer circuit is formed (S2);
상기 도전성 물질이 적층된 기판 상에 감광성 수지를 부착하여 비어홀 패드부와 더미패턴을 형성한 후, 노출된 비어홀 패드부와 더미패턴부에 전기동 도금을 실시하는 단계(S3);Attaching a photosensitive resin on the substrate on which the conductive material is laminated to form a via hole pad part and a dummy pattern, and then performing electroplating on the exposed via hole pad part and the dummy pattern part (S3);
상기 감광성 수지를 박리하여 상기 도전성 물질을 제거한후, 상기 절연수지에 대한 밀착력을 향상시키기 위해서 전처리 또는 조도처리를 수행하는 단계(S4);Peeling the photosensitive resin to remove the conductive material, and then performing pretreatment or roughness treatment to improve adhesion to the insulating resin (S4);
전처리 또는 조도처리된 기판상에 절연층을 형성하는 단계(S5);Forming an insulating layer on the pretreated or roughened substrate (S5);
상기 절연층을 연마시키는 단계(S6);Polishing the insulating layer (S6);
연마된 기판상에서 상기 비어홀에 대한 도통 랜드(land)를 형성시키는 단계(S7); 그리고Forming a conductive land for the via hole on the polished substrate (S7); And
상기 단계(S1) 내지 상기 단계(S7)을 반복적으로 수행하여 빌드업 다층 인쇄회로기판을 형성하는 단계(S8)를 포함하는 것을 특징으로 하는 다층 인쇄회로기판의 제조방법을 제공한다.It provides a method of manufacturing a multilayer printed circuit board comprising the step (S8) to form a build-up multilayer printed circuit board by repeatedly performing the step (S1) to the step (S7).
이상에서 설명한 바와같이, 본 발명에 따른 빌드업 다층 인쇄회로기판의 제조방법에서는, 회로가 형성된 절연기판의 전면에 화학동 또는 도전성 물질을 부착시키고 그위에 감광성 수지를 도포하고 도통홀 및 더미패턴만 전기동도금을 하여 도통 수직회로를 형성하며, 절연수지로 양면에 인쇄 또는 도포처리후 완전 자외선 조사 또는 열경화 처리후 샌딩 연마처리로 도통회로의 랜드를 형성 노출시켜 그위에 조도형성과 화학동 및 전기동을 전착 도금한다.As described above, in the method for manufacturing a build-up multilayer printed circuit board according to the present invention, a chemical copper or conductive material is attached to the entire surface of an insulating substrate on which a circuit is formed, and a photosensitive resin is applied thereon, and only a conductive hole and a dummy pattern are provided. Electroplating is used to form a vertical conducting circuit. After printing or coating on both sides with insulating resin, the surface of the conducting circuit is exposed by sanding and polishing after complete UV irradiation or heat curing. Electrode plated.
이하, 첨부된 도면들을 참조하여 본 발명에 따른 빌드업 다층 인쇄회로기판의 제조방법을 보다 상세하게 설명하면 다음과 같다.Hereinafter, a method of manufacturing a build-up multilayer printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 빌드업(build-up) 다층 인쇄회로기판의 제조 공정을 도식적으로 나타낸 도면이다.1 is a diagram illustrating a manufacturing process of a build-up multilayer printed circuit board according to the present invention.
도 1을 참조하면, 먼저 특수하게 제작된 재단기를 사용하여 구리피복 라미네이트를 일정크기로 재단한후, 얇은 코어(thin core) 상에 감광성 유제를 약 5∼10μm의 두께로 도포하고 식각처리를 수행하여 내층 회로를 형성시킨다(단계 S1).Referring to FIG. 1, first, a copper coating laminate is cut to a predetermined size using a specially manufactured cutting machine, and then a photosensitive emulsion is applied on a thin core to a thickness of about 5 to 10 μm and then etched. To form an inner layer circuit (step S1).
다음에는, 내층 회로가 형성된 기판의 양면상에 도전성 물질을 적층시킨다. 즉, 무전해 화학동을 약 0.5∼3μm의 두께로 석출시킨다. 그런후에는, 감광성 필름을 약 40μm 두께로 부착하고 도통 비어홀부 및 더미패턴만 자외선이 차단되게한 상태로 약 0.75∼1.2%의 Na2CO3용액을 이용하여 미노광부만 용해 현상함으로써, 약 50∼150μm 직경의 비어홀이 형성되고 내층의 회로동층을 노출시켜 패턴이 노출된 기판의 전면에는 도전성이 부여된다(단계 S2).Next, a conductive material is laminated on both surfaces of the substrate on which the inner layer circuit is formed. In other words, electroless chemical copper is deposited to a thickness of about 0.5 to 3 탆. Thereafter, by attaching the photosensitive film to a thickness of about 40 μm and dissolving and developing only the unexposed portion by using a solution of Na 2 CO 3 of about 0.75 to 1.2% in a state in which only the conductive via hole portion and the dummy pattern were blocked with ultraviolet rays. A via hole having a diameter of ˜150 μm is formed, and the inner copper circuit layer is exposed, so that conductivity is imparted to the entire surface of the substrate on which the pattern is exposed (step S2).
다음에는, 노출된 비어홀과 패드부에 약 30∼120μm의 두께로 전기동 도금을 실시한다(단계 S3).Next, electrolytic plating is applied to the exposed via hole and the pad portion at a thickness of about 30 to 120 탆 (step S3).
그런후에는, 약 3∼5%의 NaOH 또는 KOH를 사용하여 감광성 수지를 제거하고 소프트(soft) 부식액을 사용하여 화학동층을 제거함과 동시에, 절연층과의 밀착력을 증진시키기 위해서 동회로층에 전처리 또는 조도처리를 수행한다. 그 결과, 동회로층은 약 0.5∼1.5μm의 거칠기를 갖게된다(단계 S4).Thereafter, about 3 to 5% of NaOH or KOH is used to remove the photosensitive resin, and a soft corrosion solution is used to remove the chemical copper layer, while pretreating the copper circuit layer to enhance adhesion with the insulating layer. Or roughness processing. As a result, the copper circuit layer has a roughness of about 0.5 to 1.5 mu m (step S4).
다음에는, 비어홀 도금층을 보호하기 위하여 1∼3차에 걸쳐서 도포기와 인쇄기를 사용하여 열경화성 에폭시 수지를 절연기판의 일면 또는 양면에 약 30∼110μm 두께로 적층하여 절연층을 형성한다(단계 S5).Next, in order to protect the via-hole plating layer, a thermosetting epoxy resin is laminated on one or both sides of the insulating substrate with a thickness of about 30 to 110 μm using an applicator and a printing machine over the first to third steps to form an insulating layer (step S5).
절연층이 적층된 절연기판을 열풍 건조기에서 완전건조시킨후, 절연에 필요한 두께를 확보하고 절연층 두께에 대한 평탄도를 유지시킴과 동시에 도통부위의 회로를 노출시키기 위해서 절연층의 샌딩(sanding) 연마공정을 수행한다(단계 S6).After drying the insulating substrate on which the insulating layer is laminated in a hot air dryer, sanding of the insulating layer is performed in order to secure the thickness necessary for insulation, maintain the flatness against the thickness of the insulating layer, and to expose the circuit of the conductive portion. The polishing process is performed (step S6).
연마된 절연수지의 표면을 디스미어(Desmear) 처리해서 표면에 조도(粗度)를 주어 화학동의 결합력을 향상시킨후, 전면에 약 2∼3μm 또는 약 0.3∼0.5μm의 두께로 화학동도금 처리를 수행한 다음, 약 80∼110℃에서 30∼50분동안 에이징처리를 수행함으로써 절연수지층과 화학동층간의 응력을 해소하여 신뢰성을 높인다. 여기에 약 15μm의 두께로 패턴 또는 패널 전기동도금을 수행하여 비어홀에 대한 도통 회로를 형성한다.(단계 S7).The surface of the polished insulating resin is desmeared to give roughness on the surface to improve the bonding strength of the chemical copper, and then the chemical copper plating is performed on the entire surface at a thickness of about 2 to 3 μm or about 0.3 to 0.5 μm. After the aging treatment is performed at about 80 to 110 ° C. for 30 to 50 minutes, the stress between the insulating resin layer and the chemical copper layer is solved, thereby improving reliability. Pattern or panel electrocopper plating is performed here to form a conductive circuit for the via hole (step S7).
다시 그위에 상기 단계(S1)에서처럼 감광성 유제를 도포하고 식각처리를 수행하여 회로를 형성시키고, 그 이후의 단계들을 반복적으로 수행하여 빌드업 다층 인쇄회로기판을 형성한다(단계 S8).Again, as in the step S1, a photosensitive emulsion is applied and an etching process is performed to form a circuit, and subsequent steps are repeatedly performed to form a buildup multilayer printed circuit board (step S8).
결과적으로, 도금에 의한 중간의 도통 회로형성과 동시에 홀에 대한플러깅(Plugging)처리를 통해서 레이저 홀가공기 및 플러지(Pluge)처리에 대한 신뢰성향상(평탄도 유지)과 자동적인 홀 플러깅 처리효과를 얻을 수 있다.As a result, the formation of an intermediate conduction circuit by plating, and the plugging process for the hole, improve the reliability (maintain flatness) and the automatic hole plugging effect for the laser hole processing machine and the plugging process. You can get it.
또한, 도전성 물질 및 도통 비어홀부의 도금 레지스트 공정이 필요하지만, 종래의 다층 인쇄회로기판 제조공정에 비해서 반복적인 레지스트 도포(4∼6회), 2회의 레이저 가공, 불안정한 디스미어처리, 홀 플러깅 처리, 샌드연마공정을 비교했을 때, 제조원가 측면에서 경쟁력을 얻을 수 있다.In addition, although the plating resist process of the conductive material and the conductive via hole part is required, the resist coating (4 to 6 times), two laser processing, unstable desmearing process, hole plugging process, and the like are repeated compared to the conventional multilayer printed circuit board manufacturing process. Comparing the sand polishing process, it can be competitive in terms of manufacturing cost.
이상에서 언급한 바와 같이, 본 발명에 따른 다층 인쇄회로기판의 제조방법에서는, 수지절연층과 회로도체층을 순차적으로 적층하는 빌드업 방식을 이용함으로써, 종래의 다층 인쇄회로기판을 형성할 때 층간 도통홀 형성을 위해서 에폭시 수지를 도포한후 레이저를 이용하는 도통홀 가공공정을 배제시켰다. 또한, 내층 및 표층에 대한 도통 비어홀 도금방식에 의한 동으로 플러깅처리함으로써, 회로의 구성밀도를 향상시킴과 동시에, 표층 회로상의 블라인드 비어홀부 위에 부품을 실장할 수 있어서 빌드업 다층기판부품의 경박 단소화 및 도통홀에 대한 신뢰성을 확보할 수 있다. 따라서, 다층 인쇄회로기판의 전제공정이 단축되고, 신뢰성이 향상되며, 소자본 참여가 가능하여 중소기업의 경쟁력을 확보할 수 있는 잇점이 얻어진다.As mentioned above, in the method of manufacturing a multilayer printed circuit board according to the present invention, by using a build-up method of sequentially stacking a resin insulating layer and a circuit conductor layer, interlayer conduction is performed when forming a conventional multilayer printed circuit board. After the epoxy resin was applied to form the hole, a through hole processing step using a laser was excluded. In addition, by plugging copper into copper via the conductive via hole plating method for the inner layer and the surface layer, the circuit density of the circuit can be improved, and the component can be mounted on the blind via hole portion on the surface layer circuit, thereby making the thin and thin end of the build-up multilayer substrate component. Reliability can be secured for fire extinguishing and through holes. Therefore, the preliminary process of the multilayer printed circuit board is shortened, reliability is improved, and small capital participation can be obtained, thereby securing the competitiveness of SMEs.
상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당기술분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.
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KR100389113B1 (en) * | 2001-06-21 | 2003-06-25 | 주식회사 태화인서트 | Device Adhering Method for FPCB |
KR100511085B1 (en) * | 2001-08-10 | 2005-08-30 | (주)알티즌하이텍 | Print template fabricating system and fabricating method thereof |
JP2003101204A (en) * | 2001-09-25 | 2003-04-04 | Nec Kansai Ltd | Wiring substrate, method of manufacturing the same, and electronic component |
KR20030071391A (en) * | 2002-02-28 | 2003-09-03 | 삼성전기주식회사 | Method for creating bump and making printed circuit board using the said bump |
KR20030095758A (en) * | 2002-06-14 | 2003-12-24 | 주식회사 심텍 | Forming method of via stud |
KR100981201B1 (en) * | 2003-05-15 | 2010-09-10 | 엘지이노텍 주식회사 | Making method of PCB for memory card |
KR100644094B1 (en) * | 2005-05-28 | 2006-11-10 | 대덕전자 주식회사 | Method of preparing a metal bump for building a package substrate on printed circuit board |
KR100709896B1 (en) * | 2006-02-28 | 2007-04-23 | 주식회사 두산 | Multilayer printed circuit board and method of manufacturing the same |
KR100843156B1 (en) | 2007-06-25 | 2008-07-02 | 대덕전자 주식회사 | Full-additive processing method for printed circuit board |
TWI519222B (en) | 2008-02-29 | 2016-01-21 | Lg伊諾特股份有限公司 | Printed circuit board and method of manufacturing the same |
KR101255892B1 (en) * | 2010-10-22 | 2013-04-17 | 삼성전기주식회사 | Printed circuit board And Method for fabricating the same |
KR101469614B1 (en) * | 2013-08-30 | 2014-12-05 | 한국생산기술연구원 | Method for forming metam patterns of double side flexible printedcircuit board |
CN114401592B (en) * | 2022-03-02 | 2024-03-29 | 立川(珠海)智能科技设备有限公司 | High-precision printing method for PCB solder mask |
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