KR100319819B1 - Method of producing a multi-layer printed-circuit board for a RF power amplifier - Google Patents

Abstract

In the process of forming a multilayer printed circuit board for RF power amplifiers, a number of unique gold plating methods were introduced instead of the existing dry thin film and solder plating resist, and the circuit thin film was formed again without peeling off the dry thin film. By successfully completing the gold plating of the site, a method of manufacturing a multilayer printed circuit board which effectively improves the poor adhesion of a dry thin film is disclosed. According to the present invention, after forming the inner layer circuit and the outer layer circuit, the primary soft gold plating is performed using a high concentration of gold plating bath, and the circuit is formed using a gold plating exclusive thin film, and the second soft gold plating is performed again and electroless Copper plating is performed. After the electroless plating is completed, the circuit is formed again using a gold plating exclusive thin film, followed by pulse plating using a pulse rectifier, followed by a third hard gold plating. After the 3rd hard gold plating is completed, a circuit is formed by using a gold plating exclusive thin film, and then the 4th soft gold plating is performed using a high concentration gold plating bath. Subsequently, the etching step and the plugging of the holes are performed, and the character printing process, the external machining process, and the electrical inspection process are sequentially performed. Finally, the substrate is cleaned by using plasma or isopropyl alcohol.

Description

Method of producing a multi-layer printed-circuit board for a RF power amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of multilayer printed circuit boards. More particularly, in the process of forming multilayer printed circuit boards for RF power amplifiers, several unique gold plating methods have been introduced instead of the existing dry thin film and solder plating resist. The present invention relates to a method for manufacturing a multilayer printed circuit board which effectively improves a poor adhesion phenomenon of a dry thin film by successfully completing a gold plating of a stepped portion by forming a circuit again thereon without peeling off the dry thin film.

In general, a printed circuit board (hereinafter, referred to as a PCB) is wired to one or both sides of a board made of various thermosetting synthetic resins in a copper line, and then the IC or electronic components are placed and fixed on the board, and electrical wiring between them is performed. It is implemented and coated with an insulator.

Since the development of electronic components, multi-layer PCBs made of overlapping circuit conductors have been developed, researches on the high density of multi-layer PCBs have been actively conducted in recent years. Multilayer PCB has required many characteristics of PCB itself due to the thinness, shortening and high integration of VLSI and electronic components. Most of these products have applied technology of fine wire (0.1mm or less) and micro diameter hole (0.3 ~ 0.05mm). It is required to mass-produce new, multi-layered and diversified technologies.

By the way, there are some problems that are not solved in the manufacturing method of the existing RF (RF) power amplifier PCB, which is shown as follows sequentially.

First, in the related art, when a hard gold plating is performed after hard gold plating, the dry thin film, which is a hard gold plating resist, is peeled off, which not only causes a cost increase but also a soft gold plating on the stepped portion. At the time of the stepped portion, the thin film does not adhere during the dry thin film lamination, so that the plating solution penetrates and causes a short.

In other words, in the conventional circuit forming method using a dry thin film (tenting method) or Sn or Sn-Pb alloy (pattern method), there was no suitable solution to increase the adhesion of the dry thin film resist of the stepped portion. Typically, the step portion that can be covered through the dry thin film is 4㎛, the step of the product currently being applied is 50 ~ 127㎛ as a dry thin film (40 ~ 50㎛) it is difficult to overcome this.

3 is a view showing a poor adhesion of a dry thin film during circuit formation in the manufacturing process of the multilayer printed circuit board for RF power amplifier according to the prior art.

Referring to Figure 3, in the manufacturing process of the multilayer printed circuit board for the RF power amplifier according to the prior art, when using the existing dry thin film resist 30, as well as excessive gold plating, the side portion 32 of the stepped portion Since the gold layer is not adhered to the portion to be plated properly 34, the plating layer penetrates into the lower portion of the dry thin film during the gold plating so that unwanted portions are left during circuit formation, and as a result, there is a problem of causing short defects.

On the other hand, in the past, when filling the hole with PSR ink itself when filling the hole, PSR ink was repeatedly applied several times to completely fill the hole. However, even after such a series of repetition process, a part of the hole is not completely filled, so that the epoxy liquid flows to the lower part when molding with epoxy after wire bonding.

In addition, conventionally, electroless plating is performed before gold plating, and then the plated soft gold plating layer is continuously exposed during copper plating, hard gold plating, and tertiary hard gold plating, so that the surface is oxidized and scratches are generated. There was a problem that a bad wire bonding occurs frequently.

In addition, when electroplating is performed with the existing DC rectifier, the plating takes a long time and the plating variation between the holes and the surface layer is severe when plating with a thickness of 50 μm or more in the hole and the surface layer. In other words, the conventional DC copper plating method has a thickness difference of about 60: 100 in the hole and the surface, and if the plating area is wide, it should be plated for a long time, which finally causes the thin film to be lifted due to the chemical limitation of the dry film.

The present invention has been made to solve the above conventional problems, the object of the present invention in the manufacturing process of the multilayer printed circuit board for RF power amplifier in place of the existing dry thin film and solder plating resist many times unique gold plating The present invention provides a method of manufacturing a multilayer printed circuit board which effectively improves the adhesion failure of a dry thin film by successfully completing the gold plating of the stepped portion by forming a circuit thereon again without peeling off the dry thin film.

Another object of the present invention is to introduce a plugging process during hole filling in the manufacturing process of a multilayer printed circuit board for RF power amplifier, and to perform the hole filling simply and completely, thereby shortening the manufacturing process and increasing work efficiency. The present invention provides a method for manufacturing a multilayer printed circuit board.

Another object of the present invention is to carry out electroless copper plating after the second gold plating in the manufacturing process of the multilayer printed circuit board for RF power amplifier, thereby protecting the flexible gold plated layer and preventing oxidation of the gold plated layer. It is to provide a method of manufacturing a substrate.

It is another object of the present invention to apply a plating method using a pulse rectifier before the third gold plating in the manufacturing process of a multilayer printed circuit board for RF power amplifier, thereby effectively eliminating the plating deviation, which has been a problem when electroplating using a conventional DC rectifier. The present invention provides a method of manufacturing a multilayer printed circuit board that is not limited by time even when the thin plated layer is removed.

1 is a diagram schematically illustrating a manufacturing process of a multilayer printed circuit board for RF power amplifier according to the present invention;

2 is a view showing the adhesion of the dry thin film when forming the circuit in the manufacturing process of the multilayer printed circuit board for RF power amplifier according to the present invention, and

3 is a view showing a poor adhesion of a dry thin film during circuit formation in the manufacturing process of the multilayer printed circuit board for RF power amplifier according to the prior art.

<Explanation of symbols for main parts of drawing>

20,22,30: dry thin film resist 24,34: gold plating site

32: side part

In order to achieve the above object, the present invention,

Cutting the inner core material to a predetermined size and then boring the via hole and performing copper plating to form an inner layer circuit (S1);

After surface-treating the inner layer core on which the inner layer circuit is formed, thermally compressing the bonding sheet on one or both surfaces of the inner layer core, and subsequently laminating a conductor layer on the exposed surface of the bonding sheet (S2);

A half etching step (S3) of etching only one surface of a solder surface of the stacked substrate while passing through the step (S2);

After the step S3, forming a hole in a predetermined position of an outer layer and then forming a primary circuit (S4);

Performing a primary soft gold plating with a thickness of 2 to 5 µm nickel and 0.2 µm or more gold using a high concentration gold plating bath after the formation of the primary circuit (S5);

Forming a secondary circuit using a gold plating exclusive thin film after performing the first soft gold plating (S6);

Performing secondary soft gold plating with a thickness of 2 to 5 μm of nickel and 1.06 μm or more of gold using a high concentration of gold plating bath after the formation of the secondary circuit (S7);

After the second soft gold plating, electroless copper plating is performed on the via hole wall surface and the board to form a copper film having a thickness of 2 to 3 μm (S8);

Forming a tertiary circuit by using a gold-plated thin film after the electroless copper plating is finished (S9);

Performing pulse plating using a pulse rectifier after the formation of the tertiary circuit (S10);

After the pulse plating is finished using a high gold plating bath of high concentration step of performing a third hard gold plating with a thickness of nickel 2 ~ 5㎛, gold 0.2㎛ or more (S11);

Forming a fourth circuit by using a gold plating exclusive thin film after the third hard gold plating is finished (S12);

After the formation of the fourth circuit, performing a fourth soft gold plating to a thickness of 0.5 to 1 µm of nickel and 1.06 µm of gold or more using a gold plating bath having a high concentration (S13);

Removing the remaining dry thin film resist in addition to the pad and the pattern gold plated layer on which the component is mounted after the 4th soft gold plating, and etching at a speed of 4 to 4.5 m / min (S14);

Performing a plugging process on the hole after etching (S15);

After the step (S15), step (S16) of sequentially performing the character printing process, the appearance processing process and the electrical inspection process; And

It provides a method of manufacturing a multilayer printed circuit board comprising the step (S17) of cleaning the substrate passed through the step (S16).

As described above, in the method of manufacturing a multilayer printed circuit board according to the present invention, by applying a plurality of gold plating methods, a resist is formed on the gold plated resist instead of peeling the existing resist, thereby forming a conventional dry thin film resist. Eliminate adhesion defects that occur at In addition, electroless copper plating is performed after the first and second gold plating to achieve conduction in the hole and effectively protect the gold plating layer for wire bonding.

Hereinafter, a method of manufacturing a multilayer printed circuit board for RF power amplifier according to the present invention will be described in detail with reference to the accompanying drawings.

The present invention is to provide a method for manufacturing a multilayer printed circuit board suitable for the manufacturing process of a high difficulty product which requires BVH processing technology, the plating thickness in the hole should be 50㎛ or more and gold wire bonding after surface treatment (soft gold plating).

To this end, the present invention fabricates a multilayer PCB for RF power amplifiers based on the manufacturing process shown schematically in FIG.

As shown in FIG. 1, inner layer preparation is performed as the first process for producing a multilayer PCB. That is, in the multilayer PCB design, the inner core of the layer structure determined in the multilayer configuration is cut to a certain size using a special cutting machine, and a via hole is installed at a predetermined position of the board using a computer numerical control method using a drill of 0.25Φ diameter. After the hole is formed, plating of the inner layer panel is performed to give conductivity to the punched via hole. That is, copper plating is performed on the via hole wall surface and the board to form a copper film having a thickness of 10 to 15 mu m.

After the copper plating is finished, an inner layer circuit is formed. That is, for interface with IC component mounting terminals for mounting ICs, passive component mounting terminals for mounting passive components of electronic components such as resistors, capacitors, diodes, and additionally equipped sockets. To form the connector terminals, a dry film, which is plotted according to the circuit design data, is coated on the copper plated board, followed by exposure and development of the dry film, followed by etching, peeling, cleaning, and drying. The inner layer circuit is formed through.

After the formation of the inner layer circuit, the inner core is subjected to the surface treatment, and then the bonding sheet is thermocompression-bonded to a thickness of 0.1 to 0.4 mm on one surface of the board.

After lamination, so-called half etching is performed to etch only one surface of the solder surface. That is, only the unexposed portion was dissolved by attaching a photosensitive film to a thickness of about 40㎛ using a Na ₂ CO ₃ solution of about 0.75~1.2% blind via hole part, only the via holes and the dummy pattern in a state where the ultraviolet rays to be blocked on the solder surface on one side It develops and exposes the circuit layer of an inner layer, and removes only one surface of the board | substrate which the pattern was exposed.

Next, a via hole is formed at a predetermined position of the outer layer by a computer numerical control method using a drill having a diameter of 0.3Φ, and then a primary circuit is formed in the same manner as the formation of the inner layer circuit as described above. At this time, the gold-plated thin film is coated on the board and subjected to the exposure and development processes, and to form a primary circuit through the drying process.

After the formation of the primary circuit, primary soft gold plating is performed with a thickness of 2 to 5 µm nickel and 0.2 µm or more gold using an acidic gold plating bath of high concentration. After the first soft gold plating is performed, a second circuit is formed again using a gold plating exclusive thin film.

After the formation of the secondary circuit, secondary soft gold plating is performed using a high concentration of acidic gold plating bath with a thickness of 2 to 5 μm of nickel and 1.06 μm of gold, and current flows from front to back or back to front in the multilayer PCB. Electroless copper plating is performed on the via hole wall surface and the board of the outer layer so as to form a copper film having a thickness of 2-3 m.

Thus, electroless copper plating can be performed after the second soft gold plating to effectively protect the soft gold plating layer and prevent oxidation of the gold plating layer. That is, in the PCB manufacturing process according to the prior art, the electroless copper plating was used only to conduct the hole in the electroplating, but in the present invention, the conduction of the hole is performed based on the conduction and protects the gold plating layer for wire bonding. .

After the electroless plating is completed, the third circuit is formed again using a gold-plated thin film, and then pulse plating is performed using a pulse rectifier. That is, pulse copper plating is performed on the via hole wall surface and the board of the outer layer to form a copper film having a thickness of 50 µm or more. At this time, the plating working conditions were forward current density of 3.0 ± 1.0A / dm ² , reverse current density of 10.0 ± 3.0A / dm ² , forward pulse application time of 5-20 seconds, reverse pulse application time of 0.5-2 Seconds, and the total plating time is 60 to 150 minutes.

By applying the plating method using a pulse rectifier in this way, it is possible to effectively eliminate the plating deviation which was a problem when electroplating in the conventional process using a DC rectifier. In addition, even when the thick plating layer is formed, copper plating can be performed without being restricted by time.

After the pulse plating is completed, the third hard gold plating is performed using a high concentration of gold plating bath with a thickness of 2 to 5 μm of nickel and 0.2 μm of gold.

2 is a view showing the adhesion of the dry thin film during the circuit formation in the manufacturing process of the multilayer printed circuit board for RF power amplifier according to the present invention.

Referring to FIG. 2, when the third plating is performed on the upper layer of 50 탆 without peeling off the dry thin film 20, which is an electroplating resist used during the 50 탆 pulse plating, using the portion to be gold-plated 24 as the lower etching resist. By using it as a lower layer of the dry thin film 22 which is a gold plating resist, process loss can be shortened and the adhesion defect which arises in stepped PCB manufacture can be eliminated.

On the other hand, after tertiary hard gold plating is completed, the secondary circuit is formed again using a gold plating exclusive thin film, and after forming the fourth circuit, the fourth soft gold plating is performed with a thickness of 1.0 μm or more by using an acid gold plating bath of high concentration. do. After the 4th soft gold plating, residual dry thin film resist is removed in addition to the pad and pattern gold plated layer on which the component is mounted and etched at a speed of 4 to 4.5 m / min.

Next, the hole plugging process is performed. That is, a conductor plug made of a conductive paste containing conductive powder is inserted into the hole and sintered to fill the hole primarily. Therefore, the PSR application can be done only once, and the ink can also be dried because it uses only a small amount of volatile ink in the hole before filling the PSR ink, exposes it, cures it, and then applies PSR again. It was possible to solve the problem of the ink shrinking during the opening in the hole.

After going through letter printing process, processing of external form and electric inspection process, the product is completed by cleaning process to remove contaminants or organic matters that may occur during PCB manufacturing process. At this time, in the cleaning process, by using plasma or isopropyl alcohol (IPA) treatment, the bonding force of the metal wire bonding can be improved.

As mentioned above, in the method of manufacturing a multilayer printed circuit board according to the present invention, plating of the stepped portions, which is not solved in the existing circuit formation, is achieved by using gold plating several times. That is, when gold plating is formed, the lower end etching resist is formed and the upper end is plated with a thickness of 50 μm or more, and when the gold plating resist is formed, the resist is formed again on top of the existing resist, i.e., gold plating. Penetration was eliminated.

In addition, electroless copper plating was carried out after the first and second gold plating to achieve conduction in the hole and effectively protect the gold plating layer for wire bonding.

In addition, since the plugging process is introduced in the hole filling and the hole filling is primarily performed in the plugging, the PSR coating can be fully performed by one time. At this time, when filling the hole, before applying the PSR, the hole is filled with only a small amount of volatile ink and then exposed and cured. Then, the PSR is applied again. Since the ink also uses less volatile components, it is possible to prevent the phenomenon of shrinking the ink during opening and opening of the holes.

In addition, in case of electric copper plating using DC rectifier in the existing PCB manufacturing process, if the plating thickness is increased to 50㎛ or more to add heat dissipation function to the PCB itself due to the plating deviation of the hole and the surface, The surface is plated with a thickness of 70 ~ 80㎛ and when the commercially available dry thin film is used, it is overplated to cause short defects, or the surface of the plate becomes rough due to the increase of plating particles due to the control of plating time. Affect the surface. However, the PCB manufacturing process according to the present invention can solve this problem because copper plating is performed using a pulse rectifier.

Finally, in the conventional PCB manufacturing process, the cleaning is finished by the final pre-BBT cleaning, resulting in a decrease in bonding strength during wire bonding, but in the present invention, contaminants or organic substances that may occur during PCB manufacturing after BBT are plasma or isopropyl alcohol. By rinsing using, the bonding force of the gold plated wire can be increased.

While the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (4)

Cutting the inner core material to a predetermined size and then boring the via hole and performing copper plating to form an inner layer circuit (S1); After surface-treating the inner layer core on which the inner layer circuit is formed, thermally compressing the bonding sheet on one or both surfaces of the inner layer core, and subsequently laminating a conductor layer on the exposed surface of the bonding sheet (S2); A half etching step (S3) of etching only one surface of a solder surface of the stacked substrate while passing through the step (S2); After the step S3, forming a hole in a predetermined position of an outer layer and then forming a primary circuit (S4); Performing a primary soft gold plating with a thickness of 2 to 5 µm nickel and 0.2 µm or more gold using a high concentration gold plating bath after the formation of the primary circuit (S5); Forming a secondary circuit using a gold plating exclusive thin film after performing the first soft gold plating (S6); Performing secondary soft gold plating with a thickness of 2 to 5 μm of nickel and 1.06 μm or more of gold using a high concentration of gold plating bath after the formation of the secondary circuit (S7); After the second soft gold plating, electroless copper plating is performed on the via hole wall surface and the board to form a copper film having a thickness of 2 to 3 μm (S8); Forming a tertiary circuit by using a gold-plated thin film after the electroless copper plating (S9); Performing pulse plating using a pulse rectifier after the formation of the tertiary circuit (S10); After the pulse plating is finished using a high gold plating bath of high concentration step of performing a third hard gold plating with a thickness of nickel 2 ~ 5㎛, gold 0.2㎛ or more (S11); Forming a fourth circuit by using a gold plating exclusive thin film after the third hard gold plating is finished (S12); After the formation of the fourth circuit, performing a fourth soft gold plating to a thickness of 1.0 μm or more using a gold plating bath of high concentration (S13); Removing the insulating coating film in addition to the plating layer of the part in which the component is mounted after the fourth soft gold plating, and etching at a speed of 4 to 4.5 m / min (S14); Performing a plugging process on the hole after etching (S15); After the step (S15), step (S16) of sequentially performing the character printing process, the appearance processing process and the electrical inspection process; And Method of manufacturing a multilayer printed circuit board comprising the step (S17) of cleaning the substrate passed through the step (S16). The method of claim 1, wherein in the step S10, the forward current density is 3.0 ± 1.0 A / dm ² , the reverse current density is 10.0 ± 3.0 A / dm ² , the forward pulse application time is 5 to 20 seconds, the reverse pulse application Under the operating conditions of 0.5 to 2.0 seconds and total plating time of 60 to 150 minutes, pulse copper plating is performed on the via hole wall surface and the board of the outer layer to form a copper film having a thickness of 50 μm or more. Method of manufacturing a printed circuit board. The method of claim 1, wherein in step (S15), after inserting a conductive plug made of a conductive paste containing a conductive powder into the hole and sintering to fill the hole first, the volatile component only in the hole before PSR ink is applied. A method of manufacturing a multilayer printed circuit board, which comprises using a small amount of ink to fill, expose and cure, and then apply PSR thereon. The method of claim 1, wherein in step S17, plasma or cleaning is performed using isopropyl alcohol (IPA).