JPH036880A - Printed wiring board and manufacture thereof - Google Patents
Printed wiring board and manufacture thereofInfo
- Publication number
- JPH036880A JPH036880A JP14101389A JP14101389A JPH036880A JP H036880 A JPH036880 A JP H036880A JP 14101389 A JP14101389 A JP 14101389A JP 14101389 A JP14101389 A JP 14101389A JP H036880 A JPH036880 A JP H036880A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- resist
- wiring board
- printed wiring
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910000679 solder Inorganic materials 0.000 claims abstract description 49
- 238000007747 plating Methods 0.000 claims abstract description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052802 copper Inorganic materials 0.000 claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 16
- 238000004070 electrodeposition Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 25
- 238000005476 soldering Methods 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 13
- 230000000873 masking effect Effects 0.000 claims description 5
- 238000005553 drilling Methods 0.000 claims 1
- 239000011889 copper foil Substances 0.000 abstract description 9
- 238000003780 insertion Methods 0.000 abstract description 2
- 230000037431 insertion Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 13
- 239000010410 layer Substances 0.000 description 12
- 229910000831 Steel Inorganic materials 0.000 description 7
- 239000010959 steel Substances 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 235000011121 sodium hydroxide Nutrition 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100482057 Abies grandis ag10 gene Proteins 0.000 description 1
- -1 Boron fluoride Tin fluoride Boron fluoride Lead Chemical compound 0.000 description 1
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 1
- 229910000976 Electrical steel Inorganic materials 0.000 description 1
- 241000750004 Nestor meridionalis Species 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- JZCCFEFSEZPSOG-UHFFFAOYSA-L copper(II) sulfate pentahydrate Chemical compound O.O.O.O.O.[Cu+2].[O-]S([O-])(=O)=O JZCCFEFSEZPSOG-UHFFFAOYSA-L 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント配線板に関するものであり、特に面付
部品及び挿入部品が混在したプリント配−板及びその製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printed wiring board, and more particularly to a printed wiring board in which surface-mounted parts and inserted parts are mixed, and a method for manufacturing the same.
(従来技術1)
従来、面付部品と挿入部品とが混在するプリント配線板
は、藁4図に示す様にスルーホール部3と面付ランド部
17とが備えられている。ここで。(Prior Art 1) Conventionally, a printed wiring board in which surface-mounted components and inserted components coexist is provided with through-hole portions 3 and surface-mounted land portions 17, as shown in FIG. here.
面付部品(18)と挿入部品(19) (第8図I参照
)とは四時にはんだ付けできないため、側5図A〜Cに
示す工程で行なわれる。纂5図Aは纂4図の正面図であ
り、まず易5図Bの工程では、面付ランドs17におい
てはんだペースト20により面付部品18のはんだ付を
行なう。しかし、この纂5図Bの工程における過熱によ
り、スルーホールN5の銅箔表面が酸化するため、論5
図CK示す工程の押入部品19のはんだ付けにおいて、
はんだ5のフローアップ不足21やグミ−ホール22等
のはんだ付不良が発生しやすかりた。Since the surface-mounted part (18) and the inserted part (19) (see FIG. 8I) cannot be soldered together at the same time, the steps shown in FIGS. 5A to 5C are performed. Figure 5A is a front view of Figure 4. First, in the process shown in Figure 5B, the surface-mounted component 18 is soldered on the surface-mounted land s17 with the solder paste 20. However, due to overheating in the process shown in Figure 5B, the surface of the copper foil in through hole N5 is oxidized.
In soldering the push-in part 19 in the process shown in Figure CK,
Soldering defects such as insufficient flow-up 21 of solder 5 and gummy holes 22 were likely to occur.
また第6図及びあ7図Aに示す様に、予めパターン全体
にはんだめっぎあるいははんだコーティング5を行ない
、スルーホール部5のむかえはんだとなる構造もある。Furthermore, as shown in FIGS. 6 and 7A, there is also a structure in which the entire pattern is plated with solder or coated with solder 5 in advance, and the through-hole portions 5 are coated with solder.
しかし、面付ランド部17にはんだ5が予め付いている
状態では、纂7図Bに示す様に、はんだがはじかれて接
続不良となる現象(ウィッキング25)が発生しやすく
なる。However, in a state where the solder 5 is preliminarily attached to the surface land portion 17, a phenomenon (wicking 25) in which the solder is repelled and a connection failure occurs is likely to occur, as shown in FIG. 7B.
基板表面の銅箔パターンの上に設けられた半田めりき層
の一部を除去した構造が特開昭61−123196
号公報に記載されているが、前記問題を解決するもので
ない。A structure in which a part of the solder plated layer provided on the copper foil pattern on the surface of the board is removed is disclosed in JP-A-61-123196.
Although it is described in the above publication, it does not solve the above problem.
(従来技術2)
小径スルーホール(φ0.5myt以下〕を有する篇密
度基板の回路形成法には、スルーホールの信頼性を保つ
ため、篤8図に示す様なはんだめりぎ法が一般的に用い
られている。以下にその工程を示す。(Prior art 2) In order to maintain the reliability of the through-holes, the soldering method shown in Figure 8 is commonly used to form circuits on high-density boards with small-diameter through-holes (φ0.5 myt or less). The process is shown below.
以下のアルファベットANIは、第8図の図番A−IK
対応するものである。The alphabet ANI below is the figure number A-IK in Figure 8.
It corresponds to this.
A 銅張り積層板1の穴あけ、銅めりぎを行ない。A: Drill holes in the copper-clad laminate 1 and perform copper inserts.
スルーホール3を形成する。A through hole 3 is formed.
B フィルム溢感光性レジスト11を基板全面にラミネ
ートし、ポジマスク10を用いて露光する。B: Laminate a film-filled photosensitive resist 11 over the entire surface of the substrate, and expose using a positive mask 10.
C現像により、めりきレジスト4を形成する。A plated resist 4 is formed by C development.
D はんだめっきを行なう。D Perform solder plating.
E めりきレジスト4を剥離する。(はんだめりき5に
よるエツチングレジストの形成)F エツチングを行な
う。E Peel off the plated resist 4. (Formation of etching resist using solder plate 5) F Etching is performed.
G エツチングレジスト5を剥離してパターン13を形
成する。G. The etching resist 5 is peeled off to form a pattern 13.
I ンルダーレジスト26を印刷する。I Print the ruler resist 26.
1 部品18 、19を実装しはんだ付けを行なう。1. Mount and solder parts 18 and 19.
しかしパターンの極am化(解像良50−μ扉以下)に
伴ない、従来のフィルム型の感光性レジスト11では、
第9図Aに示す様にレジスト解像不良23、レジストv
!jyII不良24が発生するため、回路形成が困難で
あった。However, as patterns become more AM-oriented (resolution of 50-μ or less), the conventional film-type photosensitive resist 11
As shown in FIG. 9A, resist resolution failure 23, resist v
! Since the jyII defect 24 occurred, it was difficult to form a circuit.
一方高所像度#1線パターンを形成するために1電層型
感光レジストを用いる工法がある。On the other hand, there is a method that uses a single-layer photosensitive resist to form a high-image resolution #1 line pattern.
電sm感元性レジストを用いると、@9図BK示す様に
フィルム型に比べ膜厚が薄く、銅箔表面2との缶溜性が
艮いため、高解像[細線パターンの形成が可能である。When using an electro-SM sensitive resist, as shown in Figure 9 BK, the film thickness is thinner than that of a film type resist, and its retention with the copper foil surface 2 is excellent, making it possible to form high-resolution [fine line patterns]. be.
しかし、電;)l型の場合、スルーホール内も露光しな
くてはならないため、/h径ススルーホールおいては、
jtLlolV、44C示す様に光9か照射されに(
<、部分的に露光されない懸念がある。よって現像、エ
ツチング後は、第10凶Bに示す様にスルーホール欠陥
16が発生するため一スルーホールの信頼性が低下する
。However, in the case of the electron ;) l type, the inside of the through hole must also be exposed, so for /h diameter through holes,
jtLlolV, as shown in 44C, light 9 is irradiated (
<, there is a concern that some parts may not be exposed. Therefore, after development and etching, through-hole defects 16 occur as shown in the tenth defect B, and the reliability of one through-hole decreases.
スルーホールの信頼性を償うことなく高所[L#巌パタ
ーンを形成する方法として、特開昭6l−24709o
号公@に記載された発明があるが、を層レジストは
、めっきレジストとし℃用いられており、はんだめっき
がエツチングレジストとなるため、エツチング精度は、
従来のはんだめっき法と同等と考えられる。As a method for forming an L# rock pattern in high places without sacrificing the reliability of through holes, Japanese Patent Application Laid-open No. 6L-24709O
There is an invention described in the publication @, but the layer resist is used as a plating resist, and since the solder plating becomes the etching resist, the etching accuracy is
It is considered to be equivalent to the conventional solder plating method.
以上のように、従来技術1においては、面付央装の加熱
工程により′鋼表面が酸化し、次のはんだ付はフローア
ップ工程でスルーホールのはんだ付は性が劣化し、また
従来技術2においては、面付実装の際にはんだペースト
のはじきが発生し接続不良となる問題があった。As described above, in Prior Art 1, the heating process of the surface mounting center oxidizes the steel surface, and the soldering properties of through-holes deteriorate during the next soldering process during the flow-up process. In the above, there was a problem in which solder paste was repelled during surface mounting, resulting in poor connection.
本発明は、このような問題点を同時に解決するプリント
配嶽板及びその製造方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a printed mounting board and a method for manufacturing the same that solves these problems at the same time.
上Llll的は、スルーホールのみをはんだめりきでカ
バーした後、電層mUrレジストを用いて回路形成を行
なうことにより−S成される。In general, -S is formed by covering only the through holes with solder and then forming a circuit using a conductive layer mUr resist.
小径スルーホールは、はんだめりきによりエツチング時
の信頼性が保持され、表面回路は、電漕溢UVレジスト
により、高解像I!L11all/IMパターンの形成
が可能となるため、小径スルーホールを有する高密度回
路基板の形成に有効である。The reliability of the small-diameter through-holes during etching is maintained by soldering, and the surface circuitry has high resolution I! Since it is possible to form an L11all/IM pattern, it is effective for forming a high-density circuit board having small-diameter through holes.
上記方法で形成されたプリント板の11I造は、スルー
ホール部のみにはんだが残るため、面付部品挿入部品の
はんだ付は時における、クィッキング。In the case of the 11I printed circuit board formed by the above method, solder remains only in the through-hole portions, so soldering of the surface-mounted parts insertion parts is sometimes quick.
7a−アップ不足等の問題が解決できる。7a- Problems such as insufficient uploading can be solved.
以下本発明の一実施例を第1図乃至第3図によりi!!
明する。纂1図は本発明によるプリント配線板の製造工
程の概略図であり、以下その内容を説明する。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. !
I will clarify. FIG. 1 is a schematic diagram of the manufacturing process of a printed wiring board according to the present invention, and the details thereof will be explained below.
以下のアルファベラ)A−Jは、謳1図の図番A−,=
1に対応するものである。The following Alphabella) A-J is the figure number A-,= of the song 1 diagram.
This corresponds to 1.
A 銅張り積層板1のPJ′r足位f[Kドリルを用い
スルーホールX通孔5をあける。その恢、通常用いられ
ているスルーホールめっきプロセス(例えばシブレイ社
pTHプaセス)によりスルーホール内面を含む全面に
厚さ10〜5Ωμmの銅めりぎを析出させる。この時析
出させる鋼めっぎとしては以下の成分から構成される厚
付は化学鋼めっきを用いることが、めっき厚バラツキ抑
制1品質安定化の面から有効である。A PJ'r foot position f of the copper-clad laminate 1 [K Drill through hole Thereafter, copper plating with a thickness of 10 to 5 Ωμm is deposited on the entire surface including the inner surface of the through hole by a commonly used through hole plating process (for example, Sibley's pTH process). As the steel plating to be deposited at this time, it is effective to use a thick chemical steel plating composed of the following components from the viewpoint of suppressing variation in plating thickness and stabilizing quality.
化学銅めっき液成分例 硫酸銅5水塩 10〜121/J 苛性ソーダ ホルマリン EDTA・2N。Example of chemical copper plating solution components Copper sulfate pentahydrate 10-121/J caustic soda formalin EDTA・2N.
添加剤
化学鋼めっき条件例
pH12〜12.5.液温7o±1℃
B 感光性フィルム例えば日立化成製7オテツク850
A F T−513を全面に貼シ付けた後、所定スル
ーホール用のランド部のみ銅が露出する様、帛2図に示
す様なポジマスク10にて膳光し、現像を行ない、はん
だめっき用レジスト4を形成する。この時用いるポジマ
スク1Ωのランド径14(纂り図#照)は、プリント板
仕上り状態でのランド径<US図15)K比べ0*05
〜0.1 mm小さく製作した物を用いることにより、
ランド部のマスクズレによる銅11kBを防ぐことがで
きる。Additive chemical steel plating condition example pH 12-12.5. Liquid temperature: 7o±1℃ B Photosensitive film, such as Hitachi Chemical's 7Otek 850
After pasting A F T-513 on the entire surface, it was exposed to light using a positive mask 10 as shown in Figure 2 so that the copper was exposed only in the land area for the predetermined through-hole, and then developed. A resist 4 is formed. The land diameter 14 of the positive mask 1Ω used at this time (as shown in the assembled diagram) is 0*05 compared to the land diameter in the finished state of the printed board <US diagram 15)K.
By using a product made smaller by ~0.1 mm,
It is possible to prevent copper 11kB due to mask displacement in the land portion.
c4出しているランド部12およびスルーホール5の内
部にはんだめりき5を以下の成分1条件で厚さ5μm以
上析出させる。c4 Solder plating 5 is deposited to a thickness of 5 μm or more inside the exposed land portions 12 and through holes 5 under the following component 1 conditions.
はんだめっぎ液成分例
10〜121iり
5〜4mj、/7
56〜46ji/1
適量
硼弗化錫
硼弗化鉛
硼弗化水素酸
添加剤
はんだめりぎ条件例
電fi密度 1〜! 、4/dm”液 温
20〜30℃D はんだめりき用レ
ジスト4を剥離除去する。Solder plating liquid component example 10-121i 5-4mj, /7 56-46ji/1 Appropriate amount Boron fluoride Tin fluoride Boron fluoride Lead borohydrofluoride Additive Solder plating condition example Electron fi density 1 ~! , 4/dm” liquid temperature
20 to 30° C. Peel and remove the solder plating resist 4.
前記7オテツク865 A F T−50の場合は5〜
5%苛性ソーダ液を50℃にし次ぎ付けることにより容
易に剥離除去できる。In the case of the above 7 otek 865 AFT-50, it is 5~
It can be easily peeled off and removed by subsequently applying a 5% caustic soda solution at 50°C.
E 露出している銅およびランド部、スルーホール部の
はんだめっきよK tfffi感光性レジスト〔以下@
@UVレジストとい5〕6を遺族する。E Solder plating on exposed copper, land areas, and through holes K tfffi photosensitive resist [hereinafter @
@UV Resist 5] 6 is survived.
電層UVレジスト6としてはシブレイ社展イーグル20
00 を用い1条件として液温20〜30℃電g’i
iは40〜60 mA/cLm2程度であり、また時間
は通電電流値が最小となる時までとした。この時の電y
jtUVレジストの膜厚はおおむね10〜20μ風であ
りた。Sibley Exhibition Eagle 20 is an electric layer UV resist 6.
00 and one condition is liquid temperature 20~30℃ electric g'i
i was about 40 to 60 mA/cLm2, and the time was set to the time when the current value reached the minimum. Electricity at this time
The film thickness of the jtUV resist was approximately 10 to 20 μm.
100〜2007/j
5Ω〜100y/J
200〜4001/j
適 重
F 所定回路を描いたネガマスクを位置合せし、密層さ
せた後、超高圧水銀灯を具備した蕗光愼を用い波長56
5nm程度の紫外光を200m//C−!照射し、表面
回路部分ランド1iit1.スルーホール部のt涜UV
レジスト6を光硬化させる。その後現像液としてシブレ
イ社製現像液な用い未光硬化部分な浴解除去する。この
電層UVレジスト6が1次工程エツチングのためのエツ
チングレジスト7となる。100~2007/j 5Ω~100y/J 200~4001/j Appropriate Weight F After aligning the negative masks depicting the predetermined circuit and layering them closely, we used a Fukōshin equipped with an ultra-high-pressure mercury lamp to produce a 56-wavelength mask.
Ultraviolet light of about 5 nm at 200 m//C-! irradiate the surface circuit portion land 1iit1. UV of through-hole part
The resist 6 is photocured. Thereafter, a developer manufactured by Sibley Co., Ltd. was used as a developer, and the uncured portion was removed by bath decomposition. This electric layer UV resist 6 becomes an etching resist 7 for the first step etching.
C塩化m2鉄、塩化纂2銅、アルカリエッチャント等に
より、エツチングレジスト7で僅れていない銅箔2の膳
出都を溶解除去する。The portion of the copper foil 2 that is not removed by the etching resist 7 is dissolved and removed using m2 iron chloride, copper chloride, an alkali etchant, or the like.
Hエツチングレジスト7を剥離することにより、スルー
ホール部3のみにはんだ5の付いたfi14紬パターン
13が形成される。剥離液としてはシブレイ社製剥離液
を用いる。By peeling off the H-etching resist 7, a fi14 pongee pattern 13 with solder 5 attached only to the through-hole portion 3 is formed. A stripping solution manufactured by Sibley is used as the stripping solution.
以上の様なプロセスにより帛1図Hの徊遺を有するプリ
ント配線板を得ることができる。Through the process described above, a printed wiring board having the variations shown in FIG. 1H can be obtained.
本構造は、スルーホール部5にはんだめつき5が設けら
れ、面付ランド部17は銅箔2が露出し℃いる。In this structure, a solder pad 5 is provided in the through-hole portion 5, and the copper foil 2 is exposed in the surface-mounted land portion 17.
この後の部品の実装工程としては、謳1図IK示すよう
に面付ランド部17及びスルーホール都5以外をソルダ
ーレジスト26で覆うように印刷し、しかる後、第1図
1に示すように1面付部品18を面付ランド部1711
Cはんだ付けし、また挿入部品19をスルーホール部3
に挿入した後はんだ付け”する。In the subsequent component mounting process, as shown in FIG. 1, parts other than the surface-mounted land 17 and the through-hole cap 5 are covered with solder resist 26, and then, as shown in FIG. The one-sided part 18 is attached to the one-sided land part 1711
C solder and also insert the insert part 19 into the through-hole part 3.
solder after inserting it into the
よって挿入部品1面付部品のはんだ付は時には、面付ラ
ンド[17には銅箔2がまた゛スルーホール部5にはは
んだめっき5が露出しているため、第5図C、第7図B
に示す様な)a−アップ不足21゜ウィッキング25が
発生しなくなり、部品との接続qi幀性が著しく向上で
きる。Therefore, when soldering a component with one side of the inserted part, sometimes the copper foil 2 is on the surface land [17] and the solder plating 5 is exposed on the through-hole part 5, so it is difficult to solder the parts with one side attached.
The lack of a-up 21° wicking 25 as shown in FIG.
なお、スルーホール内のはんだ形成については、次の方
法をとることもできる。即ち、銅張り、11鳩板あるい
はすでに内層回路を積層プレスされた多層板に穴あけし
た故、スルーホール内を含む全表面に化学鋼めっきのみ
でまたは化学銅めっき上へ電気鋼めっきを1P以上析出
させ、フィルム状感光性レジストでスルーホールをおお
う形状で′に元。Note that the following method can also be used to form solder inside the through hole. In other words, since holes are made in a copper-plated, 11-layer board or a multilayer board on which inner layer circuits have already been laminated and pressed, chemical steel plating alone is applied to the entire surface including the inside of the through-hole, or electrical steel plating is deposited on top of chemical copper plating for 1P or more. Then, cover the through hole with a film-like photosensitive resist.
現像−エッチング、剥離を行ない回路を形層した恢、ソ
ルダーレジストで必4!部をコーティングし、はんだ不
要部分をマスキングテープあるいは耐薬品性インクを印
刷した後、露出しているランド部。After developing, etching, and peeling the circuit to form a layer, the solder resist is a must! After coating the area and printing masking tape or chemical-resistant ink on areas that do not require soldering, the exposed land area.
スルーホール部に溶融はんだを0.1μm以上付層させ
、その後マスキングテープあるいは耐薬品性インクを除
去する。これによっても、表面回路は銅で、またランド
部、スルーホール部ははんだが被覆される。A layer of 0.1 μm or more of molten solder is applied to the through-hole portion, and then the masking tape or chemical-resistant ink is removed. In this case, the surface circuit is covered with copper, and the land portion and through-hole portion are covered with solder.
以上詳しく説明したように本発明によれば、従来技術に
おいて問題となっていたフローアップ不足(第5図C)
及びウィッキング(N7図B)が−挙に解消でき、面付
部品及び挿入部品を混載するプリント配線板において両
部品の接続信頼性を著しく向上せしめることができる。As explained in detail above, according to the present invention, the lack of flow-up (FIG. 5C), which was a problem in the prior art,
and wicking (Fig. N7B) can be eliminated at once, and the connection reliability between the two components can be significantly improved in a printed wiring board on which surface-mounted components and inserted components are mounted together.
また裏道プロセス中においては、第5図に示す様にスル
ーホール5をはんだめつき5で保護した状態で、エツチ
ングレジスト7による回路形成ができ4ため、スルーホ
ールの信頼性を損うことなく、高解像度+1[パターン
の形成が可能となる。In addition, during the back-path process, as shown in Figure 5, circuit formation can be performed using etching resist 7 while protecting through-hole 5 with solder 5, without impairing the reliability of the through-hole. , high resolution +1 [pattern formation becomes possible.
萬1図A〜Iは本発明のプリント配線板の一実施例の回
路形成工程図及び部品実装図である。
纂2図は基板とポジマスクの合わせ状態を示す外観図、
aKS図は電着によるエツチングレジスト形成後の状態
を示すプリント配線板の外観図である。
纂4図は従来の鋼箔露出プリント配線板の外観図、第5
図ANCは落4図のプリント配線板のはんだ付はプロセ
ス概略図を示し、第5図Aはプリント配線板の断面図、
纂5図Bは面付部品のはんだ付けを示す断面図、纂5図
Cは挿入部品のはんだ付けを示す断面図である。
篤6図は従来のはんだ付着プリント配線板の外観図%第
7図A、Bは第6図のプリント配線板のはんだ付はプロ
セス概略図を示し、第7図Aはプリント配線板の断面図
、第7図Bは面付部品のはんだ付けを示す断面図である
。
第8図は従来のプリント配線板の回路形成工程脂及び理
想的な部品笑#C図、第9図A、Bは谷々フィルム型#
11L層型感光性レジストによるノくターンの形成状態
を示す外貌図、ag10図A、Bは電層型レジストを用
いた場合の穴門島光を示す楓#@断面図で、纂10図A
は蕗光時j纂10図Bは現像。
エツチング住の状態を示すl#r面図である。
(符号の説明)
1・・・銅張り積層板 2・・・銅箔3・・・スル
ーホール
4・・・はんだめっき用レジスト
5・・・はんだめっき
6・・・電;lv型感光性レしスト
7・・・エツチングレジスト9・・・照射光10・・・
ポジマスク
11・・・フィルム型感光性レジスト
12・・・ランド部 16・・・鋼箔パターン
14・・・はんだめっぎランド径(ポジマスク径)15
・・・仕上りランド径 16・・・スルーホール欠陥
部17・・・面付ランドs18・・・面付部品19・・
・挿入部品 20・・・はんだペースト21・
−フローアップ不足 22・・・グミ−ホール2S・・
・レジスト解像不良 24・・・レジスト密層不良25
・・・クイツキング 26・・・ソルダーレジスト
菫
釦
易 1図B
誇W
易
図
巳
11 図Q
寛
図F
3
目
届
図H
図1
β
日J
(2)
カ
カ
52八
m−、−一ノ
2
に汁
岩
ら
図
z9品へ
z9弓B
図
わ
ん
トー
昂
B図E
カ
8 回F
凹A
鴬8図8
ζ−
図
ζ
8 図4
0HFigures A to I are circuit forming process diagrams and component mounting diagrams of an embodiment of the printed wiring board of the present invention. Figure 2 is an external view showing the alignment of the substrate and positive mask.
The aKS diagram is an external view of the printed wiring board showing the state after formation of etching resist by electrodeposition. Figure 4 is an external view of a conventional exposed steel foil printed wiring board;
Figure ANC shows a schematic diagram of the process for soldering a printed wiring board in Figure 4, and Figure 5A is a cross-sectional view of the printed wiring board.
Figure 5B is a sectional view showing soldering of surface-mounted parts, and Figure 5C is a sectional view showing soldering of inserted parts. Figure 6 is an external view of a conventional soldered printed wiring board; Figures 7A and B are schematic diagrams of the soldering process of the printed wiring board in Figure 6; Figure 7A is a cross-sectional view of the printed wiring board. , FIG. 7B is a sectional view showing soldering of surface-mounted parts. Figure 8 shows the conventional printed wiring board circuit forming process and ideal parts (Figure C), Figure 9 A and B show the valley film type
11A is an external view showing the state of formation of a nokturn by the L layer type photosensitive resist, ag10 Figures A and B are Kaede#@ cross-sectional views showing the Anamojima Hikari when using the electric layer type resist, and Figure 10A is
Figure 10 B is developed by Fukumitsu. It is a l#r side view showing the state of etching. (Explanation of symbols) 1...Copper-clad laminate 2...Copper foil 3...Through hole 4...Solder plating resist 5...Solder plating 6...Electric; LV type photosensitive resin Resist 7...Etching resist 9...Irradiation light 10...
Positive mask 11...Film type photosensitive resist 12...Land portion 16...Steel foil pattern 14...Solder plating land diameter (positive mask diameter) 15
...Finished land diameter 16...Through hole defective part 17...Surfaced land s18...Surfaced part 19...
・Insert parts 20...Solder paste 21・
-Insufficient flow up 22...Gummy hole 2S...
・Resist resolution failure 24...Resist dense layer failure 25
...Kuitsuking 26...Solder resist Sumitomo Ei 1 Diagram B Kozu Izumi 11 Diagram Q Hirozu F 3 Inventory diagram H Diagram 1 β Day J (2) Kaka 528m-, -ichino2 Nijiruiwa et al. z 9 items z 9 bow B zuwanto ko B fig. E ka 8 times F concave A 8 fig. 8 ζ- fig. ζ 8 fig. 4 0H
Claims (6)
線板において、スルーホール内面の銅がはんだにより被
覆されてなるスルーホール部と、一部がはんだ被覆され
ていない表面回路部とを備えてなるプリント配線板。1. A printed wiring board having a through hole and a surface circuit, the printed wiring board comprising a through hole portion in which copper on the inner surface of the through hole is covered with solder, and a surface circuit portion partially not covered with solder.
装用の面付ランドを含むことを特徴とする請求項1記載
のプリント配線板。2. 2. The printed wiring board according to claim 1, wherein the surface circuit portion not covered with solder includes a surface-mounted land for mounting surface-mounted components.
有するプリント配線板のスルーホール内にのみはんだめ
っきを行なった後、感光性レジストを全面に塗膜し、必
要回路の露光,現像,エッチング,剥離を行なうことに
より、スルーホールにはんだめっき層が表面回路に銅層
が形成されることを特徴とするプリント配線板の製造方
法。3. After solder plating is applied only to the through-holes with a copper plating layer and the through-holes of a printed wiring board with a surface copper layer, a photosensitive resist is applied to the entire surface, and the necessary circuits are exposed, developed, etched, and peeled off. A method for manufacturing a printed wiring board, characterized in that a solder plating layer is formed in the through holes and a copper layer is formed in the surface circuit by performing the above steps.
を特徴とする請求項5記載のプリント配線板の製造方法
。4. 6. The method for manufacturing a printed wiring board according to claim 5, wherein the photosensitive resist is an electrodeposition type UV resist.
とを特徴とする請求項3記載のプリント配線板の製造方
法。5. 4. The method of manufacturing a printed wiring board according to claim 3, wherein the photosensitive resist is a film resist.
スされた多層板に穴あけした後、スルーホール内を含む
全表面に化学銅めっきのみでまたは化学銅めっき上へ電
気銅めっきを1μm以上析出させ、フイルム状感光性レ
ジストでスルーホールをおおう形状で露光,現像,エッ
チング,剥離を行ない回路を形成した後、ソルダーレジ
ストで必要部をコーテイングし、はんだ不要部分をマス
キングテープあるいは耐薬品性インクを印刷した後、露
出しているランド部,スルーホール部に溶融はんだを0
.1μm以上付着させ、その後マスキングテープあるい
は耐薬品性インクを除去することにより、表面回路は銅
でランド部,スルーホール部ははんだが被覆されている
ことを特徴とするプリント配線板の製造方法。6. After drilling holes in a copper-clad laminate or a multilayer board that has already been laminated and pressed with inner layer circuits, chemical copper plating alone is applied to the entire surface including the inside of the through hole, or electrolytic copper plating is deposited to a thickness of 1 μm or more on top of the chemical copper plating, and a film-like film is formed. After forming a circuit by covering the through holes with photosensitive resist, exposing, developing, etching, and peeling, coat the necessary parts with solder resist, and print masking tape or chemical-resistant ink on the parts that do not require soldering. Apply no molten solder to the exposed lands and through holes.
.. A method for producing a printed wiring board, characterized in that the land portions of the surface circuitry and the through-hole portions are covered with solder by attaching the masking tape or chemical-resistant ink to a thickness of 1 μm or more, and then removing the masking tape or chemical-resistant ink.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1141013A JP2804084B2 (en) | 1989-06-05 | 1989-06-05 | Blind wiring board and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1141013A JP2804084B2 (en) | 1989-06-05 | 1989-06-05 | Blind wiring board and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH036880A true JPH036880A (en) | 1991-01-14 |
JP2804084B2 JP2804084B2 (en) | 1998-09-24 |
Family
ID=15282167
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1141013A Expired - Fee Related JP2804084B2 (en) | 1989-06-05 | 1989-06-05 | Blind wiring board and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2804084B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05198909A (en) * | 1992-01-23 | 1993-08-06 | Hitachi Ltd | High density printed board and manufacture thereof |
US5338171A (en) * | 1991-04-17 | 1994-08-16 | Kabushiki Kaisha Komatsu Seisakusho | Die-clamping apparatus with aligning device |
US5370518A (en) * | 1992-01-29 | 1994-12-06 | Kabushiki Kaisha Komatsu Seisakusho | Apparatus for injection and compression molding |
US6174562B1 (en) * | 1996-07-09 | 2001-01-16 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and device on printed boards |
CN102970833A (en) * | 2012-11-05 | 2013-03-13 | 杭州华三通信技术有限公司 | Processing method and insert hole structure of printed circuit board (PCB) insert hole |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102046006B1 (en) * | 2016-06-07 | 2019-11-18 | 주식회사 엘지화학 | High-current transfer methods utilizing the printed circuit board |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54120866A (en) * | 1978-03-10 | 1979-09-19 | Anritsu Electric Co Ltd | Method of producing through hole printed board |
-
1989
- 1989-06-05 JP JP1141013A patent/JP2804084B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54120866A (en) * | 1978-03-10 | 1979-09-19 | Anritsu Electric Co Ltd | Method of producing through hole printed board |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5338171A (en) * | 1991-04-17 | 1994-08-16 | Kabushiki Kaisha Komatsu Seisakusho | Die-clamping apparatus with aligning device |
JPH05198909A (en) * | 1992-01-23 | 1993-08-06 | Hitachi Ltd | High density printed board and manufacture thereof |
US5370518A (en) * | 1992-01-29 | 1994-12-06 | Kabushiki Kaisha Komatsu Seisakusho | Apparatus for injection and compression molding |
US6174562B1 (en) * | 1996-07-09 | 2001-01-16 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and device on printed boards |
CN102970833A (en) * | 2012-11-05 | 2013-03-13 | 杭州华三通信技术有限公司 | Processing method and insert hole structure of printed circuit board (PCB) insert hole |
Also Published As
Publication number | Publication date |
---|---|
JP2804084B2 (en) | 1998-09-24 |
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