JPH05243709A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH05243709A
JPH05243709A JP4428692A JP4428692A JPH05243709A JP H05243709 A JPH05243709 A JP H05243709A JP 4428692 A JP4428692 A JP 4428692A JP 4428692 A JP4428692 A JP 4428692A JP H05243709 A JPH05243709 A JP H05243709A
Authority
JP
Japan
Prior art keywords
resin layer
photosensitive resin
insulating substrate
layer
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4428692A
Other languages
Japanese (ja)
Other versions
JP2723744B2 (en
Inventor
Yoshiaki Horii
良晃 堀井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Toppan Circuit Solutions Toyama Inc
Original Assignee
NEC Toppan Circuit Solutions Toyama Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Toppan Circuit Solutions Toyama Inc filed Critical NEC Toppan Circuit Solutions Toyama Inc
Priority to JP4428692A priority Critical patent/JP2723744B2/en
Publication of JPH05243709A publication Critical patent/JPH05243709A/en
Application granted granted Critical
Publication of JP2723744B2 publication Critical patent/JP2723744B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To reduce breaking of discontinuity and defects by forming a conductive resin layer on a photosensitive resin film to prevent static electricity and hence deposition of foreign objects, in view of the fact that the photosensitive resin layer easily accumulates static electricity since it has no conductivity, and thus foreign objects deposit on portions of the photosensitive resin layer and these portions are not exposed to light at the time of exposure, which causes discontinuity of the wiring and defects. CONSTITUTION:A copper-clad insulating substrate 1 is coated with a positive photosensitive resin film 8 by electrodeposition, and then the insulating substrate 1 is coated with a conductive resin and dried, thereby obtaining a conductive resin layer 9.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は印刷配線板の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board.

【0002】[0002]

【従来の技術】一般に、スルーホール印刷配線板(以
下、T/H PWBと記す)の製造には、図7(a)〜
図8(b)に示すテンティング工法が多く用いられてお
り、この方法に依れば、図7(a)に示す如く、絶縁基
板1上に銅めっき層を含む導体層2とスルーホール(以
下、T/Hと記す)1aを形成した絶縁基板1上に図7
(b)に示す如く、感光性樹脂層3を貼付し、この上か
ら図7(c)に示す如く、マスクフィルム4を介して所
望の配線回路のパターンを紫外線で焼き付ける。
2. Description of the Related Art In general, manufacturing of a through-hole printed wiring board (hereinafter referred to as T / H PWB) is performed with reference to FIGS.
The tenting method shown in FIG. 8B is often used. According to this method, as shown in FIG. 7A, the conductor layer 2 including the copper plating layer and the through hole ( Hereinafter, referred to as T / H) 1a is formed on the insulating substrate 1 shown in FIG.
As shown in FIG. 7B, the photosensitive resin layer 3 is attached, and a desired wiring circuit pattern is printed with ultraviolet rays through the mask film 4 as shown in FIG. 7C.

【0003】次に、図7(d)に示す如く、現像液で未
露光部分の感光性樹脂層3を除去しエッチングレジスト
5a,5bを得る。更に、図8(a)に示す如く、露出
した導体層2をエッチング除去した後、最後に、図8
(b)に示す如く、エッチングレジスト5a,5bを剥
離除去してT/H PWBを得るものである。
Next, as shown in FIG. 7D, the photosensitive resin layer 3 in the unexposed portion is removed with a developing solution to obtain etching resists 5a and 5b. Further, as shown in FIG. 8A, after the exposed conductor layer 2 is removed by etching, finally, as shown in FIG.
As shown in (b), the etching resists 5a and 5b are peeled and removed to obtain T / H PWB.

【0004】又、図9(a)〜図10(c)に示す穴埋
め工法では、図9(a)に示す如く、絶縁基板1上に銅
めっき層を含む導体層2とT/H1aを形成した基板の
T/H内部に図9(b)に示す如く、穴埋めインク7を
充填,硬化させ、絶縁基板1表面に感光性樹脂層3を貼
付する。この上から図9(d)に示す如く、マスクフィ
ルム4を介して所望の配線パターンを紫外線で焼き付け
る。
Further, in the hole filling method shown in FIGS. 9A to 10C, the conductor layer 2 including the copper plating layer and the T / H 1a are formed on the insulating substrate 1 as shown in FIG. 9A. As shown in FIG. 9B, the hole filling ink 7 is filled and cured in the T / H of the formed substrate, and the photosensitive resin layer 3 is attached to the surface of the insulating substrate 1. As shown in FIG. 9D from above, a desired wiring pattern is printed with ultraviolet rays through the mask film 4.

【0005】次に、図10(a)に示す如く、現像液で
未露光部分の感光性樹脂層3を除去しエッチングレジス
ト5a,5bを得る。更に、図10(b)に示す如く、
露出した導体層2をエッチング除去した後、図10
(c)に示す如く、エッチングレジスト5a,5b及び
穴埋めインク7を剥離除去してT/H PWBを得るも
のである。尚、この工法では、感光性樹脂層3によるエ
ッチングレジスト5a,5bの代わりに、スクリーン印
刷に依って形成された画像をエッチングレジストとして
用いることもできる。
Next, as shown in FIG. 10A, the photosensitive resin layer 3 in the unexposed portion is removed with a developing solution to obtain etching resists 5a and 5b. Further, as shown in FIG.
After removing the exposed conductor layer 2 by etching, FIG.
As shown in (c), the etching resists 5a and 5b and the hole filling ink 7 are peeled and removed to obtain T / H PWB. In this method, instead of the etching resists 5a and 5b formed by the photosensitive resin layer 3, an image formed by screen printing can be used as the etching resist.

【0006】この他、図11(a)〜図12(b)に示
すポジ型感光性樹脂の電着コーティング工法は、図11
(a)に示す如く、絶縁基板1上に銅めっき層を含む導
体層2とスルーホール1aを形成した絶縁基板1表面に
図11(b)に示す如く、ポジ型感光性樹脂膜8を電着
コーティング,乾燥させた後、この上から図11(c)
に示す如く、マスクフィルム4を介して所望の配線回路
のパターンを紫外線で焼き付ける。
In addition to this, the electrodeposition coating method of the positive type photosensitive resin shown in FIGS.
As shown in FIG. 11A, a positive photosensitive resin film 8 is formed on the surface of the insulating substrate 1 in which a conductor layer 2 including a copper plating layer and a through hole 1a are formed on the insulating substrate 1 as shown in FIG. 11B. After coating the coating and drying, from above, see FIG. 11 (c).
As shown in FIG. 5, a desired wiring circuit pattern is printed with ultraviolet rays through the mask film 4.

【0007】次に、図11(d)に示す如く、現像液で
露光部分のポジ型感光性樹脂膜8を除去しエッチングレ
ジスト5a,5bを得る。更に、図12(a)に示す如
く、露出した導体層2をエッチング除去した後、最後
に、図12(b)に示す如く、エッチングレジスト5
a,5bを剥離除去してT/H PWBを得るものであ
る。
Next, as shown in FIG. 11D, the positive photosensitive resin film 8 in the exposed portion is removed with a developing solution to obtain etching resists 5a and 5b. Further, as shown in FIG. 12A, the exposed conductor layer 2 is removed by etching, and finally, as shown in FIG.
T / H PWB is obtained by peeling and removing a and 5b.

【0008】[0008]

【発明が解決しようとする課題】しかし、いずれの工法
の場合にも図7(b),図9(c),図11(b)の工
程に於て感光性樹脂層3,ポジ型感光性樹脂膜8の表面
に静電気による異物が付着し、マスクフィルムを介して
露光した際、未露光となり断線,欠損不良の原因となる
という問題点があった。
However, in any of the construction methods, the photosensitive resin layer 3 and the positive type photosensitive layer are used in the steps of FIGS. 7 (b), 9 (c) and 11 (b). There is a problem that foreign matter due to static electricity adheres to the surface of the resin film 8 and is not exposed when exposed through the mask film, which causes disconnection and defective defects.

【0009】本発明の目的は、静電気による異物の付着
がなく、未露光による断線,欠損不良のない印刷配線板
の製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a printed wiring board in which no foreign matter is attached due to static electricity and there is no disconnection or defective defect due to unexposed light.

【0010】[0010]

【課題を解決するための手段】本発明の印刷配線板の製
造方法は、銅張絶縁基板に穴を穿設する工程と、前記銅
張絶縁基板の穴及び表面に銅めっき層を形成する工程
と、前記銅めっき層の表面に感光性樹脂層を形成する工
程と、該感光性樹脂層上に導電性樹脂層を形成する工程
と、該導電性樹脂層上にマスクフィルムを当接し所定の
配線回路のパターンを露光する工程と、現像により未露
光部分の前記感光性樹脂層を選択的に除去する工程と、
現像により露出した銅部分をエッチングで除去する工程
と、残存する前記感光性樹脂層を除去する工程とを含み
配線回路を得る。
A method of manufacturing a printed wiring board according to the present invention comprises a step of forming a hole in a copper-clad insulating substrate and a step of forming a copper plating layer in the hole and the surface of the copper-clad insulating substrate. A step of forming a photosensitive resin layer on the surface of the copper plating layer, a step of forming a conductive resin layer on the photosensitive resin layer, and a mask film contacting the conductive resin layer on a predetermined surface A step of exposing the pattern of the wiring circuit, a step of selectively removing the photosensitive resin layer in the unexposed portion by development,
A wiring circuit is obtained including a step of removing the copper portion exposed by development by etching and a step of removing the remaining photosensitive resin layer.

【0011】[0011]

【実施例】以下に、本発明の実施例について図面を参照
して説明する。図1(a)〜図2(c)は本発明の第1
の実施例を説明する工程順に示した断面図である。
Embodiments of the present invention will be described below with reference to the drawings. 1 (a) to 2 (c) show the first embodiment of the present invention.
6A to 6D are cross-sectional views showing the steps in order of explaining the embodiment of FIG.

【0012】第1の実施例は、まず、図1(a)に示す
如く、絶縁基板1に穴を穿孔した後、導体層2を形成す
る。絶縁基板1の材質としては、例えば、ガラス布基材
エポキシ樹脂板やガラス基材ポリイミド樹脂板を使用出
来る。
In the first embodiment, first, as shown in FIG. 1A, a hole is drilled in the insulating substrate 1 and then the conductor layer 2 is formed. As the material of the insulating substrate 1, for example, a glass cloth-based epoxy resin plate or a glass-based polyimide resin plate can be used.

【0013】次に、図1(b)に示す如く、感光性樹脂
層3を形成する。
Next, as shown in FIG. 1B, a photosensitive resin layer 3 is formed.

【0014】次に、図1(c)に示す如く、ローラコー
ト法により導電性樹脂層9を形成する。尚、導電性樹脂
層9としてはポリアセチレン樹脂があり、アセトン等の
溶媒に溶かし、スプレーコート法,刷毛塗り等の方法で
塗布することが出来る。また膜厚としては、0.2〜2
μmが適当である。
Next, as shown in FIG. 1C, a conductive resin layer 9 is formed by a roller coating method. As the conductive resin layer 9, there is a polyacetylene resin, which can be applied by dissolving it in a solvent such as acetone and applying it by a spray coating method, a brush coating method or the like. The film thickness is 0.2 to 2
μm is suitable.

【0015】次に図1(d)に示す如く、マスクフィル
ム4を介して露光により所望の配線回路のパターンを焼
付ける。
Next, as shown in FIG. 1D, a desired wiring circuit pattern is printed by exposure through the mask film 4.

【0016】次に図2(a)に示す如く、炭酸ソーダ水
溶液等の現像液で現像し、エッチングレジスト5a,5
bを形成する。
Next, as shown in FIG. 2 (a), the etching resists 5a, 5 are developed by developing with a developing solution such as an aqueous solution of sodium carbonate.
b is formed.

【0017】次に、図2(b)に示す如く、導体層2の
内露出した銅部分をエッチング除去する。
Next, as shown in FIG. 2B, the exposed copper portion of the conductor layer 2 is removed by etching.

【0018】次に、図2(c)に示す如く、エッチング
レジスト5a,5bを水酸化ナトリューム等の薬品を用
いて除去して配線回路6を形成し、第1の実施例のT/
HPWBを得るものである。
Next, as shown in FIG. 2 (c), the etching resists 5a and 5b are removed by using a chemical such as sodium hydroxide to form a wiring circuit 6, and the T / T of the first embodiment is used.
To obtain HPWB.

【0019】図3(a)〜図4(c)は本発明の第2の
実施例を説明する工程順に示した断面図である。
FIGS. 3A to 4C are sectional views showing the second embodiment of the present invention in the order of steps.

【0020】第2の実施例は、まず図3(a)に示す如
く、絶縁基板1上に銅めっき層を含む導体層2とT/H
1aを形成する。
In the second embodiment, first, as shown in FIG. 3A, a conductor layer 2 including a copper plating layer and a T / H are formed on an insulating substrate 1.
1a is formed.

【0021】次に、図3(b)に示す如く、絶縁基板1
のT/H内部に穴埋めインク7を充填,硬化させる。
Next, as shown in FIG. 3B, the insulating substrate 1
The T / H inside is filled with the hole-filling ink 7 and cured.

【0022】次に、図3(c)に示す如く、絶縁基板1
表面に感光性樹脂層3を貼付する。尚、導電性樹脂層9
としてはポリアセチレン樹脂があり、アセトン等の溶媒
に溶かし、スプレーコート法,刷毛塗り等の方法で塗布
することが出来る。また、膜厚としては0.2〜2μm
が適当である。
Next, as shown in FIG. 3C, the insulating substrate 1
The photosensitive resin layer 3 is attached to the surface. The conductive resin layer 9
There is a polyacetylene resin, which can be dissolved in a solvent such as acetone and applied by a spray coating method, a brush coating method or the like. The film thickness is 0.2 to 2 μm.
Is appropriate.

【0023】次に、図3(d)に示す如く、感光性樹脂
層3の上にローラコート法等により導電性樹脂層9を形
成する。
Next, as shown in FIG. 3D, a conductive resin layer 9 is formed on the photosensitive resin layer 3 by a roller coating method or the like.

【0024】次に、図3(e)に示す如く、マスクフィ
ルム4を介して所望の配線パターンを紫外線で焼き付け
る。
Next, as shown in FIG. 3E, a desired wiring pattern is printed with ultraviolet rays through the mask film 4.

【0025】次に、図4(a)に示す如く、現像液で未
露光部分の感光性樹脂層3を除去してエッチングレジス
ト5a,5bを形成する。
Next, as shown in FIG. 4A, the photosensitive resin layer 3 in the unexposed portion is removed with a developing solution to form etching resists 5a and 5b.

【0026】次に、図4(b)に示す如く、導体層2の
内露出した銅部分をエッチング除去する。
Next, as shown in FIG. 4B, the exposed copper portion of the conductor layer 2 is removed by etching.

【0027】次に、図4(c)に示す如く、エッチング
レジスト5a,5b及び穴埋めインク7を、水酸化ナト
リューム等の薬品を用いて除去して、第2の実施例のT
/HPWBを得るものである。
Next, as shown in FIG. 4C, the etching resists 5a and 5b and the hole-filling ink 7 are removed by using a chemical such as sodium hydroxide, and the T of the second embodiment is removed.
/ HPWB.

【0028】図5(a)〜図6(c)は本発明の第3の
実施例を説明する工程順に示した断面図である。
5 (a) to 6 (c) are sectional views showing the third embodiment of the present invention in the order of steps.

【0029】第3の実施例は、まず、図5(a)に示す
如く、絶縁基板1上に銅めっき層を含む導体層2とT/
H1aを形成する。
In the third embodiment, first, as shown in FIG. 5A, a conductor layer 2 including a copper plating layer and a T / T layer are formed on an insulating substrate 1.
H1a is formed.

【0030】次に、図5(b)に示す如く、絶縁基板1
表面にポジ型感光性樹脂膜8を電着コーティング,乾燥
させる。
Next, as shown in FIG. 5B, the insulating substrate 1
The positive photosensitive resin film 8 is electrodeposited on the surface and dried.

【0031】次に、図3(c)に示す如く、ローラコー
ト法により導電性樹脂層9を形成する。
Next, as shown in FIG. 3C, the conductive resin layer 9 is formed by the roller coating method.

【0032】尚、導電性樹脂層9としてはポリアセチレ
ン樹脂があり、アセトン等の溶媒に溶かし、スプレーコ
ート法,刷毛塗り等の方法で塗布することが出来る。ま
た、膜厚としては、0.2〜2μmが適当である。
As the conductive resin layer 9, there is polyacetylene resin, which can be applied by dissolving it in a solvent such as acetone and applying it by a spray coating method, a brush coating method or the like. Further, the suitable film thickness is 0.2 to 2 μm.

【0033】次に、図5(d)に示す如く、導電性樹脂
層9の上からマスクフィルム4を介して所望の配線回路
のパターンを紫外線で焼き付ける。
Next, as shown in FIG. 5D, a desired wiring circuit pattern is printed on the conductive resin layer 9 through the mask film 4 with ultraviolet rays.

【0034】次に、図6(a)に示す如く、現像液で露
光部分のポジ型感光性樹脂膜8を除去し、エッチングレ
ジスト5a,5bを形成する。
Next, as shown in FIG. 6A, the positive photosensitive resin film 8 in the exposed portion is removed with a developing solution to form etching resists 5a and 5b.

【0035】次に、図6(b)に示す如く、露出した導
体層2をエッチング除去する。
Next, as shown in FIG. 6B, the exposed conductor layer 2 is removed by etching.

【0036】次に、図6(c)に示す如く、エッチング
レジスト5a,5bを水酸化ナトリューム等の薬品を用
いて除去して、第3の実施例のT/H PWBを得るも
のである。
Next, as shown in FIG. 6C, the etching resists 5a and 5b are removed by using a chemical such as sodium hydroxide to obtain the T / H PWB of the third embodiment.

【0037】[0037]

【発明の効果】以上の説明から明らかなように本発明
は、感光性樹脂層、又は、ポジ型感光性樹脂膜上に導電
性樹脂層を形成し、露光,エッチングを行うことによ
り、従来の感光性樹脂層、又は、ポジ型感光性樹脂膜上
の静電気による異物付着を防止でき、未露光による断
線,欠損不良を低減することができる効果がある。
As is apparent from the above description, according to the present invention, a conductive resin layer is formed on a photosensitive resin layer or a positive type photosensitive resin film, and exposure and etching are performed. It is possible to prevent foreign matter from adhering to the photosensitive resin layer or the positive type photosensitive resin film due to static electricity, and to reduce disconnection and defective defects due to unexposed light.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明する工程順に示し
た断面図である。
FIG. 1 is a cross-sectional view showing a process sequence of a first embodiment of the present invention.

【図2】本発明の第1の実施例を説明する工程順に示し
た断面図である。
2A to 2D are cross-sectional views showing a process sequence for explaining the first embodiment of the present invention.

【図3】本発明の第2の実施例を説明する工程順に示し
た断面図である。
3A to 3D are cross-sectional views showing a second embodiment of the present invention in the order of steps.

【図4】本発明の第2の実施例を説明する工程順に示し
た断面図である。
4A to 4D are cross-sectional views showing a second embodiment of the present invention in the order of steps.

【図5】本発明の第3の実施例を説明する工程順に示し
た断面図である。
5A to 5C are sectional views showing a process sequence for explaining a third embodiment of the present invention.

【図6】本発明の第3の実施例を説明する工程順に示し
た断面図である。
6A to 6C are cross-sectional views showing a process sequence for explaining a third embodiment of the present invention.

【図7】従来のテンティング工法による印刷配線板の製
造方法を説明する工程順に示した断面図である。
7A to 7C are cross-sectional views showing a method of manufacturing a printed wiring board by a conventional tenting method in order of steps.

【図8】従来のテンティング工法による印刷配線板の製
造方法を説明する工程順に示した断面図である。
FIG. 8 is a cross-sectional view showing a method of manufacturing a printed wiring board by a conventional tenting method, in the order of steps.

【図9】従来の穴埋め工法による印刷配線板の製造方法
を説明する工程順に示した断面図である。
FIG. 9 is a cross-sectional view showing the method of manufacturing a printed wiring board by a conventional hole filling method in the order of steps.

【図10】従来の穴埋め工法による印刷配線板の製造方
法を説明する工程順に示した断面図である。
FIG. 10 is a cross-sectional view showing a method of manufacturing a printed wiring board by a conventional hole filling method in the order of steps.

【図11】従来のポジ型感光性樹脂の電着コーティング
法による印刷配線板の製造方法を説明する工程順に示し
た断面図である。
FIG. 11 is a cross-sectional view showing, in the order of steps, a method of manufacturing a printed wiring board by a conventional positive-type photosensitive resin electrodeposition coating method.

【図12】従来のポジ型感光性樹脂の電着コーティング
法による印刷配線板の製造方法を説明する工程順に示し
た断面図である。
FIG. 12 is a cross-sectional view showing the order of steps for explaining a conventional method for manufacturing a printed wiring board by electrodeposition coating of a positive photosensitive resin.

【符号の説明】[Explanation of symbols]

1 絶縁基板 1a T/H 2 導体層 3 感光性樹脂層 4 マスクフィルム 5a,5b エッチングレジスト 6 配線回路 7 穴埋めインク 8 ポジ型感光性樹脂膜 9 導電性樹脂層 1 Insulating Substrate 1a T / H 2 Conductor Layer 3 Photosensitive Resin Layer 4 Mask Film 5a, 5b Etching Resist 6 Wiring Circuit 7 Hole Filling Ink 8 Positive Photosensitive Resin Film 9 Conductive Resin Layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 銅張絶縁基板に穴を穿設する工程と、前
記銅張絶縁基板の穴及び表面に銅めっき層を形成する工
程と、前記銅めっき層の表面に感光性樹脂層を形成する
工程と、該感光性樹脂層上に導電性樹脂層を形成する工
程と、該導電性樹脂層上にマスクフィルムを当接し所定
の配線回路のパターンを露光する工程と、現像により未
露光部分の前記感光性樹脂層を選択的に除去する工程
と、現像により露出した銅部分をエッチングで除去する
工程と、残存する前記感光性樹脂層を除去する工程とを
含み配線回路を得ることを特徴とする印刷配線板の製造
方法。
1. A step of forming a hole in a copper-clad insulating substrate, a step of forming a copper plating layer in the hole and the surface of the copper-clad insulating substrate, and forming a photosensitive resin layer on the surface of the copper plating layer. A step of forming a conductive resin layer on the photosensitive resin layer, a step of exposing a predetermined wiring circuit pattern by contacting a mask film on the conductive resin layer, and an unexposed portion by development. And a step of selectively removing the photosensitive resin layer, a step of removing the copper portion exposed by development by etching, and a step of removing the remaining photosensitive resin layer to obtain a wiring circuit. And a method for manufacturing a printed wiring board.
JP4428692A 1992-03-02 1992-03-02 Manufacturing method of printed wiring board Expired - Fee Related JP2723744B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4428692A JP2723744B2 (en) 1992-03-02 1992-03-02 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4428692A JP2723744B2 (en) 1992-03-02 1992-03-02 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH05243709A true JPH05243709A (en) 1993-09-21
JP2723744B2 JP2723744B2 (en) 1998-03-09

Family

ID=12687264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4428692A Expired - Fee Related JP2723744B2 (en) 1992-03-02 1992-03-02 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP2723744B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106525114A (en) * 2016-11-08 2017-03-22 江门崇达电路技术有限公司 Method for testing production line hole making capability in positive process
CN106556422A (en) * 2016-11-08 2017-04-05 江门崇达电路技术有限公司 The method of testing of production line drilling ability in a kind of negative film technique

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106525114A (en) * 2016-11-08 2017-03-22 江门崇达电路技术有限公司 Method for testing production line hole making capability in positive process
CN106556422A (en) * 2016-11-08 2017-04-05 江门崇达电路技术有限公司 The method of testing of production line drilling ability in a kind of negative film technique
CN106556422B (en) * 2016-11-08 2018-12-07 江门崇达电路技术有限公司 The test method of production line drilling ability in a kind of negative film technique
CN106525114B (en) * 2016-11-08 2018-12-07 江门崇达电路技术有限公司 The test method of production line drilling ability in a kind of positive blade technolgy

Also Published As

Publication number Publication date
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