JP2583365B2 - Manufacturing method of printed wiring board - Google Patents

Manufacturing method of printed wiring board

Info

Publication number
JP2583365B2
JP2583365B2 JP3141701A JP14170191A JP2583365B2 JP 2583365 B2 JP2583365 B2 JP 2583365B2 JP 3141701 A JP3141701 A JP 3141701A JP 14170191 A JP14170191 A JP 14170191A JP 2583365 B2 JP2583365 B2 JP 2583365B2
Authority
JP
Japan
Prior art keywords
hole
land
conductor layer
resin coating
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3141701A
Other languages
Japanese (ja)
Other versions
JPH04365392A (en
Inventor
要 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Toppan Circuit Solutions Toyama Inc
Original Assignee
NEC Toppan Circuit Solutions Toyama Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Toppan Circuit Solutions Toyama Inc filed Critical NEC Toppan Circuit Solutions Toyama Inc
Priority to JP3141701A priority Critical patent/JP2583365B2/en
Publication of JPH04365392A publication Critical patent/JPH04365392A/en
Application granted granted Critical
Publication of JP2583365B2 publication Critical patent/JP2583365B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は印刷配線板の製造方法に
関し、特に高密度の配線回路を有する印刷配線板の製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board having a high-density wiring circuit.

【0002】[0002]

【従来の技術】一般に、高密度の配線回路を有する印刷
配線板(以下PWBと称す)の製造には、図4(a)〜
(d)及び図5(a)〜(c)の如く、穴埋め工法が用
いられており、この方法に寄れば、図4(a)の如く、
銅めっき層を含む導体層1とスルーホール1eを形成し
た絶縁基板2のスルーホール1e内部に図4(b)のよ
うに、穴埋め樹脂7を充填,硬化させ、更に、図4
(c)の如く、絶縁基板2表面に感光性ドライフィルム
6を貼付け、この上から図4(d)の如く、所定の配線
パターンを有するマスクフィルム4を当接し、紫外線5
で焼き付ける。次に、現像液で未露光部分の感光性ドラ
イフィルム6を除去し、図5(a)の如く、配線回路部
分のエッチングレジスト6aを得る。
2. Description of the Related Art Generally, a printed wiring board (hereinafter referred to as PWB) having a high-density wiring circuit is manufactured by using FIGS.
As shown in FIG. 4D and FIG. 5A to FIG. 5C, a hole filling method is used.
As shown in FIG. 4B, the inside of the through hole 1e of the insulating substrate 2 in which the conductor layer 1 including the copper plating layer and the through hole 1e are formed is filled and cured as shown in FIG.
4C, a photosensitive dry film 6 is attached to the surface of the insulating substrate 2, and a mask film 4 having a predetermined wiring pattern is brought into contact with the photosensitive dry film 6 as shown in FIG.
Bake. Next, the photosensitive dry film 6 in the unexposed portion is removed with a developer to obtain an etching resist 6a in a wiring circuit portion as shown in FIG.

【0003】更に、図5(b)の如く、露出した導体層
1をエッチング除去した後、最後に、図5(c)の如
く、エッチングレジスト6a及び穴埋め樹脂7を剥離除
去してPWBを得る。
Further, after the exposed conductor layer 1 is removed by etching as shown in FIG. 5 (b), finally, as shown in FIG. 5 (c), the etching resist 6a and the filling resin 7 are peeled off to obtain PWB. .

【0004】尚、この工法では、感光性ドライフィルム
6の代わりに、スクリーン印刷によって形成された画像
をエッチングレジストとして用いることもできる。
In this method, instead of the photosensitive dry film 6, an image formed by screen printing can be used as an etching resist.

【0005】[0005]

【発明が解決しようとする課題】上述した従来工法に於
て、ランドの無いスルーホールを有するPWBを得る場
合、所定の径より大なるスルーホールに対しては、穴埋
め樹脂が均一に充填されにくく、スルーホールの形成が
困難なため、図6の如く、穴径のばらつきが大きくなり
部品実装時の位置決め精度が低下するという問題点があ
った。
In the above-mentioned conventional method, when obtaining a PWB having a through hole without a land, it is difficult to fill the through hole larger than a predetermined diameter with a uniform filling resin. In addition, since it is difficult to form a through hole, as shown in FIG. 6, there is a problem that the variation in the hole diameter becomes large and the positioning accuracy at the time of component mounting is reduced.

【0006】本発明の目的は、穴径のばらつきの小さい
ランドの無いスルーホールを形成し、部品実装時の位置
決め精度の高い印刷配線板の製造方法を提供することに
ある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a printed wiring board having a land-free through-hole with a small variation in hole diameter and high positioning accuracy when mounting components.

【0007】[0007]

【課題を解決するための手段】本発明の印刷配線板の製
造方法は、導体層とスルーホールが形成された絶縁基板
の前記スルーホールと前記導体層表面にポジ型感光性樹
脂塗膜を電着コーティングする工程と、ランドを有する
スルーホールには該スルーホール径より大なる部分とラ
ンドの無いスルーホールには該スルーホール径に対して
50〜300μm小さい部分及び配線部分には遮光する
ようなパターンを有するマスクフィルムを当接しプリン
タにより露光する工程と、現像により露光されたポジ型
感光性樹脂塗膜を選択的に除去する工程と、現像により
露出した前記導体層をエッチングで除去する工程と、更
に残存する前記ポジ型観光性樹脂塗膜を除去する工程と
を有し、ランドを有するスルーホール及び穴径のばらつ
きの小さいランドの無いスルーホール及び配線回路を得
ることを特徴とする。
According to the method of manufacturing a printed wiring board of the present invention, a positive photosensitive resin coating film is applied to the through holes and the surface of the conductor layer of an insulating substrate having the conductor layer and the through holes formed thereon. In the step of coating and coating, a portion larger than the diameter of the through hole for a through hole having a land and a portion smaller than the diameter of the through hole by 50 to 300 μm for a through hole having no land and a wiring portion are shielded from light. A step of abutting a mask film having a pattern and exposing by a printer, a step of selectively removing a positive photosensitive resin coating film exposed by development, and a step of etching and removing the conductor layer exposed by development. And a step of removing the remaining positive-type tourist resin coating film, and a land having a land with a small variation in through-holes and hole diameters. Characterized in that to obtain a free through-holes and the wiring circuit.

【0008】[0008]

【実施例】以下に、本発明の実施例について図面を参照
して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0009】図1(a)〜(c)及び図2(a)〜
(c)は本発明の一実施例を説明する工程順に示した断
面図である。
1 (a) to 1 (c) and 2 (a) to 2 (a)
(C) is sectional drawing shown in order of the process explaining one Example of this invention.

【0010】まず図1(a)に示すように、絶縁基板2
に銅めっき処理を施し、導体層1とスルーホール1eを
形成する。絶縁基板2の材質としては、例えば、ガラス
布基材エポキシ樹脂板やガラス布基材ポリイミド樹脂板
を使用する。
First, as shown in FIG.
Is subjected to a copper plating process to form a conductor layer 1 and a through hole 1e. As a material of the insulating substrate 2, for example, a glass cloth base epoxy resin plate or a glass cloth base polyimide resin plate is used.

【0011】次に、図1(b)の如く、絶縁基板の表面
全体に厚さ3〜15μmのポジ型感光性樹脂塗膜3aを
電着コーティングにより形成した後乾燥する。
Next, as shown in FIG. 1B, a positive photosensitive resin coating 3a having a thickness of 3 to 15 μm is formed on the entire surface of the insulating substrate by electrodeposition coating and then dried.

【0012】更に、図1(c)の如く、ポジ型感光性樹
脂塗膜3aの上にランドを有するスルーホール及びラン
ドの無いスルーホール及び配線部は光を遮断するような
パターンを有するマスクフィルム4を当接しプリンタに
より200〜1000mJ/cm2 の紫外線5を照射す
る。これにより全てのスルーホール1e内は露光されな
い。
Further, as shown in FIG. 1 (c), a mask film having a pattern in which through-holes having lands and through-holes without lands and wiring portions on the positive type photosensitive resin coating film 3a block light is provided. 4 and is irradiated with ultraviolet rays 5 of 200 to 1000 mJ / cm @ 2 by a printer. Thus, the inside of all through holes 1e is not exposed.

【0013】次に、マスクフィルム4を取り外し、図2
(a)のように、露光されたポジ型感光性樹脂塗膜3b
をpH10〜pH13のアルカリ水溶液等の現像液で除
去する。このアルカリ水溶液としてNa2 Co3 や、N
a2 SiO3 等を用いることが出来る。
Next, the mask film 4 is removed, and FIG.
As shown in (a), the exposed positive photosensitive resin coating film 3b
Is removed with a developer such as an aqueous alkaline solution having a pH of 10 to 13. As the alkaline aqueous solution, Na2 Co3, N2
a2 SiO3 or the like can be used.

【0014】この後、図2(b)の如く、露出した導体
層1を酸性のエッチング液により除去する。
Thereafter, as shown in FIG. 2B, the exposed conductor layer 1 is removed with an acidic etchant.

【0015】次に、図2(c)に示すように、ポジ型感
光性樹脂塗膜3aを1〜4パーセントのNaOHまたは
KOH等の温水溶液で剥離除去し、配線回路1cとラン
ドを有するスルーホール1a及びランドの無いスルーホ
ール1bを有するPWBが得られる。
Next, as shown in FIG. 2C, the positive photosensitive resin coating film 3a is peeled off with a hot aqueous solution of 1 to 4% of NaOH or KOH to remove the wiring circuit 1c and a land having a land. A PWB having a hole 1a and a through hole 1b without a land is obtained.

【0016】図3は図1(c)の露光工程を説明する断
面図である。
FIG. 3 is a sectional view for explaining the exposure step of FIG.

【0017】図3に示すように、ランドの無いスルーホ
ールを形成する部分は、穴径に対して50〜300μm
小さい部分を遮光するようなマスクフィルム4を当接す
れば、スルーホール内を十分遮光できる。
As shown in FIG. 3, the portion forming a through hole without a land has a diameter of 50 to 300 μm with respect to the hole diameter.
By contacting the mask film 4 which shields a small portion from light, the inside of the through hole can be sufficiently shielded from light.

【0018】尚、図1(c)に於て散乱光紫外線を用い
ることもできる。
In FIG. 1 (c), scattered ultraviolet light can be used.

【0019】[0019]

【発明の効果】以上から明らかなように本発明によれ
ば、従来の穴埋め工法に比べ、穴径のばらつきの小さい
ランドの無いスルーホールを有するPWBを得ることが
可能となり部品実装時の位置決め精度が向上する。
As is apparent from the above, according to the present invention, it is possible to obtain a PWB having a landless through-hole with a small variation in hole diameter as compared with the conventional hole filling method, and the positioning accuracy at the time of component mounting can be obtained. Is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を説明する工程順に示した断
面図である。
FIG. 1 is a cross-sectional view shown in the order of steps for explaining an embodiment of the present invention.

【図2】本発明の一実施例を説明する工程順に示した断
面図である。
FIG. 2 is a cross-sectional view shown in the order of steps for explaining an embodiment of the present invention.

【図3】図1(c)の露光工程を説明する断面図であ
る。
FIG. 3 is a cross-sectional view illustrating an exposure step of FIG. 1 (c).

【図4】従来の穴埋め工法によるPWBの製造方法を説
明する工程順に示した断面図である。
FIG. 4 is a cross-sectional view showing a PWB manufacturing method by a conventional hole filling method in the order of steps for explaining the method.

【図5】従来の穴埋め工法によるPWBの製造方法を説
明する工程順に示した断面図である。
FIG. 5 is a cross-sectional view shown in the order of steps for explaining a PWB manufacturing method by a conventional hole filling method.

【図6】従来の穴埋め工法によるランドの無いスルーホ
ール部分の断面図である。
FIG. 6 is a cross-sectional view of a through-hole portion having no land by a conventional hole filling method.

【符号の説明】[Explanation of symbols]

1 導体層 1a ランドを有するスルーホール 1b ランドの無いスルーホール 1c 配線回路 1e スルーホール 2 絶縁基板 3a ポジ型感光性樹脂塗膜 3b 露光されたポジ型感光性樹脂塗膜 4 マスクフィルム 5 紫外線 6 感光性ドライフィルム 6a 配線回路部分のエッチングレジスト 7 穴埋め樹脂 REFERENCE SIGNS LIST 1 conductor layer 1a through hole with land 1b through hole without land 1c wiring circuit 1e through hole 2 insulating substrate 3a positive photosensitive resin coating 3b exposed positive photosensitive resin coating 4 mask film 5 ultraviolet ray 6 photosensitive Dry film 6a Etching resist for wiring circuit 7 Resin filling

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 導体層とスルーホールが形成された絶縁
基板の前記スルーホールと前記導体層表面にポジ型感光
性樹脂塗膜を電着コーティングする工程と、ランドを有
するスルーホールには該スルーホール径より大なる部分
とランドの無いスルーホールには該スルーホール径に対
して50〜300μm小さい部分及び配線部分には遮光
するようなパターンを有するマスクフィルムを当接しプ
リンタにより露光する工程と、現像により露光されたポ
ジ型感光性樹脂塗膜を選択的に除去する工程と、現像に
より露出した前記導体層をエッチングで除去する工程
と、更に残存する前記ポジ型観光性樹脂塗膜を除去する
工程とを有し、ランドを有するスルーホール及び穴径の
ばらつきの小さいランドの無いスルーホール及び配線回
路を得ることを特徴とする印刷配線板の製造方法。
A step of electrodepositing a positive photosensitive resin coating on the through hole of the insulating substrate having the conductor layer and the through hole formed thereon and the surface of the conductor layer; A step of abutting a mask film having a pattern that shields light to a portion larger than the hole diameter and a through hole having no land by 50 to 300 μm with respect to the through hole diameter and a wiring portion, and exposing by a printer; A step of selectively removing the positive-type photosensitive resin coating film exposed by development, a step of removing the conductor layer exposed by development by etching, and further removing the remaining positive-type tourist resin coating film And a step of obtaining a through-hole having a land and a through-hole and a wiring circuit without a land having a small variation in hole diameter. Method of manufacturing a printed wiring board that.
JP3141701A 1991-06-13 1991-06-13 Manufacturing method of printed wiring board Expired - Fee Related JP2583365B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3141701A JP2583365B2 (en) 1991-06-13 1991-06-13 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3141701A JP2583365B2 (en) 1991-06-13 1991-06-13 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH04365392A JPH04365392A (en) 1992-12-17
JP2583365B2 true JP2583365B2 (en) 1997-02-19

Family

ID=15298193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3141701A Expired - Fee Related JP2583365B2 (en) 1991-06-13 1991-06-13 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP2583365B2 (en)

Also Published As

Publication number Publication date
JPH04365392A (en) 1992-12-17

Similar Documents

Publication Publication Date Title
WO2005022970A1 (en) Method for manufacturing printed wiring board and printed wiring board
JPH0135518B2 (en)
JP3031042B2 (en) Printed wiring board for surface mounting
JP2583365B2 (en) Manufacturing method of printed wiring board
JPH04348591A (en) Manufacture of printed circuit board
KR100688702B1 (en) Manufacturing method of printed circuit board with landless via hole
JP2723744B2 (en) Manufacturing method of printed wiring board
JP2625968B2 (en) Printed wiring board
JPH08186373A (en) Manufacture of printed wiring board
JPS6012791A (en) Method of producing printed circuit board
KR101519545B1 (en) Manufacturing method of circuit board for car black box
JPH02251195A (en) Manufacture of printed wiring board
JPH05218641A (en) Manufacture of printed wiring board
JPH0353587A (en) Formation of resist pattern
JP2910261B2 (en) Printed wiring board and its manufacturing method
JPH03256393A (en) Manufacture of printed wiring board
JP2701408B2 (en) Manufacturing method of printed wiring board
JPH077264A (en) Manufacture of printed wiring board
JPH0567871A (en) Printed-wiring board and manufacture thereof
JP3686717B2 (en) Mask for solder paste printing
JPH04186791A (en) Manufacture of printed wiring board
JPH06318774A (en) Manufacturing method of printed-wiring board
JPH01321683A (en) Manufacture of printed wiring board
JPS6155796B2 (en)
JPH08186381A (en) Multilayer printed wiring board and its manufacturing method

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19961008

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

R371 Transfer withdrawn

Free format text: JAPANESE INTERMEDIATE CODE: R371

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071121

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081121

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081121

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091121

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091121

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101121

Year of fee payment: 14

LAPS Cancellation because of no payment of annual fees