JPH118465A - Manufacture of printed wiring board through additive method - Google Patents
Manufacture of printed wiring board through additive methodInfo
- Publication number
- JPH118465A JPH118465A JP17515397A JP17515397A JPH118465A JP H118465 A JPH118465 A JP H118465A JP 17515397 A JP17515397 A JP 17515397A JP 17515397 A JP17515397 A JP 17515397A JP H118465 A JPH118465 A JP H118465A
- Authority
- JP
- Japan
- Prior art keywords
- resist layer
- plating
- plating resist
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、アディティブ法プ
リント配線板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an additive method printed wiring board.
【0002】[0002]
【従来の技術】図2は、従来のアディティブ法プリント
配線板の製造方法を説明する断面図を示し、同図に基づ
いて説明する。同図において、接着剤付き絶縁基板1に
ドリル加工により貫通穴4を穿孔し、無電解銅めっきを
析出させるためにめっき触媒処理を施した後、めっきレ
ジスト層2を設け、無電解銅めっきを施し前記めっきレ
ジスト層2以外の部分に導体回路3を形成する。次に、
部品実装に関係のない、たとえば部品実装ランド5以外
の銅箔表面をソルダーレジスト層6によって覆う。この
ソルダーレジスト層6は、熱硬化タイプまたは紫外線
(以下UVという)硬化タイプのインクを用い、印刷法
または写真法で形成するが、一般的には、このソルダー
レジスト層6は無電解ニッケル・金めっきには耐えられ
るものがあるが、処理時間が長くなる無電解銅めっきに
は耐えられるものがない。2. Description of the Related Art FIG. 2 is a cross-sectional view for explaining a conventional method of manufacturing a printed wiring board by the additive method, which will be described with reference to FIG. In the figure, a through hole 4 is drilled in an insulating substrate 1 with an adhesive, a plating catalyst treatment is performed to deposit electroless copper plating, a plating resist layer 2 is provided, and electroless copper plating is performed. Then, a conductor circuit 3 is formed in a portion other than the plating resist layer 2. next,
The copper foil surface which is not related to the component mounting, for example, other than the component mounting land 5 is covered with the solder resist layer 6. The solder resist layer 6 is formed by a printing method or a photographic method using a thermosetting type or ultraviolet (hereinafter referred to as UV) curing type ink. In general, the solder resist layer 6 is made of electroless nickel / gold. Some of them can withstand plating, but none can withstand electroless copper plating, which requires a long processing time.
【0003】[0003]
【発明が解決しようとする課題】上述した方法で形成さ
れるソルダーレジスト層6は、印刷法においては印刷ず
れやソルダーレジストインクのにじみにより部品実装に
必要な部品実装ランド5の銅箔面積が得られないことが
あり、写真法では印刷法と同様の問題が生じることもあ
るが、現像処理工程で部品実装ランド5の銅箔表面に薄
いソルダーレジスト被膜が残渣として形成され、はんだ
付け不良を生じる危険性もある。In the printing method, the solder resist layer 6 formed by the above-described method has a copper foil area of the component mounting land 5 necessary for component mounting due to printing misalignment or bleeding of the solder resist ink. In some cases, the same problem as in the printing method may occur in the photographic method, but a thin solder resist film is formed as a residue on the copper foil surface of the component mounting land 5 in the developing process, resulting in poor soldering. There is also danger.
【0004】また、アディティブ法プリント配線板Pは
図2に示すように、めっきレジスト層2は通常導体回路
3を形成した後、除去しないため無電解銅めっき処理後
は、このプリント配線板Pの表面は平滑となっている。
その後、部品実装ランド5以外の銅箔表面にソルダーレ
ジスト層6を設けることによって、この表面の平滑性の
特徴が失われてしまうことがある。Further, as shown in FIG. 2, the additive printed circuit board P is not removed after the plating resist layer 2 is formed, usually after the conductor circuit 3 is formed. The surface is smooth.
Thereafter, by providing the solder resist layer 6 on the surface of the copper foil other than the component mounting lands 5, the smoothness characteristic of the surface may be lost.
【0005】本発明では、前記のめっきレジスト層2の
形成で用いた耐めっき液性のドライフィルムを第2のめ
っきレジスト層(ソルダーレジスト層)16として用
い、これと無電解銅めっきとの組合せにより部品実装に
必要な部品実装ランド5の銅箔面積を確保し、かつプリ
ント配線板Pの表面が平滑となるアディティブ法プリン
ト配線板の製造方法を提供するものである。In the present invention, the plating solution resistant dry film used in the formation of the plating resist layer 2 is used as a second plating resist layer (solder resist layer) 16, and this is combined with electroless copper plating. Accordingly, a method of manufacturing an additive-type printed wiring board in which the copper foil area of the component mounting land 5 necessary for component mounting is secured and the surface of the printed wiring board P is smoothed.
【0006】[0006]
【課題を解決するための手段】前記した課題を解決する
ために、図1に示すように接着剤付き絶縁基板1に、貫
通穴4を穿孔し、めっきレジスト層2を形成し、粗面化
処理後に第1の無電解銅めっきにより導体回路3を形成
する。その次に、前記のめっきレジスト層2と導体回路
3の上に、第2のめっきレジスト層(ソルダーレジスト
層)16を形成するため、前記のめっきレジスト層2に
用いたドライフィルムをラミネートし、露光,現像、そ
してUV硬化を行い、必要な部品実装ランド5以外を被
覆する第2のめっきレジスト層16を設ける。その後、
第2の無電解銅めっきを行って第2の導体回路15を形
成する。In order to solve the above-mentioned problems, as shown in FIG. 1, a through hole 4 is formed in an insulating substrate 1 with an adhesive, a plating resist layer 2 is formed, and the surface is roughened. After the treatment, the conductor circuit 3 is formed by the first electroless copper plating. Next, a dry film used for the plating resist layer 2 is laminated on the plating resist layer 2 and the conductor circuit 3 to form a second plating resist layer (solder resist layer) 16 on the conductive film 3. Exposure, development, and UV curing are performed to provide a second plating resist layer 16 covering portions other than the necessary component mounting lands 5. afterwards,
A second conductive circuit 15 is formed by performing a second electroless copper plating.
【0007】[0007]
【発明の実施の形態】以下、本発明の実施の形態を図1
に基づいて説明する。同図は、本発明に係るアディティ
ブ法プリント配線板の製造方法を説明する断面図であ
る。図1に示すように、接着剤付き絶縁基板1(日立化
成工業株式会社の商品名:ACL−E−168)にドリ
ルで貫通穴4を穿孔し、めっき触媒処理を施した後、こ
の接着剤付き絶縁基板1に耐めっき液性のドライフィル
ム(日立化成工業株式会社の商品名:SR−3000)
をラミネートする。次にネガフィルムを用いて焼付機で
露光,現像処理し、UV硬化または熱硬化を行って導体
回路3以外の部分に、めっきレジスト層2を形成し、粗
面化処理後、第1の無電解銅めっきで導体回路3を形成
する。FIG. 1 is a block diagram showing an embodiment of the present invention.
It will be described based on. FIG. 3 is a cross-sectional view illustrating a method for manufacturing an additive method printed wiring board according to the present invention. As shown in FIG. 1, a through-hole 4 is drilled in an insulating substrate 1 with an adhesive (trade name: ACL-E-168 of Hitachi Chemical Co., Ltd.), and a plating catalyst treatment is performed. Plating solution-resistant dry film on the insulating substrate 1 with a coating solution (trade name of Hitachi Chemical Co., Ltd .: SR-3000)
Is laminated. Next, using a negative film, the film is exposed and developed by a printing machine, and is subjected to UV curing or thermal curing to form a plating resist layer 2 on a portion other than the conductor circuit 3. The conductor circuit 3 is formed by electrolytic copper plating.
【0008】その次に、第2のめっきレジスト層(ソル
ダーレジスト層)16を形成するために、めっきレジス
ト層2で使用したドライフィルムをラミネートする。ラ
ミネート後、ネガフィルムを用いて露光,現像そしてU
V硬化を行い、スルーホール部および部品実装ランド5
以外を第2のめっきレジスト層16で被覆する。その
後、第2の無電解銅めっきを行って第2の導体回路15
を形成する。この第2の無電解銅めっきで形成する第2
の導体回路15には、スルーホール部と部品実装ランド
5のみとし、配線用の導体回路は第1の無電解銅めっき
で形成する導体回路3に配置することもできる。Next, in order to form a second plating resist layer (solder resist layer) 16, the dry film used for the plating resist layer 2 is laminated. After lamination, exposure using a negative film, development and U
V-cured, through-holes and component mounting lands 5
Are covered with a second plating resist layer 16. Then, a second electroless copper plating is performed to form the second conductor circuit 15.
To form The second formed by this second electroless copper plating
The conductor circuit 15 may include only the through-hole portion and the component mounting land 5, and the conductor circuit for wiring may be disposed on the conductor circuit 3 formed by the first electroless copper plating.
【0009】上述した本発明によるアディティブ法プリ
ント配線板の製造方法で形成される第2のめっきレジス
ト層(ソルダーレジスト層)16は必ずしも、めっきレ
ジスト層2とは平面上の位置が一致しない。しかし、第
2のめっきレジスト層16の位置ずれ部分にあるめっき
レジスト層2の上にも第2の無電解銅めっきによって第
2の導体回路15が形成されるため部品実装に必要な銅
箔面積を安定して確保した部品実装ランド5を形成でき
る。さらに、第2のめっきレジスト層16と第2の導体
回路15(部品実装ランド5)とは高さが、ほぼ同一に
なるためプリント配線板Pの表面は平滑となる。The second plating resist layer (solder resist layer) 16 formed by the above-described method for manufacturing an additive printed wiring board according to the present invention does not always coincide with the plating resist layer 2 on a plane. However, since the second conductive circuit 15 is also formed by the second electroless copper plating on the plating resist layer 2 at the position where the second plating resist layer 16 is displaced, the copper foil area required for component mounting is required. Can be formed stably. Further, since the heights of the second plating resist layer 16 and the second conductor circuit 15 (the component mounting land 5) are substantially the same, the surface of the printed wiring board P becomes smooth.
【0010】[0010]
【発明の効果】以上、説明したように本発明によれば、
次の効果がある。 (1)第2のめっきレジスト層16の位置ずれが生じて
も、この工程後に第2の無電解銅めっきによって部品実
装ランド5を形成することで部品実装に必要な銅箔面積
を安定して確保できる。 (2)部品実装ランド5のみ第2の無電解銅めっきで第
2の導体回路に形成すれば、部品実装の作業性,検査効
率,品質などの大幅改善となる。 (3)本発明では、無電解銅めっきで導体回路3,15
の厚さを制御することができ、第2のめっきレジスト層
16と第2の導体回路15とは、ほぼ同一の高さとなり
表面が平滑なプリント配線板Pが得られる。As described above, according to the present invention,
It has the following effects: (1) Even if the displacement of the second plating resist layer 16 occurs, the component mounting land 5 is formed by the second electroless copper plating after this step, so that the copper foil area required for component mounting can be stably maintained. Can be secured. (2) If only the component mounting land 5 is formed on the second conductor circuit by the second electroless copper plating, the workability, the inspection efficiency, the quality, and the like of the component mounting can be greatly improved. (3) In the present invention, the conductor circuits 3, 15 are formed by electroless copper plating.
And the second plating resist layer 16 and the second conductive circuit 15 have substantially the same height, and a printed wiring board P having a smooth surface can be obtained.
【図1】本発明に係るアディティブ法プリント配線板の
製造方法を説明する断面図。FIG. 1 is a cross-sectional view illustrating a method of manufacturing an additive printed wiring board according to the present invention.
【図2】従来のアディティブ法プリント配線板の製造方
法を説明する断面図。FIG. 2 is a cross-sectional view illustrating a method for manufacturing a conventional additive printed circuit board.
P…プリント配線板 1…接着剤付き絶縁基板 2…め
っきレジスト層 3…導体回路 4…貫通穴 5…部品実装ランド 6…
ソルダーレジスト層 15…第2の導体回路 16…第2のめっきレジスト層
(ソルダーレジスト層)P ... Printed wiring board 1 ... Insulating substrate with adhesive 2 ... Plating resist layer 3 ... Conductor circuit 4 ... Through hole 5 ... Component mounting land 6 ...
Solder resist layer 15: second conductive circuit 16: second plating resist layer (solder resist layer)
Claims (2)
(4)を穿孔し、めっきレジスト層(2)を形成し、粗
面化処理後に無電解銅めっきにより導体回路(3)を形
成するアディティブ法プリント配線板の製造方法におい
て、前記めっきレジスト層(2)と導体回路(3)の上
に第2のめっきレジスト層(16)と第2の導体回路
(15)とを形成することを特徴とするアディティブ法
プリント配線板の製造方法。1. A through hole (4) is formed in an insulating substrate (1) with an adhesive, a plating resist layer (2) is formed, and a conductive circuit (3) is formed by electroless copper plating after a surface roughening treatment. Forming a second plating resist layer (16) and a second conductor circuit (15) on the plating resist layer (2) and the conductor circuit (3). A method for manufacturing an additive method printed wiring board, comprising:
5)にスルーホール部と部品実装ランド(5)のみを形
成することを特徴とするアディティブ法プリント配線板
の製造方法。2. The circuit according to claim 1, wherein
5) A method of manufacturing an additive-processed printed wiring board, wherein only a through-hole portion and a component mounting land (5) are formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17515397A JPH118465A (en) | 1997-06-17 | 1997-06-17 | Manufacture of printed wiring board through additive method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17515397A JPH118465A (en) | 1997-06-17 | 1997-06-17 | Manufacture of printed wiring board through additive method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH118465A true JPH118465A (en) | 1999-01-12 |
Family
ID=15991204
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17515397A Pending JPH118465A (en) | 1997-06-17 | 1997-06-17 | Manufacture of printed wiring board through additive method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH118465A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106851998A (en) * | 2017-03-22 | 2017-06-13 | 深圳市景旺电子股份有限公司 | A kind of fine and closely woven PCB circuits and preparation method |
CN107734871A (en) * | 2017-09-29 | 2018-02-23 | 深圳市互连微电子材料有限公司 | A kind of production method of FPC |
CN109195323A (en) * | 2018-10-26 | 2019-01-11 | 深圳欣强智创电路板有限公司 | The disconnected cut position of optical module golden finger sets resist ink graphic structure |
-
1997
- 1997-06-17 JP JP17515397A patent/JPH118465A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106851998A (en) * | 2017-03-22 | 2017-06-13 | 深圳市景旺电子股份有限公司 | A kind of fine and closely woven PCB circuits and preparation method |
CN107734871A (en) * | 2017-09-29 | 2018-02-23 | 深圳市互连微电子材料有限公司 | A kind of production method of FPC |
CN109195323A (en) * | 2018-10-26 | 2019-01-11 | 深圳欣强智创电路板有限公司 | The disconnected cut position of optical module golden finger sets resist ink graphic structure |
CN109195323B (en) * | 2018-10-26 | 2024-05-24 | 深圳欣强智创电路板有限公司 | Anti-electroplating ink graph structure at cutting position of optical module golden finger |
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