JPH02119298A - Manufacture of multilayer printed wiring board for mounting semiconductor element - Google Patents
Manufacture of multilayer printed wiring board for mounting semiconductor elementInfo
- Publication number
- JPH02119298A JPH02119298A JP63273637A JP27363788A JPH02119298A JP H02119298 A JPH02119298 A JP H02119298A JP 63273637 A JP63273637 A JP 63273637A JP 27363788 A JP27363788 A JP 27363788A JP H02119298 A JPH02119298 A JP H02119298A
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- resist film
- insulating plate
- wiring board
- laminate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000011889 copper foil Substances 0.000 claims abstract description 32
- 229910052802 copper Inorganic materials 0.000 claims abstract description 7
- 239000010949 copper Substances 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052731 fluorine Inorganic materials 0.000 abstract description 2
- 239000011737 fluorine Substances 0.000 abstract description 2
- 239000007789 gas Substances 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 238000003475 lamination Methods 0.000 abstract 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- -1 then Chemical compound 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003205 fragrance Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子搭載用多層印刷配線板の製造方法に
関し、特に半導体素子を直接搭載するための凹部の形成
工程を含む半導体素子搭載用多層印刷配線板の製造方法
に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer printed wiring board for mounting a semiconductor element, and in particular, a method for manufacturing a multilayer printed wiring board for mounting a semiconductor element, which includes a step of forming a recess for directly mounting a semiconductor element. The present invention relates to a method for manufacturing a printed wiring board.
従来、半導体素子を直接搭載するための印刷配線板とし
て、印刷配線板の表面に半導体素子を装着するための凹
部を設けることが提案されており、次のような製造方法
が見られる。BACKGROUND ART Conventionally, as a printed wiring board for directly mounting a semiconductor element, it has been proposed to provide a recessed portion for mounting a semiconductor element on the surface of the printed wiring board, and the following manufacturing methods are available.
銅箔を両面に有する絶縁板の銅箔を印刷−エッチングし
て回路パターンを形成し、前記絶縁板の表裏両面に複数
のプリプレグ及び片面に銅箔を有する絶縁板あるいは銅
箔を配置し、加熱圧着し積層板を形成し、前記積層板に
貫通孔およびドリルビットを用い凹状の溝を設けた後全
面にパネルめっきを施し、表面の導体を印刷−エッチン
グし、スルーホール及び半導体素子搭載用凹状の溝を含
む導電回路を形成し、半導体素子搭載用多層印刷配線板
を作成する。凹状の溝の底部は絶縁板あるいは内層グラ
ンド層とする2つの方法がある。Printing and etching the copper foil of an insulating plate having copper foil on both sides to form a circuit pattern, placing a plurality of prepregs on both sides of the insulating plate and an insulating plate or copper foil having copper foil on one side, and heating. A laminated plate is formed by pressure bonding, and after forming through holes and concave grooves in the laminated plate using a drill bit, panel plating is applied to the entire surface, conductors on the surface are printed and etched, and through holes and concave grooves for mounting semiconductor elements are formed. A conductive circuit including grooves is formed to create a multilayer printed wiring board for mounting semiconductor elements. There are two methods of making the bottom of the concave groove an insulating plate or an inner ground layer.
上述した従来の製造方法は、特に、半導体素子搭載用の
凹状の溝の底部が絶縁板である場合は凹状の溝の底部の
めっきの密着性が悪く、半田付時あるいは製造工程中の
加熱工程で凹状の溝の底部のめっきが絶縁板より剥離を
生じるという欠点があった。In the conventional manufacturing method described above, the adhesion of the plating at the bottom of the concave groove is poor, especially when the bottom of the concave groove for mounting the semiconductor element is an insulating plate, and the heating process during soldering or the manufacturing process is difficult. However, there was a drawback in that the plating on the bottom of the concave groove peeled off from the insulating plate.
また、凹状の溝の底部を内装銅箔面とする場合ルータ−
ビットの深さ方向の位置精度が内層銅箔の厚みに比べ悪
いことと、凹状の溝の底部の凹凸が内層銅箔の厚みに比
べ大きいことから、内層銅箔を破壊せずに正確に凹状の
溝を内層銅箔上面が底部となるよう加工することは困難
であるという欠点があった。In addition, if the bottom of the concave groove is the internal copper foil surface, the router
Because the positional accuracy of the bit in the depth direction is poor compared to the thickness of the inner layer copper foil, and the unevenness at the bottom of the concave groove is larger than the thickness of the inner layer copper foil, it is possible to accurately form the concave without destroying the inner layer copper foil. There was a drawback in that it was difficult to process the groove so that the top surface of the inner layer copper foil was at the bottom.
本発明の目的は、凹状の溝のめっきが絶縁板より剥離す
ることがなく、内層銅箔を破壊せずに正確に凹状の溝を
内層銅箔上面が底部となるよう加工できる半導体素子搭
載用多層印刷配線板を提供することにある。An object of the present invention is to provide a semiconductor element mounting device that prevents the plating in the concave groove from peeling off from the insulating plate and allows the concave groove to be precisely processed so that the top surface of the inner layer copper foil becomes the bottom without destroying the inner layer copper foil. An object of the present invention is to provide a multilayer printed wiring board.
本発明の半導体素子搭載用多層印刷配線板の製造方法は
、
(a)表裏両面に銅箔を有する絶縁板の前記銅箔を印刷
−エッチングして回路パターンを形成する工程。The method for manufacturing a multilayer printed wiring board for mounting semiconductor elements according to the present invention includes the following steps: (a) printing and etching the copper foil of an insulating plate having copper foil on both the front and back surfaces to form a circuit pattern.
(b)前記回路パターンの半導体素子搭載部にレジスト
皮膜を形成する工程。(b) forming a resist film on the semiconductor element mounting portion of the circuit pattern;
(c)前記絶縁板の表裏両面に複数のプリプレグ及び片
面に銅箔を有する絶縁板と銅箔とのうちのいずれか一方
を配置し、加熱圧着して積層板を形成する工程。(c) A step of arranging either one of a plurality of prepregs and an insulating plate having a copper foil on one side and a copper foil on both the front and back surfaces of the insulating plate, and bonding them under heat and pressure to form a laminate.
(d)前記積層板に貫通孔を設ける工程。(d) A step of providing through holes in the laminate.
(e)前記積層板の表面より前記レジスト皮膜まで達す
る凹状の溝を形成する工程。(e) forming a concave groove reaching from the surface of the laminate to the resist film;
(f)前記貫通孔のスミア除去を行うと同時に前記凹状
の溝の底部に残存する前記レジスト皮膜を除去し、前記
回路パターンを露出する工程。(f) At the same time as removing the smear from the through hole, the resist film remaining at the bottom of the concave groove is removed to expose the circuit pattern.
(g)前記積層板の全面に銅めっきを施した後、表面の
導体を印刷−エッチングし、スルーホールおよび半導体
素子搭載用凹状の溝を含む導電回路を形成する工程。(g) After applying copper plating to the entire surface of the laminate, a conductor on the surface is printed and etched to form a conductive circuit including through holes and concave grooves for mounting semiconductor elements.
とを含んで構成されている。It is composed of:
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(g)は本発明の第1の実施例を説明す
るための工程順に示した要部断面図である。FIGS. 1(a) to 1(g) are sectional views of main parts shown in the order of steps for explaining the first embodiment of the present invention.
第1の実施例は、まず、第1図(a)に示すように、表
裏両面に銅箔1を加熱圧着した絶縁板2を用意する。銅
箔1としては厚さ35μmの片面を粗化した圧延銅箔を
使用し、絶縁板2にはガラスファイバー繊維により補強
されたエポキシ樹脂を用いた。In the first embodiment, first, as shown in FIG. 1(a), an insulating plate 2 having copper foil 1 bonded under heat and pressure on both the front and back surfaces is prepared. As the copper foil 1, a rolled copper foil having a thickness of 35 μm and roughened on one side was used, and as the insulating plate 2, an epoxy resin reinforced with glass fiber was used.
次いで、第2図(b)に示すように、絶縁板2の表裏両
面に通常の印刷−エッチング法を用い貫通孔形成部の内
層回路とスルーホールとの接続のない部分の銅箔1をエ
ツチング除去し、回路パターン3を形成した。Next, as shown in FIG. 2(b), the copper foil 1 is etched on both the front and back sides of the insulating plate 2 by using a normal printing-etching method to etch the portions of the copper foil 1 where there is no connection between the inner layer circuit of the through-hole forming part and the through-hole. It was removed to form a circuit pattern 3.
次に、第1図(c)に示すように、絶縁板1の表面に光
感光性レジストフィルムをラミネートし、露光、現像す
ることにより、回路パターン3上の凹状の溝形成部にレ
ジスト皮rIA4を形成した。なお現像液には1・1・
1−トリクロロエタンを用いた。Next, as shown in FIG. 1(c), a photosensitive resist film is laminated on the surface of the insulating plate 1, exposed to light, and developed to form a resist film rIA4 in the concave groove forming portion on the circuit pattern 3. was formed. Note that the developer contains 1.1.
1-trichloroethane was used.
次に、第1図(d)に示すように、絶縁板1の両側に複
数のプリプレグ5及び片面を粗化した銅箔6を配し、加
熱圧着することにより積層板7を形成した。Next, as shown in FIG. 1(d), a plurality of prepregs 5 and a copper foil 6 with one side roughened were placed on both sides of the insulating plate 1 and bonded under heat and pressure to form a laminate 7.
次に、第1図(e)に示すように、積層板7の所定の位
置にドリルで穴あけを行ない貫通孔8を形成し、更に、
ドリルビットを用いて、積層板7の表面よりレジスト皮
膜4まで達する凹状の溝9を形成した。Next, as shown in FIG. 1(e), holes are drilled at predetermined positions in the laminate 7 to form through holes 8, and further,
A concave groove 9 reaching from the surface of the laminate 7 to the resist film 4 was formed using a drill bit.
次に、第1図(f)に示すように、積層板7を塩化メチ
レンにスプレー浸漬し、凹状の溝9の底部のレジスト皮
膜4の残金を膨潤除去するか、または、酸素とフッ素の
混合ガスより成るプラズマで20分間処理し、スミア1
0とレジスト残香11を酸化除去した後、積層板7の貫
通孔8の内壁および凹状の溝9の内壁を含む全面に通常
の脱脂、触媒処理、無電解銅めっき及び電気銅めっきを
施し、銅めっき12を形成しな。Next, as shown in FIG. 1(f), the laminate 7 is spray immersed in methylene chloride to swell and remove the remaining resist film 4 at the bottom of the concave groove 9, or a mixture of oxygen and fluorine is added. Treated with plasma consisting of gas for 20 minutes, smear 1
After oxidizing and removing the resist residue 11, the entire surface of the laminated board 7, including the inner walls of the through holes 8 and the inner walls of the concave grooves 9, is subjected to conventional degreasing, catalyst treatment, electroless copper plating, and electrolytic copper plating. Do not form plating 12.
次に、第1図(g)に示すように、積層板7に通常の印
刷−エッチング法により回路形成を施し、スルーホール
13.半導体素子搭載部14及び導電回路15を形成し
、半導体素子搭載用多層印刷配線板20を得た。Next, as shown in FIG. 1(g), a circuit is formed on the laminate 7 by a normal printing-etching method, and the through holes 13. A semiconductor element mounting portion 14 and a conductive circuit 15 were formed to obtain a multilayer printed wiring board 20 for mounting semiconductor elements.
このようにして得られた半導体素子搭載用多層印刷配線
板は、特に、半導体素子搭載用の凹状の溝の底部の銅め
っきの密着が優れ、半田付等の加熱処理によってふくれ
等を生じなかった。また、ドリルビット加工の際に内層
銅箔を損傷することもなく、平坦な底部形状を持つ凹状
の溝を作成することができた。The thus obtained multilayer printed wiring board for mounting semiconductor elements had particularly good adhesion of the copper plating at the bottom of the concave groove for mounting semiconductor elements, and did not bulge during heat treatment such as soldering. . Furthermore, it was possible to create a concave groove with a flat bottom shape without damaging the inner layer copper foil during drilling bit processing.
第2の実施例は、第1図(a)〜(g)に示す第1の実
施例のレジスト皮膜4の形成にアルカリ可溶型の光感光
性レジストフィルムを用い、現像処理を炭酸ナトリウム
水溶液で行なうこと以外は第1の実施例と全く同じ方法
で半導体素子搭載用多層印刷配線板を作成した。In the second embodiment, an alkali-soluble photosensitive resist film was used to form the resist film 4 of the first embodiment shown in FIGS. A multilayer printed wiring board for mounting semiconductor elements was prepared in exactly the same manner as in the first example except for the following steps.
このようにして得られた半導体素子搭載用多層印刷配線
板も第1の実施例と同様に凹状の溝の底部のめっきの密
着性は良好で、半田付等の熱処理によってふくれ等を生
じなく、また、内層銅箔の損傷がなく平坦な底部形状を
持つ凹状の溝を作成することができた。Similarly to the first embodiment, the thus obtained multilayer printed wiring board for mounting semiconductor elements has good adhesion of the plating at the bottom of the concave groove, and does not bulge during heat treatment such as soldering. Furthermore, it was possible to create a concave groove with a flat bottom shape without damaging the inner copper foil.
以上説明したように本発明は、半導体素子搭載用多層印
刷配線板の半導体素子搭載部の凹状の溝を形成する際に
、あらかじめ凹状の溝の底部となる部分にレジスト皮膜
を形成しておくことにより、内層銅箔を損傷することな
く内層銅箔面に接して平坦な底を持つ凹状の溝を形成す
ることができ、搭載する半導体素子の吸湿特性、電磁気
シールド特性及び放熱性等を著しく改善することができ
る効果がある。As explained above, the present invention involves forming a resist film in advance on the bottom portion of the concave groove when forming the concave groove in the semiconductor element mounting portion of a multilayer printed wiring board for mounting semiconductor elements. This makes it possible to form a concave groove with a flat bottom in contact with the inner copper foil surface without damaging the inner copper foil, significantly improving the moisture absorption characteristics, electromagnetic shielding characteristics, heat dissipation characteristics, etc. of the mounted semiconductor element. There is an effect that can be done.
また、ドリルおよびドリルビット加工によるスミアの除
去をプラズマ処理により行なうのと同時にレジスト皮膜
残香の除去も行なうことにより、経済的な製造方法が得
られるという効果もある。Furthermore, by using plasma treatment to remove smear caused by drill and drill bit processing, and at the same time removing residual odor from the resist film, an economical manufacturing method can be obtained.
・・・積層板、8・・・貫通孔、9・・・凹状の溝、1
o川スミア、11・・・レジスト残香、12・・・銅め
っき、13・・・スルーホール、14・・・半導体素子
搭載部、15・・・導電回路、20・・・半導体素子搭
載用多層印刷配線板。...Laminated plate, 8...Through hole, 9...Concave groove, 1
o river smear, 11... Resist residual fragrance, 12... Copper plating, 13... Through hole, 14... Semiconductor element mounting part, 15... Conductive circuit, 20... Multilayer for semiconductor element mounting Printed wiring board.
代理人 弁理士 内 原 晋Agent Patent Attorney Susumu Uchihara
【図面の簡単な説明】
第1図(a)〜(g)は本発明の第1の実施例の製造方
法を説明するための工程順に示した要部断面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a) to 1(g) are sectional views of main parts shown in order of steps for explaining the manufacturing method of the first embodiment of the present invention.
Claims (1)
層印刷配線板の製造方法。 (a)表裏両面に銅箔を有する絶縁板の前記銅箔を印刷
−エッチングして回路パターンを形成する工程。 (b)前記回路パターンの半導体素子搭載部にレジスト
皮膜を形成する工程。 (c)前記絶縁板の表裏両面に複数のプリプレグ及び片
面に銅箔を有する絶縁板と銅箔とのうちのいずれか一方
を配置し、加熱圧着して積層板を形成する工程。 (d)前記積層板に貫通孔を設ける工程。 (e)前記積層板の表面より前記レジスト皮膜まで達す
る凹状の溝を形成する工程。 (f)前記貫通孔のスミア除去を行うと同時に前記凹状
の溝の底部に残存する前記レジスト皮膜を除去し、前記
回路パターンを露出する工程。 (g)前記積層板の全面に銅めっきを施した後、表面の
導体を印刷−エッチングし、スルーホールおよび半導体
素子搭載用凹状の溝を含む導電回路を形成する工程。[Scope of Claims] A method for manufacturing a multilayer printed wiring board for mounting semiconductor elements, comprising the following steps (a) to (g). (a) A step of printing and etching the copper foil of an insulating plate having copper foil on both the front and back surfaces to form a circuit pattern. (b) forming a resist film on the semiconductor element mounting portion of the circuit pattern; (c) A step of arranging either one of a plurality of prepregs and an insulating plate having a copper foil on one side and a copper foil on both the front and back surfaces of the insulating plate, and bonding them under heat and pressure to form a laminate. (d) A step of providing through holes in the laminate. (e) forming a concave groove reaching from the surface of the laminate to the resist film; (f) At the same time as removing the smear from the through hole, the resist film remaining at the bottom of the concave groove is removed to expose the circuit pattern. (g) After applying copper plating to the entire surface of the laminate, a conductor on the surface is printed and etched to form a conductive circuit including through holes and concave grooves for mounting semiconductor elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63273637A JPH0682928B2 (en) | 1988-10-28 | 1988-10-28 | Manufacturing method of multilayer printed wiring board for mounting semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63273637A JPH0682928B2 (en) | 1988-10-28 | 1988-10-28 | Manufacturing method of multilayer printed wiring board for mounting semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02119298A true JPH02119298A (en) | 1990-05-07 |
JPH0682928B2 JPH0682928B2 (en) | 1994-10-19 |
Family
ID=17530470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63273637A Expired - Fee Related JPH0682928B2 (en) | 1988-10-28 | 1988-10-28 | Manufacturing method of multilayer printed wiring board for mounting semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0682928B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0715142A (en) * | 1993-06-22 | 1995-01-17 | Nec Corp | Printed wiring board and its manufacture |
KR100734049B1 (en) * | 2005-11-29 | 2007-06-29 | 주식회사 코리아써키트 | Manufacturing method of cavity typed printed circuit board |
-
1988
- 1988-10-28 JP JP63273637A patent/JPH0682928B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0715142A (en) * | 1993-06-22 | 1995-01-17 | Nec Corp | Printed wiring board and its manufacture |
KR100734049B1 (en) * | 2005-11-29 | 2007-06-29 | 주식회사 코리아써키트 | Manufacturing method of cavity typed printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPH0682928B2 (en) | 1994-10-19 |
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