JP2869616B2 - Manufacturing method of circuit wiring board - Google Patents

Manufacturing method of circuit wiring board

Info

Publication number
JP2869616B2
JP2869616B2 JP27074294A JP27074294A JP2869616B2 JP 2869616 B2 JP2869616 B2 JP 2869616B2 JP 27074294 A JP27074294 A JP 27074294A JP 27074294 A JP27074294 A JP 27074294A JP 2869616 B2 JP2869616 B2 JP 2869616B2
Authority
JP
Japan
Prior art keywords
adhesive layer
insulating adhesive
photosensitive insulating
wiring pattern
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27074294A
Other languages
Japanese (ja)
Other versions
JPH08111590A (en
Inventor
史朗 赤間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON MEKUTORON KK
Original Assignee
NIPPON MEKUTORON KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON MEKUTORON KK filed Critical NIPPON MEKUTORON KK
Priority to JP27074294A priority Critical patent/JP2869616B2/en
Publication of JPH08111590A publication Critical patent/JPH08111590A/en
Application granted granted Critical
Publication of JP2869616B2 publication Critical patent/JP2869616B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は回路配線基板の製造法に
関し、更に具体的に云えば、本発明はドリルやレ−ザ−
加工等によりビアホ−ル等の微細加工をすることなく、
通常の露光・現像処理とエッチング処理によって微細な
配線パタ−ンニングとビアホ−ル接続を形成可能な多層
型の回路配線基板の製造法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a circuit wiring board, and more specifically, the present invention relates to a method for manufacturing a drill or laser.
Without fine processing such as via holes by processing, etc.
The present invention relates to a method of manufacturing a multilayer circuit wiring board capable of forming fine wiring patterns and via-hole connections by ordinary exposure / development processing and etching processing.

【0002】[0002]

【従来技術とその問題点】回路配線基板に使用される絶
縁材料にビアホ−ル等の微細加工を施す為の従来の手法
としては、ドリル加工の他、レ−ザ−加工手段や樹脂エ
ッチング手段等がある。
2. Description of the Related Art Conventional techniques for performing fine processing such as via holes on an insulating material used for a circuit wiring board include drill processing, laser processing means and resin etching means. Etc.

【0003】しかし、ドリル加工では微細な孔や正確な
深さを得ることは困難であり、これに対し、レ−ザ−加
工手段の場合は、設備コストが高く、樹脂性絶縁層の微
細加工に適するように常に最適にレ−ザ−条件を保持す
る為には頻繁にメンテナンスを行う必要があり、また、
レ−ザ−装置のランニングコストも高い他、レ−ザ−加
工部に導電性の炭化物が生じ易いので絶縁特性に問題が
発生する等、量産手法としては多くの問題がある。
[0003] However, it is difficult to obtain a fine hole and an accurate depth by drilling. On the other hand, in the case of a laser processing means, the equipment cost is high and the fine processing of the resinous insulating layer is difficult. Frequent maintenance is required to keep the laser conditions optimal at all times to suit
In addition to the high running cost of the laser device, there are many problems in the mass production method, such as a problem in the insulating characteristics because conductive carbides are easily generated in the laser processed portion.

【0004】また、樹脂エッチング手段の場合は、樹脂
エッチング液には人体に著しく有害な物質が多いので、
作業、保守、管理及び廃液処理等を含めて安定且つ安全
に工程を組む為には相当の設備コストが必要である。
In the case of resin etching means, since the resin etching liquid contains many substances which are extremely harmful to the human body,
Considerable equipment costs are required to stably and safely organize processes including work, maintenance, management, and waste liquid treatment.

【0005】[0005]

【発明の目的及び構成】そこで本発明は、ドリルやレ−
ザ−加工等によりビアホ−ル等の微細加工をすることな
く、通常の露光・現像処理とエッチング処理によって微
細な配線パタ−ンニングとビアホ−ル接続を形成可能な
多層型の回路配線基板の製造法を提供するものである。
SUMMARY OF THE INVENTION Accordingly, the present invention relates to a drill and a laser.
Manufacture of multi-layer circuit wiring board that can form fine wiring pattern and via-hole connection by ordinary exposure / development processing and etching processing without fine processing of via-holes etc. It provides the law.

【0006】その為に本発明の回路配線基板の製造法で
は、絶縁基材の少なくとも一方面に所要の配線パタ−ン
を形成した後、前記配線パタ−ン上に感光性絶縁接着層
を形成し、該感光性絶縁接着層に露光処理を加えてビア
ホ−ルを形成する位置に未露光領域を形成すると共にそ
れ以外の位置に露光領域を形成し、前記未露光領域上に
は導体部が位置しないように前記感光性絶縁接着層上に
他の所要の配線パタ−ンを形成した後、現像処理により
前記感光性絶縁接着層の未露光領域を除去し、次いでキ
ュア−処理を加えて前記感光性絶縁接着層の露光領域を
絶縁層に形成した後、露出した配線パタ−ンと前記他の
配線パタ−ンとにビアホ−ル接続の為の導通層を形成す
る工程を採用したものである。
Therefore, in the method of manufacturing a circuit wiring board according to the present invention, after a required wiring pattern is formed on at least one surface of an insulating base material, a photosensitive insulating adhesive layer is formed on the wiring pattern. Then, the photosensitive insulating adhesive layer is subjected to an exposure treatment to form an unexposed area at a position where a via hole is formed and an exposed area at other positions, and a conductor portion is formed on the unexposed area. After forming another required wiring pattern on the photosensitive insulating adhesive layer so as not to be located, an unexposed area of the photosensitive insulating adhesive layer is removed by a developing process, and then a curing process is applied to the photosensitive insulating adhesive layer. Forming an exposed region of the photosensitive insulating adhesive layer on the insulating layer, and then forming a conductive layer for via hole connection between the exposed wiring pattern and the other wiring pattern. is there.

【0007】[0007]

【実施例】図1の(1)〜(9)は本発明の一実施例に
よる回路配線基板の製造工程図を示す。同図(1)のよ
うに、先ず適当な絶縁基材1の一方面に常法により所要
の配線パタ−ン2,3を形成する。ここで、配線パタ−
ン2,3は絶縁基材1の両面に形成することもできる。
1 (1) to 1 (9) show a manufacturing process diagram of a circuit wiring board according to an embodiment of the present invention. As shown in FIG. 1A, first, required wiring patterns 2 and 3 are formed on one surface of an appropriate insulating base material 1 by an ordinary method. Here, the wiring pattern
The terminals 2 and 3 can also be formed on both surfaces of the insulating base material 1.

【0008】そこで、同図(2)の如く、配線パタ−ン
2,3上に感光性絶縁接着フィルムからなる感光性絶縁
接着層4をラミネ−トして形成し、次いで、この感光性
絶縁接着層4に露光処理を施すことにより、同図(3)
の如く、例えば配線パタ−ン2の部分に後述のビアホ−
ルを形成できるようにその配線パタ−ン2の部分上に未
露光領域4Aを形成すると共にそれ以外の領域に露光領
域4Bを形成する。
Therefore, as shown in FIG. 1B, a photosensitive insulating adhesive layer 4 made of a photosensitive insulating adhesive film is formed on the wiring patterns 2 and 3 by laminating the wiring patterns. By subjecting the adhesive layer 4 to an exposure treatment,
As shown in FIG.
An unexposed area 4A is formed on the portion of the wiring pattern 2 so that a pattern can be formed, and an exposed area 4B is formed in other areas.

【0009】このような露光処理を加えた段階で、未露
光領域4A及び露光領域4Bからなる感光性絶縁接着層
上には、同図(4)のように、導電箔の貼着、スパッタ
リング又はメッキ手段等で導電層5を一様に形成する。
At the stage where such an exposure treatment is applied, a conductive foil is adhered, sputtered or sputtered on the photosensitive insulating adhesive layer composed of the unexposed area 4A and the exposed area 4B as shown in FIG. The conductive layer 5 is formed uniformly by plating means or the like.

【0010】そこで、この導電層5を用いて他の配線パ
タ−ンを形成する為に、この導電層5上に同図(5)の
如く例えばドライフィルムからなるエッチングレジスト
6をラミネ−トして形成し、次いで、このエッチングレ
ジスト6に露光及び現像処理を施すことにより、同図
(6)の如くビアホ−ル形成の為の上記未露光領域4A
と一致した位置に孔6Aを形成して導電層5の一部を露
出させる。
In order to form another wiring pattern using the conductive layer 5, an etching resist 6 made of, for example, a dry film is laminated on the conductive layer 5 as shown in FIG. By exposing and developing the etching resist 6, the unexposed area 4A for forming a via hole is formed as shown in FIG.
A hole 6A is formed at a position coincident with the above, and a part of the conductive layer 5 is exposed.

【0011】次に、同図(7)のように、エッチング処
理工程によって上記孔6Aに露出する導電層5の一部を
エッチング除去して孔7を形成すると共に、他の所要の
配線パタ−ン5Aを形成するものである。このようなエ
ッチング処理後には不要となったエッチングレジスト6
を剥離除去する。
Next, as shown in FIG. 7 (7), a portion of the conductive layer 5 exposed to the hole 6A is removed by etching to form a hole 7 by etching, and other necessary wiring patterns are formed. 5A. The etching resist 6 which becomes unnecessary after such an etching process
Is peeled off.

【0012】ここで、他の所要の配線パタ−ン5Aを導
電性インクで形成する手法の場合には、導電層5を形成
することなく露光処理を施した上記感光性絶縁接着層上
に直ちにその配線パタ−ン5Aを形成できる。
Here, in the case where the other required wiring pattern 5A is formed of conductive ink, the wiring pattern 5A is formed on the photosensitive insulating adhesive layer which has been exposed without forming the conductive layer 5. The wiring pattern 5A can be formed.

【0013】次いで、同図(8)の如く、現像処理に付
して感光性絶縁接着層の未露光領域4Aを除去すること
によりビアホ−ル用の孔7Aを形成して一層目の配線パ
タ−ン2の一部を露出させると共に、キュアリングを施
して感光性絶縁接着層の露光領域4Bを絶縁層4Cに形
成する。
Next, as shown in FIG. 8 (8), the unexposed area 4A of the photosensitive insulating adhesive layer is removed by performing a developing process to form a hole 7A for a via hole to form a first layer wiring pattern. The exposed region 4B of the photosensitive insulating adhesive layer is formed in the insulating layer 4C by exposing a part of the negative electrode 2 and performing curing.

【0014】そこで、ビアホ−ル用の孔7Aに対して無
電解メッキ、電解メッキ又はスパッタリング或いは導電
性インクの付着等の手段でビアホ−ル接続の為の導通層
8を形成することにより、一層目の配線パタ−ン2と二
層目の配線パタ−ン5Aとを微細なビアホ−ルで電気的
に相互接続した多層型の回路配線基板を製作することが
できる。
Therefore, a conductive layer 8 for via hole connection is formed in the via hole hole 7A by means such as electroless plating, electrolytic plating, sputtering, or adhesion of conductive ink. It is possible to manufacture a multilayer circuit wiring board in which the first wiring pattern 2 and the second wiring pattern 5A are electrically interconnected by a fine via hole.

【0015】このような工程で得られたビアホ−ル接続
を有する回路配線基板に対しては、更に前記の工程を採
用することによって他のビアホ−ル接続を備えた配線パ
タ−ンを多層化することが容易であり、また、このよう
な一連の工程は既存の設備を用いて低コストに連続化す
ることも容易である。
With respect to the circuit wiring board having the via hole connection obtained in such a step, the wiring pattern having another via hole connection is multilayered by adopting the above-mentioned step. It is easy to perform such a series of steps at a low cost using existing equipment.

【0016】なお、このようなビアホ−ル接続を有する
多層型の回路配線基板には、常法により配線パタ−ン間
にスル−ホ−ル接続を構成することも勿論可能である。
In the multilayer circuit wiring board having such a via-hole connection, it is of course possible to form a through-hole connection between the wiring patterns by an ordinary method.

【0017】[0017]

【発明の効果】本発明による回路配線基板の製造法で
は、中間の絶縁層を形成する部材として感光性絶縁接着
層を使用するので、一般的な露光・現像処理と導電層に
対するエッチング処理により必要とするビアホールの為
の孔を容易に形成でき、従って、ビアホール接続形成の
為の導通層も簡便に構成できる。このようなビアホール
の為の孔は、二層目の配線パターンを形成した後に形成
するものであるから、二層目の配線パターンは、導電箔
のエッチング、スパッタリング、メッキ又は導電性イン
ク等の手法を用いて形成できるので、この二層目の配線
パターンの形成に大きな自由度がある。
In the method for manufacturing a circuit wiring board according to the present invention, since a photosensitive insulating adhesive layer is used as a member for forming an intermediate insulating layer, it is necessary to perform general exposure / development processing and etching processing for a conductive layer. A hole for the via hole can be easily formed, and thus a conductive layer for forming the via hole connection can be easily formed. Such a via hole
Holes after forming the second layer wiring pattern
The wiring pattern of the second layer is made of conductive foil
Etching, sputtering, plating or conductive
This second layer wiring
There is great freedom in pattern formation.

【0018】本発明の手法を繰り返すことにより、構成
部材間の接着層を低減しながらビアホ−ル接続を有する
微細な配線パタ−ンの薄型多層化も容易であり、また、
工程の連続化も低コストに達成できる。
By repeating the method of the present invention, it is easy to make a fine wiring pattern having a via hole connection into a thin multi-layer while reducing the adhesive layer between the constituent members.
Continuation of the process can also be achieved at low cost.

【0019】従って、マルチチップモジュ−ルの如きI
Cベアチップ等を搭載可能な高機能回路基板の製造手法
として有利である。
Therefore, the I-type module such as a multi-chip module
This is advantageous as a method for manufacturing a high-performance circuit board on which a C bare chip or the like can be mounted.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 (1)〜(9)は本発明の一実施例による回
路配線基板の製造工程図。
FIGS. 1 (1) to 1 (9) are manufacturing process diagrams of a circuit wiring board according to an embodiment of the present invention.

【符号の説明】 1 絶縁基材 2 配線パタ−ン 3 配線パタ−ン 4 感光性絶縁接着層 4C 絶縁層 5 導電層 5A 他の配線パタ−ン 6 エッチングレジスト 7 孔 8 ビアホ−ル接続の為の導通層[Description of Signs] 1 Insulating base material 2 Wiring pattern 3 Wiring pattern 4 Photosensitive insulating adhesive layer 4C Insulating layer 5 Conductive layer 5A Other wiring pattern 6 Etching resist 7 Hole 8 For via hole connection Conductive layer

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁基材の少なくとも一方面に所要の配
線パターンを形成した後、前記配線パターン上に感光性
絶縁接着層を形成し、該感光性絶縁接着層に露光処理を
加えてビアホールを形成する位置に未露光領域を形成す
ると共にそれ以外の位置に露光領域を形成し、前記未露
光領域上には導体部が位置しないように前記感光性絶縁
接着層上に他の所要の配線パターンを形成した後、現像
処理により前記感光性絶縁接着層の未露光領域を除去
し、次いでキュアー処理を加えて前記感光性絶縁接着層
の露光領域を絶縁層に形成した後、露出した配線パター
ンと前記他の配線パターンとにビアホール接続の為の導
通層を形成する工程を含む回路配線基板の製造法。
After a required wiring pattern is formed on at least one surface of an insulating base material, a photosensitive insulating adhesive layer is formed on the wiring pattern, and the photosensitive insulating adhesive layer is exposed to light to form a via hole. An unexposed area is formed at the position where the pattern is to be formed, and an exposed area is formed at other positions. Other necessary wiring patterns are formed on the photosensitive insulating adhesive layer so that the conductor is not located on the unexposed area. After forming, the unexposed area of the photosensitive insulating adhesive layer is removed by a development treatment, and then a cured treatment is applied to form the exposed area of the photosensitive insulating adhesive layer on the insulating layer. A method for manufacturing a circuit wiring board, comprising a step of forming a conductive layer for connecting a via hole to the another wiring pattern.
【請求項2】 前記感光性絶縁接着層は感光性絶縁接着
フィルムである請求項1の回路配線基板の製造法。
2. The method according to claim 1, wherein the photosensitive insulating adhesive layer is a photosensitive insulating adhesive film.
JP27074294A 1994-10-07 1994-10-07 Manufacturing method of circuit wiring board Expired - Fee Related JP2869616B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27074294A JP2869616B2 (en) 1994-10-07 1994-10-07 Manufacturing method of circuit wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27074294A JP2869616B2 (en) 1994-10-07 1994-10-07 Manufacturing method of circuit wiring board

Publications (2)

Publication Number Publication Date
JPH08111590A JPH08111590A (en) 1996-04-30
JP2869616B2 true JP2869616B2 (en) 1999-03-10

Family

ID=17490347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27074294A Expired - Fee Related JP2869616B2 (en) 1994-10-07 1994-10-07 Manufacturing method of circuit wiring board

Country Status (1)

Country Link
JP (1) JP2869616B2 (en)

Also Published As

Publication number Publication date
JPH08111590A (en) 1996-04-30

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