JPH05259639A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH05259639A JPH05259639A JP4055133A JP5513392A JPH05259639A JP H05259639 A JPH05259639 A JP H05259639A JP 4055133 A JP4055133 A JP 4055133A JP 5513392 A JP5513392 A JP 5513392A JP H05259639 A JPH05259639 A JP H05259639A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- circuit pattern
- plating layer
- resist
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プリント配線板の製造
方法に係り、特に電子部品の表面実装に適するプリント
配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board suitable for surface mounting electronic parts.
【０００２】[0002]
【従来の技術】回路構成のコンパクト化、回路構成の小
形大容量化などの点から、いわゆるプリント配線板に、
各種の電子部品を搭載・実装して成る実装回路装置が広
く実用に供されている。ところで、この種のプリント配
線板においては、電子部品の搭載・実装密度を上げた
り、あるいは安定した実装の保持などの観点から、電子
部品の搭載実装面が隣接する絶縁領域面と同一平面を形
成していることが望まれる。そして、このような要望に
対応したプリント配線板は、次のような手段で製造され
ている。第１の手段（方法）は、主面に接着剤層を設け
た積層板を用意し、この積層板の所定位置に所要のスル
ホールを穿設した後、逆回路パターンの永久メッキレジ
ストパターンを被着・形成してから、たとえば化学銅メ
ッキ処理など、いわゆるフルアディティブ法によって所
要の回路パターンを形成する。第２の手段（方法）は、
主面が平滑なたとえばステンレス板面に、感光性ドライ
フィルムを張り合わせ、選択的な露光・現像処理を施
し、逆回路パターンの画像を形成する。次いで、前記ス
テンレス板を一方の電極として電気銅メッキ処理を施
し、所要の回路パターンを形成してから感光性ドライフ
ィルムを剥離し、その後積層型配線板を製造するに当っ
ての、積層する工程でプリプレグ層面などに、ステンレ
ス板面から回路パターンを転写するいわゆる転写法によ
って形成している。2. Description of the Related Art From the point of view of downsizing of circuit structure, downsizing and large capacity of circuit structure, so-called printed wiring board is required.
Mounted circuit devices that are mounted and mounted with various electronic components are widely put to practical use. By the way, in this type of printed wiring board, the mounting surface of electronic parts is flush with the adjacent insulating area surface from the viewpoints of increasing the mounting and mounting density of electronic parts, and maintaining stable mounting. It is hoped that A printed wiring board that meets such a demand is manufactured by the following means. The first means (method) is to prepare a laminated plate having an adhesive layer on its main surface, form a required through hole at a predetermined position of this laminated plate, and then coat a permanent plating resist pattern of an inverse circuit pattern. After depositing and forming, a required circuit pattern is formed by a so-called full additive method such as chemical copper plating. The second means (method) is
A photosensitive dry film is attached to a stainless steel plate surface having a smooth main surface, and selective exposure / development processing is performed to form an image of a reverse circuit pattern. Next, a step of laminating, in which a copper electroplating treatment is performed using the stainless steel plate as one electrode to form a required circuit pattern, the photosensitive dry film is peeled off, and then a laminated wiring board is manufactured. Then, the circuit pattern is formed on the surface of the prepreg layer or the like by a so-called transfer method in which the circuit pattern is transferred from the stainless plate surface.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、前記プ
リント配線板の製造方法においては、実用上次のような
不都合な問題ある。すなわち、第１の手段の場合は、永
久メッキレジストパターンの現像や永久メッキレジスト
パターン層の剥離工程などにおいて、塩素系有機溶媒の
使用を要するため、安全衛生面の点で問題があるばかり
でなく、回路パターンをフルアディティブ法で形成する
際、所要の厚付けを行うのにメッキ液の管理が困難であ
ること、さらにメッキ処理に比較的長時間（通常10時間
以上）を要することなどの問題がある。また、第２の手
段の場合は、最外層の回路パターンを形成するとき有効
であるが、内層回路パターンも転写形成する場合に工程
が繁雑化するばかりでなく、連続的な製造工程を採るこ
とも困難となる上、積層後のスルホール接続に当たっ
て、穿設したスルホール内壁面に再度メッキ処理を施
し、所要のメッキ層を形成（パートリアディティブ法）
する必要があって量産的といえない。However, the above-mentioned method of manufacturing a printed wiring board has the following practical problems. That is, in the case of the first means, it is necessary to use a chlorine-based organic solvent in the step of developing the permanent plating resist pattern, the step of removing the permanent plating resist pattern layer, and the like, so that not only is there a problem in terms of safety and hygiene. When forming a circuit pattern by the full-additive method, it is difficult to control the plating solution to achieve the required thickness, and the plating process requires a relatively long time (usually 10 hours or more). There is. Further, the second means is effective when forming the circuit pattern of the outermost layer, but not only the process becomes complicated when the inner layer circuit pattern is also transferred and formed, but also a continuous manufacturing process is adopted. In addition, it is difficult to connect the through holes after lamination, and the inner wall surface of the through holes that have been drilled is plated again to form the required plating layer (partial additive method).
It cannot be said to be mass-produced because it needs to be done.
【０００４】本発明は上記事情に対処してなされたもの
で、比較的簡略化された量産的な工程でありながら、高
精度な微細パターンの形成が可能で、狭ピッチ・多ピン
の表面実装型の電子部品を高密度に、かつ安定した状態
に搭載・実装が可能なプリント配線板を容易，量産的に
製造し得る製造方法の提供を目的とする。The present invention has been made in consideration of the above circumstances, and it is possible to form a highly precise fine pattern even though it is a relatively simplified mass-production process, and a narrow pitch, multi-pin surface mounting is carried out. An object of the present invention is to provide a manufacturing method capable of easily and mass-produced a printed wiring board capable of mounting / mounting die-shaped electronic components in a high density and in a stable state.
【０００５】[0005]
【課題を解決するための手段】本発明に係るプリント配
線板の製造方法は、剥離性および平滑性良好な導電性支
持基体主面に感光性樹脂層を形成し、この感光性樹脂層
を選択露光・現像して逆回路パターンのメッキレジスト
パターン層を形成する工程と、前記メッキレジストパタ
ーン層を形成した導電性支持基体を一方の電極側とし、
その露出主面上に電気銅メッキ処理を施し所定の回路パ
ターンを形成する工程と、 前記メッキレジストマスク
を除去し、再度感光性樹脂層を塗布形成し選択露光・現
像した後、少なくとも化学銅メッキ処理を施して銅メッ
キ層を形成する工程と、前記銅メッキ層形成面上に剥離
性レジスト層を張り合わせ選択露光・現像して逆回路パ
ターンを形成する工程と、前記剥離性レジスト層から成
る逆回路パターンを形成した後、少なくとも電気メッキ
層および半田メッキ層を順次形成する工程と、前記剥離
性レジストパターンを剥離除去し、半田メッキ層をエッ
チングレジスト層として露出する前記少なくとも化学銅
メッキ処理により形成した銅メッキ層を選択的にエッチ
ング除去して所要の回路パターン層を形成してから半田
メッキ層を除去する工程と、前記回路パターン層形成面
上に感光性樹脂層の形成，選択・露光による逆回路パタ
ーンの形成した後、少くとも化学銅メッキ層の形成，剥
離性レジストパターンの形成，電気メッキ層の順次形
成，剥離性レジストパターンの剥離除去，半田メッキ層
をエッチングレジスト層とした少くとも化学銅メッキ層
の選択的なエッチング除去による所要の回路パターン層
形成および半田メッキ層の除去を繰り返す工程と、前記
回路パターンの積層形成体を導電性支持基体面から剥離
する工程とを具備して成ることを特徴とする。According to the method for producing a printed wiring board of the present invention, a photosensitive resin layer is formed on the main surface of a conductive supporting substrate having good releasability and smoothness, and this photosensitive resin layer is selected. Exposing and developing to form a plating resist pattern layer having a reverse circuit pattern, and the conductive support substrate having the plating resist pattern layer formed on one electrode side,
A step of forming a predetermined circuit pattern by performing electrolytic copper plating on the exposed main surface, and removing the plating resist mask, applying a photosensitive resin layer again, selectively exposing and developing, and then at least chemical copper plating A treatment to form a copper plating layer; a step of laminating a peelable resist layer on the copper plating layer forming surface to selectively expose and develop it to form a reverse circuit pattern; and a reverse step consisting of the peelable resist layer. After the circuit pattern is formed, at least an electroplating layer and a solder plating layer are sequentially formed, and the peelable resist pattern is peeled and removed, and the solder plating layer is exposed as an etching resist layer by at least the chemical copper plating process. Selectively etch away the copper plating layer formed to form the required circuit pattern layer and then remove the solder plating layer Steps: forming a photosensitive resin layer on the surface on which the circuit pattern layer is formed, forming a reverse circuit pattern by selection / exposure, and then forming at least a chemical copper plating layer, forming a peelable resist pattern, and forming an electroplating layer. A step of sequentially forming, peeling and removing the peelable resist pattern, selectively forming a circuit pattern layer and removing the solder plating layer by selectively etching and removing at least the chemical copper plating layer using the solder plating layer as an etching resist layer, And a step of peeling the laminated body of the circuit pattern from the surface of the conductive support substrate.
【０００６】[0006]
【作用】本発明に係るプリント配線板の製造方法は、い
わゆるビルドアップ法の特長を活かしたもので、前記工
程の繰り返しなど連続的な作業によって多層型で、かつ
表面の実装パッドなどが、これら実装パッドなどを絶縁
離隔する絶縁層と同一面を成すように構成されたプリン
ト配線板の製造が可能となる。つまり、化学銅メッキお
よび電気銅メッキ、前記メッキ処理時のメッキレジスト
の使い分けなどによって、所要の回路パターンが高精度
に、多層的に設けられるとともに、少なくとも一主面に
おいては回路パターンを含めほぼ同一平面を成している
プリント配線板を容易に得ることができる。The method for manufacturing a printed wiring board according to the present invention makes use of the features of the so-called build-up method. It is possible to manufacture a printed wiring board configured so as to be flush with an insulating layer that isolates and mounts a mounting pad and the like. In other words, the required circuit patterns are provided in multiple layers with high accuracy by using chemical copper plating, electrolytic copper plating, and proper use of plating resists during the plating process, and at least on one main surface, the circuit patterns are substantially the same. A printed wiring board having a flat surface can be easily obtained.
【０００７】[0007]
【実施例】以下、本発明の実施態様を模式的に示す図１
〜図７の断面図を参照して実施例を説明する。EXAMPLE FIG. 1 schematically shows an embodiment of the present invention.
-Examples will be described with reference to the sectional views of FIGS.
【０００８】先ず、剥離性および平滑性良好な導電性支
持基体、たとえばステンレス板１を用意し（図１）、こ
のステンレス板１の主面に感光性ドライフイルムをラミ
ネートし感光性樹脂層を形成した。その後、前記感光性
樹脂層に選択・露光，現像処理を施して、逆回路パター
ンにメッキレジストパターン２を形成する（図２）。次
いで、前記メッキレジストパターン２を形成した導電性
支持基体１を一方の電極とし、たとえば硫酸銅メッキ液
を用いて電気銅メッキ処理を施し、前記導電性支持基体
１の露出面に電気銅メッキ層を被着し、所要の回路パタ
ーン３を形成した後（図３）、前記メッキレジストパタ
ーン2aを剥離・除去する。その後、再度、感光性樹脂、
たとえばプロビマー（商品名，チバガイギ社製）を塗布
・乾燥し、この感光性樹脂層に選択・露光，現像処理を
施して、逆回路パターンにメッキレジストパターン４を
形成する（図４）。次いで、前面に化学銅メッキ処理を
施した後、さらに要すれば電気銅メッキ処理を施して厚
さ10μm 程度のメッキ層５を形成する。なお、この段階
で要すれば、化学銅メッキ処理に先立って、メッキ層５
形成面を、たとえば過マンガン酸プロセスにより粗面化
しておくことが好ましく、さらに前記メッキ層５は、電
気銅メッキ処理での電極としての機能を呈する程度に厚
く形成し得れば、電気銅メッキ処理は不要となり、微細
なパターンニングの点からその方が望ましい。First, a conductive support substrate having good peelability and smoothness, for example, a stainless steel plate 1 is prepared (FIG. 1), and a photosensitive dry film is laminated on the main surface of the stainless steel plate 1 to form a photosensitive resin layer. did. After that, the photosensitive resin layer is subjected to selection / exposure and development to form a plating resist pattern 2 on the reverse circuit pattern (FIG. 2). Then, the electroconductive support substrate 1 on which the plating resist pattern 2 is formed is used as one electrode, and an electrocopper plating process is performed using, for example, a copper sulfate plating solution to form an electrocopper plated layer on the exposed surface of the electroconductive support substrate 1. After forming a desired circuit pattern 3 (FIG. 3), the plating resist pattern 2a is peeled off and removed. Then, again, the photosensitive resin,
For example, Probimer (trade name, manufactured by Ciba-Geigy Co., Ltd.) is applied and dried, and the photosensitive resin layer is subjected to selection, exposure and development to form a plating resist pattern 4 in the reverse circuit pattern (FIG. 4). Then, the front surface is subjected to chemical copper plating, and if necessary, electrolytic copper plating is performed to form a plating layer 5 having a thickness of about 10 μm. If necessary at this stage, prior to the chemical copper plating treatment, the plating layer 5
The forming surface is preferably roughened by, for example, a permanganate process, and further, the plating layer 5 may be formed thick enough to function as an electrode in the electrolytic copper plating treatment. No treatment is required, and this is preferable from the viewpoint of fine patterning.
【０００９】次に、前記銅メッキ層５を形成した面上に
剥離性の感光性ドライフィルムをラミネートし、選択・
露光，現像処理を施して剥離性レジストパターン６を形
成する。その後、前記に準じた手法で、たとえば硫酸銅
メッキ液を用い剥離性レジストパターン６を形成した露
出面上に、厚さ15μm 程度の電気銅メッキ層７を被着・
形成する。このとき、要すれば下地として化学銅メッキ
層を形成してもよい。しかる後、前記電気銅メッキ層７
上に、厚さ 5μm 程度の半田メッキ層８を被着・形成す
る（図６）。Next, a releasable photosensitive dry film is laminated on the surface on which the copper plating layer 5 is formed, and a selection /
Exposure and development are performed to form a peelable resist pattern 6. Then, by a method similar to that described above, an electrolytic copper plating layer 7 having a thickness of about 15 μm is deposited on the exposed surface on which the peelable resist pattern 6 is formed by using, for example, a copper sulfate plating solution.
Form. At this time, if necessary, a chemical copper plating layer may be formed as a base. After that, the electrolytic copper plating layer 7
A solder plating layer 8 having a thickness of about 5 μm is deposited and formed on the top (FIG. 6).
【００１０】次に、前記剥離性レジストパターン６を剥
離除去し、半田メッキ層８をエッチングレジスト層とし
て、露出する化学銅メッキ層５などを選択的にエッチン
グ除去し、所要の回路パターンを形成してから（図
７）、たとえば硝酸−ホウフッ酸−過酸化水素混合液を
用いて、半田メッキ層８を剥離除去する。そして、これ
らの工程、すなわち前記回路パターン形成面上に、前記
に準じて感光性樹脂層の形成，選択・露光による逆回路
パターンのメッキレジストパターン４の形成、露出面上
に少くとも化学銅メッキ層５の形成，剥離性レジストパ
ターン６の形成，電気銅メッキ層７および半田メッキ層
８の順次形成，剥離性レジストパターン４の剥離除去，
半田メッキ層８をエッチングレジストとした化学メッキ
層５などの選択的なエッチング除去、および半田メッキ
層の除去（図８）の工程を繰り返す。このようにして、
目的とする多層的に回路パターンを形成してから、要す
れば前記最外層に形成された回路パターンと同一平面を
成すように絶縁層を被着・形成した後、前記導電性支持
基体１面に積層形成した多層配線層を、導電性支持基体
１面から剥離することにより、所望の多層型プリント配
線板を製造し得る（図９）。この実施例で、導電性支持
基体１の両主面に多層配線層を積層形成した場合は、一
度に２枚のプリント配線板が得られる。Next, the peelable resist pattern 6 is peeled and removed, and the exposed chemical copper plating layer 5 and the like are selectively etched and removed by using the solder plating layer 8 as an etching resist layer to form a required circuit pattern. After that (FIG. 7), the solder plating layer 8 is peeled and removed by using, for example, a nitric acid-borofluoric acid-hydrogen peroxide mixed solution. Then, in these steps, that is, on the surface on which the circuit pattern is formed, the photosensitive resin layer is formed in accordance with the above, the plating resist pattern 4 of the reverse circuit pattern is formed by selection and exposure, and at least the chemical copper plating is performed on the exposed surface. Layer 5 formation, peelable resist pattern 6 formation, electrolytic copper plating layer 7 and solder plating layer 8 formation in sequence, peeling resist pattern 4 peeling removal,
The steps of selective etching removal of the chemical plating layer 5 using the solder plating layer 8 as an etching resist and removal of the solder plating layer (FIG. 8) are repeated. In this way
After forming a desired multilayer circuit pattern, if necessary, an insulating layer is deposited and formed so as to be flush with the circuit pattern formed on the outermost layer, and then the conductive support substrate 1 surface The desired multilayer printed wiring board can be manufactured by peeling off the multilayer wiring layer formed by laminating from the surface of the conductive support substrate 1 (FIG. 9). In this embodiment, when a multilayer wiring layer is formed on both main surfaces of the conductive support substrate 1, two printed wiring boards can be obtained at one time.
【００１１】そして、前記で得られたプリント配線板の
一主面においては、接続パッドを含む回路パターンおよ
びこの回路パターンを形成する各素パターン間を絶縁す
る絶縁層が同一平面を成しているため、電子部品を容易
に，かつ安定的に搭載・実装し得るとともに、回路パタ
ーンの密度および電子部品の搭載・実装密度の向上を成
し得た。Then, on one main surface of the printed wiring board obtained above, the circuit pattern including the connection pad and the insulating layer for insulating between the element patterns forming the circuit pattern are coplanar. Therefore, electronic parts can be mounted and mounted easily and stably, and the density of circuit patterns and the mounting and mounting density of electronic parts can be improved.
【００１２】なお、上記実施例では、剥離性および平滑
性良好な導電性支持基体として、ステンレス板を用いた
が、良好な導電性，剥離性および平滑性（主面）を有す
るものであれば、他の金属板などに代替し得ることは勿
論であり、また、前記多層配線層を積層形成も、常に導
電性支持基体の一主面のみに行う必要はなく、両主面を
利用して行ってもよい。In the above examples, a stainless steel plate was used as the conductive support substrate having good peelability and smoothness, but any material having good conductivity, peelability and smoothness (main surface) can be used. Of course, other metal plates can be substituted, and the multilayer wiring layers do not always have to be formed on only one main surface of the conductive support base, and both main surfaces can be used. You can go.
【００１３】[0013]
【発明の効果】以上説明したように本発明に係るプリン
ト配線板の製造方法によれば、化学銅メッキ，電気銅メ
ッキによる回路パターン形成使い分けおよびパターン形
成工程の短縮化、前記メッキ処理時のメッキレジストの
絶縁層として残存させる場合と剥離除去する場合との使
い分けなどにより、比較的簡略な操作や設備で所要の回
路パターンが多層的に設けられるとともに、少なくとも
一主面においては回路パターンを含めほぼ同一平面を成
しているプリント配線板を容易に得ることができる。す
なわち、比較的簡単な操作（作業）や設備の利用によっ
て、配線密度などが高く、また所要の電子部品を比較的
高密度に表面実装可能な、そして実装回路装置を構成し
たときも高い信頼性を呈するプリント配線板を得ること
ができる。As described above, according to the method for manufacturing a printed wiring board according to the present invention, the circuit pattern formation is selectively used by chemical copper plating or electrolytic copper plating, the pattern forming process is shortened, and the plating during the plating treatment is performed. The required circuit pattern is provided in multiple layers by relatively simple operation and equipment, depending on whether it is left as the insulating layer of the resist or removed by peeling, and at least on one main surface, the circuit pattern including the circuit pattern is almost A printed wiring board having the same plane can be easily obtained. In other words, the wiring density is high due to the relatively simple operation (work) and the use of equipment, the required electronic parts can be surface-mounted at a relatively high density, and the reliability is high when the mounting circuit device is configured. It is possible to obtain a printed wiring board exhibiting
【図１】本発明に係るプリント配線板の製造方法におい
て用いる導電性支持基体の断面図。FIG. 1 is a cross-sectional view of a conductive support base used in a method for manufacturing a printed wiring board according to the present invention.
【図２】本発明に係るプリント配線板の製造方法におい
て導電性支持基体面に逆回路パターン（絶縁層）を形成
した状態を模式的に示す断面図。FIG. 2 is a cross-sectional view schematically showing a state in which an inverse circuit pattern (insulating layer) is formed on the surface of a conductive support substrate in the method for manufacturing a printed wiring board according to the present invention.
【図３】本発明に係るプリント配線板の製造方法におい
て第１の回路パターンを成す電気銅メッキ層を形成した
状態を示す断面図。FIG. 3 is a cross-sectional view showing a state in which an electrolytic copper plating layer forming a first circuit pattern is formed in the method for manufacturing a printed wiring board according to the present invention.
【図４】本発明に係るプリント配線板の製造方法におい
てメッキレジスト膜を形成した状態を示す断面図。FIG. 4 is a cross-sectional view showing a state in which a plating resist film is formed in the method for manufacturing a printed wiring board according to the present invention.
【図５】本発明に係るプリント配線板の製造方法におい
て化学銅メッキ層を形成した状態を示す断面図。FIG. 5 is a cross-sectional view showing a state in which a chemical copper plating layer is formed in the method for manufacturing a printed wiring board according to the present invention.
【図６】本発明に係るプリント配線板の製造方法におい
て剥離性のメッキレジストを介して電気銅メッキ層およ
び半田メッキ層を形成した状態を示す断面図。FIG. 6 is a cross-sectional view showing a state in which an electrolytic copper plating layer and a solder plating layer are formed via a peelable plating resist in the method for manufacturing a printed wiring board according to the present invention.
【図７】本発明に係るプリント配線板の製造方法におい
て半田メッキ層をエッチングレジスト膜として化学銅メ
ッキ層などを除去した状態を示す断面図。FIG. 7 is a cross-sectional view showing a state in which a chemical copper plating layer and the like are removed using a solder plating layer as an etching resist film in the method for manufacturing a printed wiring board according to the present invention.
【図８】本発明に係るプリント配線板の製造方法におい
て半田メッキ層をエッチングレジスト膜として３層目の
回路パターンを形成した状態を示す断面図。FIG. 8 is a cross-sectional view showing a state in which a circuit pattern of the third layer is formed using the solder plating layer as an etching resist film in the method for manufacturing a printed wiring board according to the present invention.
【図９】本発明に係るプリント配線板の製造方法におい
て製造したプリント配線板の構造例を示す断面図。FIG. 9 is a cross-sectional view showing a structural example of a printed wiring board manufactured by the method for manufacturing a printed wiring board according to the present invention.
１…導電性支持基体 ２…剥離性の逆回路パターン
（メッキレジスト） ３…電気銅メッキ層 ４…逆回路パターン（メッキレ
ジスト） ５…化学銅メッキ層 ６…剥離性の逆回
路パターン（メッキレジスト） ７…化学銅−電気銅
メッキ層 ８…半田メッキ層DESCRIPTION OF SYMBOLS 1 ... Conductive support base 2 ... Peeling reverse circuit pattern (plating resist) 3 ... Electrolytic copper plating layer 4 ... Reverse circuit pattern (plating resist) 5 ... Chemical copper plating layer 6 ... Peeling reverse circuit pattern (plating resist) ) 7 ... Chemical copper-electrolytic copper plating layer 8 ... Solder plating layer
Claims (1)
体主面に感光性樹脂層を形成し、この感光性樹脂層を選
択露光・現像して逆回路パターンのメッキレジストパタ
ーン層を形成する工程と、 前記メッキレジストパターン層を形成した導電性支持基
体を一方の電極側とし、その露出主面上に電気銅メッキ
処理を施し所定の回路パターンを形成する工程と、 前
記メッキレジストマスクを除去し、再度感光性樹脂層を
塗布形成し選択露光・現像した後、少なくとも化学銅メ
ッキ処理を施して銅メッキ層を形成する工程と、 前記銅メッキ層形成面上に剥離性レジスト層を張り合わ
せ選択露光・現像して逆回路パターンを形成する工程
と、 前記剥離性レジスト層から成る逆回路パターンを形成し
た後、少なくとも電気メッキ層および半田メッキ層を順
次形成する工程と、 前記剥離性レジストパターンを剥離除去し、半田メッキ
層をエッチングレジスト層として露出する前記少なくと
も化学銅メッキ処理を施して形成した銅メッキ層を選択
的にエッチング除去して所要の回路パターン層を形成し
てから半田メッキ層を除去する工程と、 前記回路パターン層形成面上に感光性樹脂層の形成，選
択・露光による逆回路パターンの形成した後、少くとも
化学銅メッキ層の形成，剥離性レジストパターンの形
成，電気メッキ層の順次形成，剥離性レジストパターン
の剥離除去，半田メッキ層をエッチングレジスト層とし
た少くとも化学銅メッキ層の選択的なエッチング除去に
よる所要の回路パターン層形成および半田メッキ層の除
去を繰り返す工程と、 前記回路パターンの積層形成体を導電性支持基体面から
剥離する工程とを具備して成ることを特徴とするプリン
ト配線板の製造方法。1. A photosensitive resin layer is formed on the main surface of a conductive supporting substrate having good peelability and smoothness, and the photosensitive resin layer is selectively exposed and developed to form a plating resist pattern layer having a reverse circuit pattern. A step of forming a predetermined circuit pattern by performing electrolytic copper plating on the exposed main surface of the conductive support substrate having the plating resist pattern layer formed on one electrode side, and removing the plating resist mask And then again forming a photosensitive resin layer, selectively exposing and developing, and then performing at least chemical copper plating to form a copper plating layer; and selecting a releasable resist layer by laminating on the copper plating layer forming surface. Exposing and developing to form a reverse circuit pattern, and after forming the reverse circuit pattern composed of the peelable resist layer, at least an electroplating layer and a solder plating layer A step of sequentially forming, the peelable resist pattern is peeled and removed, and the copper plating layer formed by performing at least the chemical copper plating treatment exposing the solder plating layer as an etching resist layer is selectively removed by etching. After forming the circuit pattern layer, removing the solder plating layer, forming a photosensitive resin layer on the circuit pattern layer forming surface, forming a reverse circuit pattern by selection / exposure, and then at least a chemical copper plating layer. Circuit, the formation of a peelable resist pattern, the sequential formation of an electroplating layer, the peeling removal of the peelable resist pattern, and the selective etching removal of at least the chemical copper plating layer using the solder plating layer as an etching resist layer. The step of repeating the pattern layer formation and the removal of the solder plating layer, and the conductive support of the laminated body of the circuit pattern. A method for manufacturing a printed wiring board, comprising the step of peeling from a substrate surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4055133A JPH05259639A (en) | 1992-03-13 | 1992-03-13 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4055133A JPH05259639A (en) | 1992-03-13 | 1992-03-13 | Manufacture of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05259639A true JPH05259639A (en) | 1993-10-08 |
Family
ID=12990287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4055133A Withdrawn JPH05259639A (en) | 1992-03-13 | 1992-03-13 | Manufacture of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05259639A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088536A (en) * | 1994-06-16 | 1996-01-12 | Sony Corp | Manufacture of multilayer printed wiring board |
| US6418615B1 (en) | 1999-03-11 | 2002-07-16 | Shinko Electronics Industries, Co., Ltd. | Method of making multilayered substrate for semiconductor device |
| JP2003142624A (en) * | 2001-10-31 | 2003-05-16 | Fujitsu Ltd | Method for manufacturing semiconductor device incorporating passive element, relay substrate and manufacturing method therefor |
| US6861757B2 (en) | 2001-09-03 | 2005-03-01 | Nec Corporation | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
| JP2007109802A (en) * | 2005-10-12 | 2007-04-26 | Nec Corp | Wiring board, semiconductor device employing same and method of manufacturing same |
| JP2009188022A (en) * | 2008-02-04 | 2009-08-20 | Shinko Electric Ind Co Ltd | Method for manufacturing wiring board |
| US8039756B2 (en) | 2005-10-12 | 2011-10-18 | Nec Corporation | Multilayered wiring board, semiconductor device in which multilayered wiring board is used, and method for manufacturing the same |
| JP2012182504A (en) * | 2012-06-25 | 2012-09-20 | Shinko Electric Ind Co Ltd | Wiring board |
| JP2022070566A (en) * | 2020-10-27 | 2022-05-13 | アオイ電子株式会社 | Method of manufacturing circuit board, circuit board, laminate substrate, and support substrate |
-
1992
- 1992-03-13 JP JP4055133A patent/JPH05259639A/en not_active Withdrawn
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088536A (en) * | 1994-06-16 | 1996-01-12 | Sony Corp | Manufacture of multilayer printed wiring board |
| US7763809B2 (en) | 1999-03-11 | 2010-07-27 | Shink Electric Industries Co., Inc. | Multilayered substrate for semiconductor device and method of manufacturing same |
| US6418615B1 (en) | 1999-03-11 | 2002-07-16 | Shinko Electronics Industries, Co., Ltd. | Method of making multilayered substrate for semiconductor device |
| US6441314B2 (en) | 1999-03-11 | 2002-08-27 | Shinko Electric Industries Co., Inc. | Multilayered substrate for semiconductor device |
| US6931724B2 (en) | 1999-03-11 | 2005-08-23 | Shinko Electric Industries Co., Ltd. | Insulated multilayered substrate having connecting leads for mounting a semiconductor element thereon |
| US6861757B2 (en) | 2001-09-03 | 2005-03-01 | Nec Corporation | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
| JP2003142624A (en) * | 2001-10-31 | 2003-05-16 | Fujitsu Ltd | Method for manufacturing semiconductor device incorporating passive element, relay substrate and manufacturing method therefor |
| US6875638B2 (en) | 2001-10-31 | 2005-04-05 | Fujitsu Limited | Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board |
| US6995044B2 (en) | 2001-10-31 | 2006-02-07 | Fujitsu Limited | Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board |
| JP2007109802A (en) * | 2005-10-12 | 2007-04-26 | Nec Corp | Wiring board, semiconductor device employing same and method of manufacturing same |
| US7791186B2 (en) | 2005-10-12 | 2010-09-07 | Nec Corporation | Wiring board, semiconductor device in which wiring board is used, and method for manufacturing the same |
| US7880295B2 (en) | 2005-10-12 | 2011-02-01 | Nec Corporation | Wiring board, semiconductor device in which wiring board is used, and method for manufacturing the same |
| US8039756B2 (en) | 2005-10-12 | 2011-10-18 | Nec Corporation | Multilayered wiring board, semiconductor device in which multilayered wiring board is used, and method for manufacturing the same |
| JP2009188022A (en) * | 2008-02-04 | 2009-08-20 | Shinko Electric Ind Co Ltd | Method for manufacturing wiring board |
| JP2012182504A (en) * | 2012-06-25 | 2012-09-20 | Shinko Electric Ind Co Ltd | Wiring board |
| JP2022070566A (en) * | 2020-10-27 | 2022-05-13 | アオイ電子株式会社 | Method of manufacturing circuit board, circuit board, laminate substrate, and support substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4897338A (en) | Method for the manufacture of multilayer printed circuit boards | |
| JP3786554B2 (en) | Circuit board manufacturing method for forming fine structure layer on both sides of flexible film | |
| US4915983A (en) | Multilayer circuit board fabrication process | |
| US5218761A (en) | Process for manufacturing printed wiring boards | |
| JP2000294903A (en) | Manufacture of printed wiring board | |
| KR100642167B1 (en) | Method for producing multi-layer circuits | |
| JPH05259639A (en) | Manufacture of printed wiring board | |
| EP0337986B1 (en) | Multilayer circuit board fabrication process | |
| JPH08107263A (en) | Manufacturing method of printed-wiring board | |
| JPH06268355A (en) | Printed wiring board and manufacture thereof | |
| KR20060066971A (en) | Manufacturing method for double side flexible printed circuit board | |
| US4994349A (en) | Printed wiring board fabrication method | |
| JPH06252529A (en) | Manufacture of printed wiring board | |
| JP3648753B2 (en) | Wiring board manufacturing method | |
| JPH03225894A (en) | Manufacture of printed wiring board | |
| JP2622848B2 (en) | Manufacturing method of printed wiring board | |
| JPH0548246A (en) | Manufacture of flexible printed circuit board | |
| JPS62156898A (en) | Manufacture of through-hole printed wiring board | |
| JP3817291B2 (en) | Printed wiring board | |
| JPH05259609A (en) | Manufacture of printed wiring board | |
| JPH0567871A (en) | Printed-wiring board and manufacture thereof | |
| JPS60208895A (en) | Method of producing printed circuit board | |
| JPH02119298A (en) | Manufacture of multilayer printed wiring board for mounting semiconductor element | |
| JPS63185092A (en) | Manufacture of printed circuit board | |
| JPH0582932A (en) | Printed wiring board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |