JPH06252529A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH06252529A
JPH06252529A JP4079993A JP4079993A JPH06252529A JP H06252529 A JPH06252529 A JP H06252529A JP 4079993 A JP4079993 A JP 4079993A JP 4079993 A JP4079993 A JP 4079993A JP H06252529 A JPH06252529 A JP H06252529A
Authority
JP
Japan
Prior art keywords
photosensitive layer
resist pattern
conductive film
forming
coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4079993A
Other languages
Japanese (ja)
Inventor
Takaaki Hiroto
卓見 廣戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4079993A priority Critical patent/JPH06252529A/en
Publication of JPH06252529A publication Critical patent/JPH06252529A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To cope with high density of an electronic equipment by forming in thin-line the copper circuit pattern of a printed wiring board in a square shape without side etching. CONSTITUTION:A first conductive covering 1 is formed on an insulation substrate with double-sided copper foil and then a first sensitized layer 3 is applied to it. Active rays are applied to the first sensitized layer 3 and then exposure and development are made for forming a resist pattern in reverse printing according to the first sensitized layer 3, a second conductive film 4 is formed on a first conductive film 2 at a part which is not covered with the resist pattern, and then the resist pattern according to the first sensitized layer 3 is peeled off. Then, a second sensitized layer 5 is coated on the first and second conductive films 2 and 4 and the resist pattern is formed in normal printing by exposure and development so that only the second conductive film 4 can be covered, and then the second sensitized layer 5 is peeled off by etching, thus forming a copper circuit pattern 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプリント配線板の製造方
法に関し、特にエッチングレジストの形状を改良したプ
リント配線板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board having an improved etching resist shape.

【0002】[0002]

【従来の技術】近年、電子機器の高密度化が進展し、プ
リント配線板においても回路パターンの細線化が要求さ
れている。従来、プリント配線板の製造方法としては、
テンティング法あるいはパターンめっき法がその代表例
として知られている。テンティング法は、まず、図3
(a)に示すように、両面に9〜12μmの厚みの銅箔
付き絶縁基板1に第1の導電性被膜2を形成した後、図
3(b)に示すように、第1の導電性被膜2上に、さら
に第2の導電性被膜4を形成する。次いで、図3(c)
に示すように、第2の導電性被膜4上に感光層7として
膜厚が50μmの感光性フィルムあるいは膜厚10〜2
0μmの電着レジストを全面に形成する。次いで、図3
(d)に示すように、活性光線を照射して露光,現像を
行い感光層7のレジストパターンを形成する。次いで、
図3(e)に示すように、塩化第2銅エッチング溶液や
塩化第2鉄エッチング溶液にてレジストパターンに被覆
されていない部分をエッチングして銅回路パターン6を
得る。最後に、図3(f)および(g)に示すように、
感光層7のレジストパターンを剥離して第1の導電性被
膜2と第2の導電性被膜4によって構成される銅回路パ
ターン6を有するプリント配線板を得る。
2. Description of the Related Art In recent years, as the density of electronic devices has increased, printed circuit boards are required to have finer circuit patterns. Conventionally, as a method of manufacturing a printed wiring board,
A tenting method or a pattern plating method is known as a representative example. The tenting method is as shown in FIG.
As shown in FIG. 3A, after forming the first conductive coating film 2 on the insulating substrate 1 with a copper foil having a thickness of 9 to 12 μm on both surfaces, as shown in FIG. A second conductive coating 4 is further formed on the coating 2. Then, FIG. 3 (c)
As shown in FIG. 5, a photosensitive film having a film thickness of 50 μm or a film thickness of 10 to 2 is formed as the photosensitive layer 7 on the second conductive film 4.
A 0 μm electrodeposition resist is formed on the entire surface. Then, FIG.
As shown in (d), the resist pattern of the photosensitive layer 7 is formed by irradiating with actinic rays for exposure and development. Then
As shown in FIG. 3E, the copper circuit pattern 6 is obtained by etching a portion not covered by the resist pattern with a cupric chloride etching solution or a ferric chloride etching solution. Finally, as shown in FIGS. 3 (f) and (g),
The resist pattern of the photosensitive layer 7 is peeled off to obtain a printed wiring board having a copper circuit pattern 6 composed of the first conductive coating 2 and the second conductive coating 4.

【0003】また、パターンめっき法は、まず、図4
(a)に示すように、両面に9〜12μmの厚みの銅箔
付き絶縁基板1に第1の導電性被膜2を形成した後、図
4(b)に示すように、第1の導電性被膜2上に膜厚5
0μmの感光性フィルムを被覆し感光層7のパターンを
形成した後、活性光線を照射して露光,現像を行い逆版
の感光層7のレジストパターンを形成する。次に、図4
(c)に示すように、感光層7のレジストパターンで被
覆されていない第1の導電性被膜2上に第2の導電性被
膜4を形成した後、図4(d)に示すように、さらに第
2の導電性被膜4上にエッチングレジストとしてはんだ
による保護金属膜8を形成する。次いで、図4(e)に
示すように、感光層7を剥離した後、図4(f)に示す
ように、塩化第2銅エッチング溶液等にて露出した第1
の導電性被膜2をエッチングして除去する。最後に、図
4(g)および(h)に示すように、保護金属膜8を剥
離して第1の導電性被膜2と第2の導電性被膜4によっ
て構成される銅回路パターン6を有するプリント配線板
を得る。
In the pattern plating method, first, as shown in FIG.
As shown in (a), after forming the first conductive coating film 2 on the insulating substrate 1 with a copper foil having a thickness of 9 to 12 μm on both sides, as shown in FIG. Film thickness 5 on coating 2
After forming a pattern of the photosensitive layer 7 by coating a photosensitive film of 0 μm, it is exposed to actinic rays and exposed and developed to form a resist pattern of the photosensitive layer 7 of the reverse plate. Next, FIG.
As shown in FIG. 4C, after forming the second conductive film 4 on the first conductive film 2 which is not covered with the resist pattern of the photosensitive layer 7, as shown in FIG. Further, a protective metal film 8 made of solder is formed as an etching resist on the second conductive film 4. Next, as shown in FIG. 4 (e), after the photosensitive layer 7 is peeled off, as shown in FIG. 4 (f), the first exposed layer is exposed with a cupric chloride etching solution or the like.
The conductive coating 2 is removed by etching. Finally, as shown in FIGS. 4G and 4H, the protective metal film 8 is peeled off to have a copper circuit pattern 6 composed of the first conductive film 2 and the second conductive film 4. Get the printed wiring board.

【0004】以上説明した従来のテンティング法とパタ
ーンめっき法では、図3(g)および図4(h)に示す
ように、片側のサイドエッチング量が約15μmにも達
し、回路パターンの細線化の障害となっていた。
In the conventional tenting method and pattern plating method described above, as shown in FIGS. 3 (g) and 4 (h), the side etching amount on one side reaches about 15 μm, and the circuit pattern is thinned. Had been an obstacle.

【0005】[0005]

【発明が解決しようとする課題】このテンティング法あ
るいはパターンめっき法による従来のプリント配線板の
製造方法では、回路パターンのサイドエッチング量が大
きく、そのため回路パターンの細線化が困難で電子機器
の高密度化に対応できないという問題点があった。
According to the conventional method for manufacturing a printed wiring board by the tenting method or the pattern plating method, the side etching amount of the circuit pattern is large, so that it is difficult to make the circuit pattern thin and the electronic device is expensive. There is a problem that it cannot cope with the densification.

【0006】本発明の目的は、回路パターンのサイドエ
ッチング量が小さく回路パターンの細線化が可能で、電
子機器の高密度化に対応できるプリント配線板の製造方
法を提供することにある。
It is an object of the present invention to provide a method for manufacturing a printed wiring board which has a small amount of side etching of a circuit pattern, enables the circuit pattern to be thinned, and can cope with high density of electronic equipment.

【0007】[0007]

【課題を解決するための手段】第1の発明のプリント配
線板の製造方法は、両面銅箔付き絶縁基板の所定の位置
に穿孔し第1の導電性被膜を形成する工程と、該第1の
導電性被膜上に第1の感光層を被覆し活性光線を照射し
露光・現像して前記第1の感光層によるレジストパター
ンを逆版形成する工程と、該レジストパターンに被覆さ
れていない部分の前記第1の導電性被膜上に第2の導電
性被膜を形成した後前記レジストパターンを剥離する工
程と、前記第1の導電性被膜と前記第2の導電性被膜上
に第2の感光層を被覆する工程と、露光・現像して前記
第2の導電性被膜のみを覆うように前記第2の感光層に
よるレジストパターンを正版形成する工程と、露出した
前記第1の導電性被膜をエッチングする工程と、前記第
2の感光層によるレジストパターンを剥離し銅回路パタ
ーンを形成する工程とを含む。
A method for manufacturing a printed wiring board according to a first aspect of the present invention comprises a step of forming a first conductive coating by perforating a predetermined position of an insulating substrate with a double-sided copper foil, and the first conductive film. Forming a resist pattern by the first photosensitive layer by reverse printing by coating the first photosensitive layer on the conductive film, irradiating with actinic rays, exposing and developing, and a portion not covered by the resist pattern. Forming a second conductive film on the first conductive film, and then removing the resist pattern; and a second photosensitive film on the first conductive film and the second conductive film. A step of coating a layer, a step of exposing and developing to form a resist pattern of the second photosensitive layer so as to cover only the second conductive film, and a step of exposing the exposed first conductive film. The etching step and the second photosensitive layer Stripping the resist pattern and forming a copper circuit pattern.

【0008】第2の発明のプリント配線板の製造方法
は、両面銅箔付き絶縁基板の所定の位置に穿孔し第1の
導電性被膜を形成する工程と、該第1の導電性被膜上に
第1の感光層を被覆し活性光線を照射し露光・現像して
前記第1の感光層によるレジストパターンを逆版形成す
る工程と、前記レジストパターンに被覆されていない部
分の前記第1の導電性被膜上に第2の導電性被膜を形成
した後該第2の導電性被膜上に第2の感光層を被覆する
工程と、前記第2の感光層のパターンの幅よりも若干太
めに露光・現像して前記第1の感光層と前記第2の感光
層によるレジストパターンを正版形成する工程と、前記
第1の導電性被膜をエッチングする工程と、前記第1の
感光層と前記第2の感光層によるレジストパターンを剥
離し銅回路パターンを形成する工程とを含む。
A method of manufacturing a printed wiring board according to a second aspect of the present invention comprises a step of forming a first conductive coating on a double-sided copper foil-insulated insulating substrate at a predetermined position and forming a first conductive coating on the first conductive coating. A step of forming a resist pattern on the first photosensitive layer by reverse printing by exposing the first photosensitive layer to actinic rays, exposing and developing, and a portion of the first conductive film not covered by the resist pattern. Of forming a second conductive film on the conductive film and then coating the second photosensitive layer on the second conductive film, and exposing to slightly thicker than the width of the pattern of the second photosensitive layer. A step of developing to form a resist pattern by the first photosensitive layer and the second photosensitive layer in an original form; a step of etching the first conductive film; the first photosensitive layer and the second Remove the resist pattern from the photosensitive layer of the copper circuit pattern And forming.

【0009】[0009]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0010】図1(a)〜(h)は本発明の第1の実施
例を説明する工程順に示した断面図、図1(i)は図1
(h)A部の拡大断面図である。第1の実施例は、ま
ず、図1(a)に示すように、両面に厚みが9〜12μ
mの銅箔が付いた絶縁基板1にドリリングにより、直径
0.4mmの穴をあけた後、無電解銅めっきを施し約2
μmの厚みの第1の導電性被膜2を形成する。次いで、
図1(b)に示すように、第1の導電性被膜2上にめっ
きレジストとして膜厚が50μmのドライフィルムの第
1の感光層3をラミネートし、露光,現像を行いパッ
ド,回路パターンを形成する領域以外の部分に第1の感
光層3のパターンを逆版形成する。
1 (a) to 1 (h) are sectional views showing the first embodiment of the present invention in the order of steps, and FIG. 1 (i) is shown in FIG.
(H) It is an expanded sectional view of A part. In the first embodiment, first, as shown in FIG. 1A, the thickness is 9-12 μm on both surfaces.
After making a hole with a diameter of 0.4 mm by drilling on the insulating substrate 1 with m copper foil, electroless copper plating is applied to about 2
A first conductive film 2 having a thickness of μm is formed. Then
As shown in FIG. 1B, a first photosensitive layer 3 of a dry film having a film thickness of 50 μm is laminated as a plating resist on the first conductive film 2 and exposed and developed to form pads and circuit patterns. The pattern of the first photosensitive layer 3 is reverse-printed on a portion other than the region to be formed.

【0011】次いで、図1(c)に示すように、電気銅
めっき液(CuSO4 :85g/l,H2 SO4 :19
0g/l,光沢剤:少量)中に電流密度1.5A/dm
2 にて約1時間浸漬、あるいは無電解銅めっき液(Cu
SO4 :10g/l,37%HCOH:3〜4ml/
l,EDTA,NaOH)中に約10時間浸漬すること
により、第1の感光層3が被覆されていない部分の第1
の導電性被膜2上に第2の導電性被膜4のパターンを約
20μmの厚みで形成する。次いで、図1(d)に示す
ように、第1の感光層3のパターンを塩化メチレンにて
剥離した後、図1(e)に示すように、第1の導電性被
膜2および第2の導電性被膜4上に第2の感光層5とし
て膜厚50μmの感光性ドライフィルムあるいは膜厚1
0〜20μmの電着レジストを真空ラミネートあるいは
電着にて形成する。
Then, as shown in FIG. 1C, electrolytic copper plating solution (CuSO 4 : 85 g / l, H 2 SO 4 : 19)
Current density of 1.5 A / dm in 0 g / l, brightener: small amount)
Immerse in 2 for about 1 hour, or electroless copper plating solution (Cu
SO 4: 10g / l, 37 % HCOH: 3~4ml /
1), EDTA, NaOH) for about 10 hours, so that the first unexposed portion of the first photosensitive layer 3
A pattern of the second conductive coating film 4 is formed on the conductive coating film 2 in a thickness of about 20 μm. Next, as shown in FIG. 1 (d), after the pattern of the first photosensitive layer 3 is peeled off with methylene chloride, as shown in FIG. 1 (e), the first conductive film 2 and the second conductive film 2 are removed. A photosensitive dry film having a film thickness of 50 μm or a film thickness of 1 as the second photosensitive layer 5 on the conductive film 4.
An electrodeposition resist of 0 to 20 μm is formed by vacuum lamination or electrodeposition.

【0012】次いで、図1(f)に示すように、第2の
感光層5を第2の導電性被膜4のパタンの幅よりも若干
太めに露光,現像を行い第2の感光層5をレジストパタ
ーンを正版形成する。次いで、図1(g)に示すよう
に、塩化第2銅のエッチング溶液(Cu2+:80〜14
0g/l,Cu+ :5〜20g/l,Na+ :0〜20
g/l,HCl:50〜100g/l)により、第2の
感光層5に被覆されていない第1の導電性被膜2をエッ
チングした後、図1(h)に示すように、第2の感光層
5を剥離してサイドエッチング量の少ない銅回路パター
ン6を有する第1の実施例によるプリント配線板を得
た。
Next, as shown in FIG. 1F, the second photosensitive layer 5 is exposed and developed so as to be slightly thicker than the width of the pattern of the second conductive film 4 to form the second photosensitive layer 5. A resist pattern is formed in the relief printing. Then, as shown in FIG. 1 (g), an etching solution of cupric chloride (Cu 2+ : 80 to 14
0 g / l, Cu + : 5 to 20 g / l, Na + : 0 to 20
g / l, HCl: 50-100 g / l), after etching the first conductive film 2 not covered by the second photosensitive layer 5, as shown in FIG. The photosensitive layer 5 was peeled off to obtain a printed wiring board according to the first embodiment having a copper circuit pattern 6 with a small amount of side etching.

【0013】このようにして得られたプリント配線板の
銅回路パターン6は、第2の導電性被膜4が第2の感光
層5に被覆されていたので、図1(i)に示すように、
第2の導電性被膜4のサイドエッチングは全くなく、細
線化が可能な矩形の形状であった。
In the copper circuit pattern 6 of the printed wiring board thus obtained, since the second conductive film 4 is covered with the second photosensitive layer 5, as shown in FIG. 1 (i). ,
There was no side etching of the second conductive coating 4, and the shape was a rectangle that could be thinned.

【0014】図2(a)〜(g)は本発明の第2の実施
例を説明する工程順に示した断面図、図2(h)は図2
(g)B部の拡大断面図である。第2の実施例は、ま
ず、図2(a)に示すように、両面に厚みが9〜12μ
mの銅箔が付いた絶縁基板1にドリリングにより、直径
0.4mmの穴をあけた後、無電解銅めっきを施し約2
μmの厚みの第1の導電性被膜2を形成する。次いで、
図2(b)に示すように、第1の導電性被膜2上にめっ
きレジストとして膜厚が50μmの第1の感光層(ポジ
型)3をラミネートし、露光,現像を行いパッド,回路
パターンを形成する領域以外の部分に第1の感光層3の
パターンを逆版形成する。
2 (a) to 2 (g) are sectional views showing a second embodiment of the present invention in the order of steps, and FIG. 2 (h) is shown in FIG.
(G) It is an expanded sectional view of a B part. In the second embodiment, first, as shown in FIG. 2A, the thickness is 9-12 μm on both sides.
After making a hole with a diameter of 0.4 mm by drilling on the insulating substrate 1 with m copper foil, electroless copper plating is applied to about 2
A first conductive film 2 having a thickness of μm is formed. Then
As shown in FIG. 2B, a first photosensitive layer (positive type) 3 having a film thickness of 50 μm is laminated as a plating resist on the first conductive film 2 and exposed and developed to perform pad and circuit patterns. The pattern of the first photosensitive layer 3 is reverse-printed on a portion other than the region for forming.

【0015】次いで、図2(c)に示すように、電気銅
めっき液(CuSO4 :85g/l,H2 SO4 :19
0g/l,光沢剤:少量)中に電気密度1.5A/dm
2 にて約1時間浸漬、あるいは無電解銅めっき液(Cu
SO4 :10g/l,37%HCHO:3〜4ml/
l,EDTA,NaOH)中に約10時間浸漬すること
により、第1の感光層3が被覆されていない部分の第1
の導電性被膜2上に第2の導電性被膜4のパターンを約
20μmの厚みで形成する。次いで、図2(d)に示す
ように、第1の感光層3を除去しないで第2の導電性被
膜4上に第2の感光層(ポジ型)5として膜厚が6〜8
μmの電着レジストを形成する。次いで、図2(e)に
示すように、第2の感光層5のパターンの幅よりも若干
太めに露光,現像を行い第1の感光層と第2の感光層に
よるレジストパターンを正版形成する。
Then, as shown in FIG. 2 (c), an electrolytic copper plating solution (CuSO 4 : 85 g / l, H 2 SO 4 : 19)
Electric density of 1.5 A / dm in 0 g / l, brightener: small amount)
Immerse in 2 for about 1 hour, or electroless copper plating solution (Cu
SO 4: 10g / l, 37 % HCHO: 3~4ml /
1), EDTA, NaOH) for about 10 hours, so that the first unexposed portion of the first photosensitive layer 3
A pattern of the second conductive coating film 4 is formed on the conductive coating film 2 in a thickness of about 20 μm. Next, as shown in FIG. 2D, a film thickness of 6 to 8 is formed as a second photosensitive layer (positive type) 5 on the second conductive film 4 without removing the first photosensitive layer 3.
A μm electrodeposition resist is formed. Then, as shown in FIG. 2E, exposure and development are performed to be slightly thicker than the width of the pattern of the second photosensitive layer 5 to form a resist pattern of the first photosensitive layer and the second photosensitive layer in the relief printing. .

【0016】次いで、図2(f)に示すように、塩化第
2銅エッチング液(Cu2+:80〜140g/l,Cu
+ :5〜20g/l,Na+ :0〜20g/l,HC
l:50〜100g/l)により、第1の感光層(ポジ
型)3,第2の感光層(ポジ型)5に被覆されていない
第1の導電性被膜2をエッチングした後、図2(g)に
示すように、第1の感光層3,第2の感光層5によるレ
ジストパターンを剥離してサイド、エッチング量の少な
い銅回路パターン6を有する第2の実施例によるプリン
ト配線板を得た。
Then, as shown in FIG. 2 (f), a cupric chloride etching solution (Cu 2+ : 80 to 140 g / l, Cu
+ : 5 to 20 g / l, Na + : 0 to 20 g / l, HC
1: 50 to 100 g / l), the first conductive film 2 which is not covered with the first photosensitive layer (positive type) 3 and the second photosensitive layer (positive type) 5 is etched, and then FIG. As shown in (g), the printed wiring board according to the second embodiment having the side and the copper circuit pattern 6 with a small etching amount by peeling off the resist pattern formed by the first photosensitive layer 3 and the second photosensitive layer 5 is formed. Obtained.

【0017】このようにして得られたプリント配線板の
銅回路パターン6は、第2の導電性被膜4が第1の感光
層3,第2の感光層5に被覆されていたので、図2
(h)に示すように、第1の実施例の同回路パターンと
同様に第2の導電性被膜4のサイドエッチングは全くな
く、細線化が可能な矩形の形状であった。
In the copper circuit pattern 6 of the printed wiring board thus obtained, the second conductive film 4 was covered with the first photosensitive layer 3 and the second photosensitive layer 5, so that FIG.
As shown in (h), there was no side etching of the second conductive film 4 like the same circuit pattern of the first embodiment, and it was a rectangular shape capable of thinning.

【0018】[0018]

【発明の効果】以上説明したように本発明は、銅回路パ
ターン形成時のエッチングレジストを銅回路パターンと
なる導電性被膜の側にも被覆することにより、銅回路パ
ターンのサイドエッチング量をなくし矩形に近い形状に
形成できるので細線化が可能となり、電子機器の高密度
化に対応できるという効果がある。
As described above, the present invention eliminates the side etching amount of the copper circuit pattern by coating the etching resist for forming the copper circuit pattern also on the side of the conductive film which becomes the copper circuit pattern. Since it can be formed in a shape close to, it has an effect that it can be made finer and can cope with higher density of electronic devices.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(h)は本発明の第1の実施例を説明
する工程順に示した断面図、図1(i)は図1(h)A
部の拡大断面図である。
1A to 1H are cross-sectional views showing the first embodiment of the present invention in the order of steps for explaining the first embodiment of the present invention, and FIG.
It is an expanded sectional view of a part.

【図2】(a)〜(g)は本発明の第2の実施例を説明
する工程順に示した断面図、図2(h)は図2(g)B
部の拡大断面図である。
2 (a) to 2 (g) are sectional views showing the second embodiment of the present invention in the order of steps, and FIG. 2 (h) is FIG. 2 (g) B.
It is an expanded sectional view of a part.

【図3】(a)〜(f)は従来のプリント配線板の製造
方法の一例を説明する工程順に示した断面図、図3
(g)は図3(f)C部の拡大断面図である。
3 (a) to 3 (f) are cross-sectional views showing the order of steps for explaining an example of a conventional method for manufacturing a printed wiring board;
FIG. 3G is an enlarged cross-sectional view of the C portion in FIG.

【図4】(a)〜(g)は従来のプリント配線板の製造
方法の他の例を説明する工程順に示した断面図、図4
(h)は図4(g)D部の拡大断面図である。
4A to 4G are cross-sectional views showing another example of the conventional method for manufacturing a printed wiring board in the order of steps,
FIG. 4H is an enlarged cross-sectional view of the D part in FIG.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 第1の導電性被膜 3 第1の感光層 4 第2の導電性被膜 5 第2の感光層 6 銅回路パターン 7 感光層 8 保護金属膜 1 Insulating Substrate 2 First Conductive Film 3 First Photosensitive Layer 4 Second Conductive Film 5 Second Photosensitive Layer 6 Copper Circuit Pattern 7 Photosensitive Layer 8 Protective Metal Film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 両面銅箔付き絶縁基板の所定の位置に穿
孔し第1の導電性被膜を形成する工程と、該第1の導電
性被膜上に第1の感光層を被覆し活性光線を照射し露光
・現像して前記第1の感光層によるレジストパターンを
逆版形成する工程と、該レジストパターンに被覆されて
いない部分の前記第1の導電性被膜上に第2の導電性被
膜を形成した後前記レジストパターンを剥離する工程
と、前記第1の導電性被膜と前記第2の導電性被膜上に
第2の感光層を被覆する工程と、露光・現像して前記第
2の導電性被膜のみを覆うように前記第2の感光層によ
るレジストパターンを正版形成する工程と、露出した前
記第1の導電性被膜をエッチングする工程と、前記第2
の感光層によるレジストパターンを剥離し銅回路パター
ンを形成する工程とを含むことを特徴とするプリント配
線板の製造方法。
1. A step of forming a first conductive coating by perforating the insulating substrate with double-sided copper foil at a predetermined position, and coating the first photosensitive layer on the first conductive coating with an actinic ray. A step of irradiating, exposing and developing to form a resist pattern by the first photosensitive layer in a reverse plate; and forming a second conductive film on the first conductive film in a portion not covered by the resist pattern. After forming, the step of peeling off the resist pattern, the step of coating a second photosensitive layer on the first conductive coating and the second conductive coating, and the second conductive coating by exposing and developing. Forming a resist pattern of the second photosensitive layer so as to cover only the conductive coating, etching the exposed first conductive coating, and
And removing the resist pattern formed by the photosensitive layer to form a copper circuit pattern.
【請求項2】 前記第2の導電性被膜上に第2の感光層
を被覆する工程が真空中にてラミネートする工程を含む
ことを特徴とする請求項1記載のプリント配線板の製造
方法。
2. The method for manufacturing a printed wiring board according to claim 1, wherein the step of coating the second photosensitive layer on the second conductive film includes a step of laminating in a vacuum.
【請求項3】 両面銅箔付き絶縁基板の所定の位置に穿
孔し第1の導電性被膜を形成する工程と、該第1の導電
性被膜上に第1の感光層を被覆し活性光線を照射し露光
・現像して前記第1の感光層によるレジストパターンを
逆版形成する工程と、前記レジストパターンに被覆され
ていない部分の前記第1の導電性被膜上に第2の導電性
被膜を形成した後該第2の導電性被膜上に第2の感光層
を被覆する工程と、前記第2の感光層のパターンの幅よ
りも若干太めに露光・現像して前記第1の感光層と前記
第2の感光層によるレジストパターンを正版形成する工
程と、前記第1の導電性被膜をエッチングする工程と、
前記第1の感光層と前記第2の感光層によるレジストパ
ターンを剥離し銅回路パターンを形成する工程とを含む
ことを特徴とするプリント配線板の製造方法。
3. A step of forming a first conductive coating by perforating the insulating substrate with double-sided copper foil at a predetermined position, and coating the first photosensitive layer on the first conductive coating with an actinic ray. A step of irradiating, exposing and developing to form a resist pattern by the first photosensitive layer in a reverse plate, and forming a second conductive film on the first conductive film in a portion not covered by the resist pattern. After the formation, a step of coating the second photosensitive layer with a second photosensitive layer, and a step of exposing and developing a layer slightly thicker than the width of the pattern of the second photosensitive layer to form the first photosensitive layer. A step of forming a resist pattern by the second photosensitive layer in an original form; a step of etching the first conductive film;
A method of manufacturing a printed wiring board, comprising the steps of peeling a resist pattern formed by the first photosensitive layer and the second photosensitive layer to form a copper circuit pattern.
【請求項4】 前記第1および第2の感光層が光分解型
の感光層であることを特徴とする請求項3記載のプリン
ト配線板の製造方法。
4. The method for manufacturing a printed wiring board according to claim 3, wherein the first and second photosensitive layers are photodegradable photosensitive layers.
JP4079993A 1993-03-02 1993-03-02 Manufacture of printed wiring board Pending JPH06252529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4079993A JPH06252529A (en) 1993-03-02 1993-03-02 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4079993A JPH06252529A (en) 1993-03-02 1993-03-02 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPH06252529A true JPH06252529A (en) 1994-09-09

Family

ID=12590682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4079993A Pending JPH06252529A (en) 1993-03-02 1993-03-02 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPH06252529A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030075825A (en) * 2002-03-21 2003-09-26 주식회사 심텍 The fabrication method of printed circuit board for semiconductor package having tailless pattern
JP2007150366A (en) * 2002-03-01 2007-06-14 Hitachi Chem Co Ltd Printed wiring board
JP2015532010A (en) * 2012-09-07 2015-11-05 アール アンド ディー サーキッツインコーポレイテッドR & D Circuits Inc. Method and structure for forming conductive pads on a printed circuit board using zero undercut technology
JP2020202343A (en) * 2019-06-13 2020-12-17 凸版印刷株式会社 Wiring board and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54109171A (en) * 1978-02-16 1979-08-27 Nippon Electric Co Method of producing printed circuit board
JPS54120866A (en) * 1978-03-10 1979-09-19 Anritsu Electric Co Ltd Method of producing through hole printed board
JPS5750489A (en) * 1980-09-11 1982-03-24 Nippon Electric Co Method of producing hybrid circuit board
JPH02105596A (en) * 1988-10-14 1990-04-18 Toyama Nippon Denki Kk Manufacture of printed wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54109171A (en) * 1978-02-16 1979-08-27 Nippon Electric Co Method of producing printed circuit board
JPS54120866A (en) * 1978-03-10 1979-09-19 Anritsu Electric Co Ltd Method of producing through hole printed board
JPS5750489A (en) * 1980-09-11 1982-03-24 Nippon Electric Co Method of producing hybrid circuit board
JPH02105596A (en) * 1988-10-14 1990-04-18 Toyama Nippon Denki Kk Manufacture of printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150366A (en) * 2002-03-01 2007-06-14 Hitachi Chem Co Ltd Printed wiring board
JP4555998B2 (en) * 2002-03-01 2010-10-06 日立化成工業株式会社 Printed wiring board
KR20030075825A (en) * 2002-03-21 2003-09-26 주식회사 심텍 The fabrication method of printed circuit board for semiconductor package having tailless pattern
JP2015532010A (en) * 2012-09-07 2015-11-05 アール アンド ディー サーキッツインコーポレイテッドR & D Circuits Inc. Method and structure for forming conductive pads on a printed circuit board using zero undercut technology
JP2020202343A (en) * 2019-06-13 2020-12-17 凸版印刷株式会社 Wiring board and method for manufacturing the same

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