JP3130707B2 - Printed circuit board and method of manufacturing the same - Google Patents

Printed circuit board and method of manufacturing the same

Info

Publication number
JP3130707B2
JP3130707B2 JP05197085A JP19708593A JP3130707B2 JP 3130707 B2 JP3130707 B2 JP 3130707B2 JP 05197085 A JP05197085 A JP 05197085A JP 19708593 A JP19708593 A JP 19708593A JP 3130707 B2 JP3130707 B2 JP 3130707B2
Authority
JP
Japan
Prior art keywords
solder
plating
copper
electroless
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP05197085A
Other languages
Japanese (ja)
Other versions
JPH0750470A (en
Inventor
修作 和泉
繁 藤田
明仁 川上
徹 鈴木
譲二 土谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP05197085A priority Critical patent/JP3130707B2/en
Publication of JPH0750470A publication Critical patent/JPH0750470A/en
Application granted granted Critical
Publication of JP3130707B2 publication Critical patent/JP3130707B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、プリント基板およびそ
の製造方法に係り、特に貫通孔内を含む基板表面のはん
だ接続部分を無電解はんだめっきで被覆したプリント基
板およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a method for manufacturing the same, and more particularly, to a printed circuit board in which solder connection portions on the surface of a substrate including through holes are coated with electroless solder plating and a method for manufacturing the same.

【0002】[0002]

【従来の技術】プリント基板に電子部品端子をはんだ接
続する際に、種々の方法でプリント基板のはんだ接続部
分にはんだを供給するが、その一つに予めプリント基板
のはんだ接続部分に電気メッキ、もしくは無電解めっき
ではんだめっきする方法が知られている。
2. Description of the Related Art When soldering electronic component terminals to a printed circuit board, the solder is supplied to the soldered parts of the printed circuit board by various methods. Alternatively, a method of performing solder plating by electroless plating is known.

【0003】その中でも無電解はんだめっき処理する方
法は、電気めっきや、溶融はんだ浴槽内に基板を浸漬し
て引上げ、余分なはんだを吹きとばして基板にはんだ合
金膜を形成するソルダーコーティング法(はんだコー
ト、はんだレベラー等とも称される)等よりも均一な膜
が形成できる優れた方法であるとして、下記に例示する
ように従来から幾つかの方法が提案されている。
[0003] Among them, the electroless solder plating method is a method of electroplating or a solder coating method (a solder coating method of dipping a substrate in a molten solder bath, pulling it up, and blowing off excess solder to form a solder alloy film on the substrate). Some methods have been conventionally proposed as an excellent method capable of forming a more uniform film than a method such as a coat, a solder leveler, etc.).

【0004】(1)その一つに、無電解はんだめっき
と、ソルダーコーティング法とを組み合わせた製造方法
がある。配線回路形成後のプリント基板表面を溶融はん
だを接触させて(ソルダーコーティング法)基板上の銅
導体回路表面に、はんだ合金膜を形成し、貫通孔内およ
びその開口部のランドを除き銅導体回路上を含む基板全
面にソルダーレジストを形成してこれをマスクとして無
電解はんだめっきを施し、貫通孔内壁に選択的に無電解
はんだめっきするというものである。
(1) One of them is a manufacturing method in which electroless solder plating is combined with a solder coating method. The printed circuit board surface after the formation of the wiring circuit is brought into contact with molten solder (solder coating method) to form a solder alloy film on the surface of the copper conductor circuit on the board, and the copper conductor circuit is removed except for the land in the through hole and its opening. In this method, a solder resist is formed on the entire surface of the substrate including the upper portion, electroless solder plating is performed using the solder resist as a mask, and electroless solder plating is selectively performed on the inner wall of the through hole.

【0005】(2)また、上記(1)と類似の方法とし
て、貫通孔内および基板上の銅導体回路表面に銅めっき
した後、それらの上に無電解はんだめっきし、さらに基
板上の無電解はんだめっきされた銅導体回路表面に溶融
はんだを接触させて(ソルダーコーティング法)、銅導
体回路上に厚いはんだ層を形成するというものである。
(2) As a method similar to the above (1), copper plating is performed on the inside of the through hole and on the surface of the copper conductor circuit on the substrate, and then electroless solder plating is performed on them, and then the copper plating is performed on the substrate. The molten solder is brought into contact with the surface of the copper conductor circuit plated with electrolytic solder (solder coating method) to form a thick solder layer on the copper conductor circuit.

【0006】(3)この製造方法は、貫通孔内および基
板上の銅導体回路表面に銅めっきした後、それらの上に
無電解はんだめっきし、貫通孔内およびその開口部のラ
ンドを除き銅導体回路上を含む基板全面にソルダーレジ
ストを形成してこれをマスクとして電気はんだめっきを
施し、貫通孔内壁とランドに選択的に電気はんだめっき
を形成するというものである。
(3) In this manufacturing method, after copper plating is performed on a copper conductor circuit surface in a through hole and on a substrate, electroless solder plating is performed thereon, and copper is removed except for lands in the through hole and its opening. In this method, a solder resist is formed on the entire surface of the substrate including the conductor circuit, and the solder resist is used as a mask to perform electric solder plating, and the electric solder plating is selectively formed on the inner wall of the through hole and the land.

【0007】なお、これらの技術に関連するものとし
て、例えば特開昭52−76833号公報、特開昭52
−85368号公報、特開昭64−82692号公報な
どが挙げられる。
As related to these techniques, for example, Japanese Patent Application Laid-Open Nos. Sho 52-76833 and
-85368 and JP-A-64-82692.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、上記
(1)の例は、溶融はんだの接触(ソルダーコーティン
グ)と、無電解はんだめっきとの組合せでプロセスが非
常に煩雑であり、溶融はんだを基板表面の銅導体回路に
接触させてはんだ層を形成するにしても、高さバラツキ
等ではんだが貫通孔内にも容易に浸入し、穴詰まりが生
じて挿入部品の実装が不可能となる場合があり、実用的
でない。また、ソルダーレジストで被覆される基板表面
の銅導体回路上には、はんだ層が形成されているため、
レジスト形成時の硬化熱、および部品搭載時のフローソ
ルダーの加熱等により、下地のはんだ層が溶解し、レジ
ストの剥離が生じ絶縁特性が著しく劣化する。さらにま
た、貫通孔内への無電解はんだめっきは、その成立ちか
ら置換タイプであるため、予めそれを考慮して最初から
厚い銅めっき膜を下地処理として形成せねばならず、そ
のため高密度回路作成には不向きである。この種の従来
技術では回路パターンの加工精度を配線幅でみると高々
100〜120μmであり、これより線幅を狭小化する
ことは不可能であった。
However, in the example of the above (1), the process is very complicated due to the combination of the contact of molten solder (solder coating) and the electroless solder plating, and the molten solder is applied to the substrate surface. Even if a solder layer is formed by contacting the copper conductor circuit, the solder may easily penetrate into the through-holes due to height variations, etc. Yes, not practical. In addition, since a solder layer is formed on the copper conductor circuit on the board surface covered with solder resist,
Due to the curing heat at the time of forming the resist and the heating of the flow solder at the time of mounting the components, the underlying solder layer is dissolved, the resist is peeled off, and the insulating properties are significantly deteriorated. Furthermore, since the electroless solder plating in the through-holes is a replacement type from the time of its establishment, a thick copper plating film must be formed as a base treatment from the beginning in consideration of this in advance, so that high-density circuit creation Not suitable for In this type of conventional technology, the processing accuracy of the circuit pattern is 100 to 120 μm at most in terms of the wiring width, and it is impossible to further reduce the line width.

【0009】また、上記(2)の例も、(1)の場合と
同様に溶融はんだを基板表面の銅導体回路に接触させて
はんだ層を形成する工程を有することから、同様に貫通
孔内の溶融はんだによる穴詰まりの問題があり、貫通孔
内の無電解はんだめっきを考慮した下地銅めっき膜の膜
厚化による高密度回路作成上の問題がある。
Also, the example of the above (2) has a step of forming a solder layer by bringing molten solder into contact with the copper conductor circuit on the substrate surface as in the case of (1). There is a problem of clogging of holes due to molten solder, and there is a problem of making a high-density circuit by increasing the thickness of a base copper plating film in consideration of electroless solder plating in through holes.

【0010】また、(3)の例は、銅めっき、はんだめ
っき共に電気めっきと、無電解めっきとを組み合わせた
もので、プロセスが非常に煩雑となる。この例でも無電
解めっきに先立ち、その下地となる銅めっきには、無電
解銅めっきに引き続き電気銅めっきを施して膜厚を増大
させていることから、上記いずれの例の場合と同様に高
密度回路作成上の問題がある。また、ソルダーレジスト
で被覆される基板表面の銅導体回路上には、無電解はん
だめっき層が形成されているため、上記(1)の場合と
同様に、レジスト形成時の硬化熱、および部品搭載時の
フローソルダーの加熱等により、下地のはんだ層が溶解
し、レジストの剥離が生じ絶縁特性が著しく劣化すると
いう問題がある。
In the case of (3), both copper plating and solder plating are a combination of electroplating and electroless plating, and the process becomes very complicated. Also in this example, prior to electroless plating, the underlying copper plating was subjected to electrolytic copper plating following electroless copper plating to increase the film thickness. There is a problem in creating a density circuit. Further, since the electroless solder plating layer is formed on the copper conductor circuit on the surface of the substrate covered with the solder resist, the curing heat during the formation of the resist and the component mounting are the same as in the above (1). There is a problem in that the underlying solder layer dissolves due to the heating of the flow solder at that time, the resist is peeled off, and the insulating characteristics are significantly deteriorated.

【0011】したがって本発明の目的は、このような従
来技術の問題点を解消することにあり、無電解はんだめ
っきが均一な膜形成に優れているという特徴を最大限に
活かして高密度配線パターンの形成を可能とした改良さ
れたプリント基板およびその製造方法を提供することに
ある。
Accordingly, an object of the present invention is to solve the above-mentioned problems of the prior art, and to make the most of the feature that electroless solder plating is superior in forming a uniform film, to realize a high-density wiring pattern. It is an object of the present invention to provide an improved printed circuit board capable of forming a printed circuit board and a method for manufacturing the same.

【0012】[0012]

【課題を解決するための手段】上記目的は、内面が銅め
っき上に無電解はんだめっきされた貫通孔と、その開口
部周縁の銅箔上に銅めっきおよび前記銅めっき層の一
部を残しその表層部を無電解はんだめっきにより置換め
っきした無電解はんだめっき層を有するランドと、基板
表面の銅箔が選択エッチングによりパターン化された回
路部と、前記銅箔回路部上を含むはんだ接続領域外の基
板表面を密着被覆したソルダーレジストとを有して成る
プリント基板により、達成される。無電解はんだめっき
の厚みは0.5μm〜10μmとすることが望ましい。
ソルダーレジストで被覆された基板上の回路部は、薄い
銅箔パターンで構成されているため選択エッチングによ
り高精細な配線パターンが形成可能である。上記ソルダ
ーレジストとしては、耐熱性と密着性を考慮しエポキシ
系レジストで構成するのが望ましい。そして、このソル
ダーレジストは、銅箔回路部上を直接被覆しているた
め、レジスト形成時、もしくははんだ接続時に加熱して
もレジスト剥離の問題は生じない。先に説明したよう
に、従来は回路上にはんだ層が介在していたためレジス
ト剥離の問題が生じた。
The object of the present invention is to provide a through-hole whose inner surface is electrolessly solder-plated on copper plating, a copper-plated layer on the copper foil around the opening, and one of the copper-plated layers.
And replace the surface layer with electroless solder plating
A land having a coated electroless solder plating layer, a circuit portion in which copper foil on the substrate surface is patterned by selective etching, and a solder in which the surface of the substrate outside the solder connection region including on the copper foil circuit portion is tightly covered. This is achieved by a printed circuit board having a resist. It is desirable that the thickness of the electroless solder plating be 0.5 μm to 10 μm.
Since the circuit portion on the substrate covered with the solder resist is formed of a thin copper foil pattern, a high-definition wiring pattern can be formed by selective etching. The solder resist is preferably made of an epoxy resist in consideration of heat resistance and adhesion. Since the solder resist directly covers the copper foil circuit portion, the problem of resist peeling does not occur even when heating at the time of forming the resist or at the time of solder connection. As described above, the problem of resist peeling has arisen because a solder layer has conventionally been interposed on a circuit.

【0013】また、上記目的は、両面銅張り基板に貫通
孔を形成する工程と、触媒付与工程を経て、基板表面の
銅箔を所定のレジストマスクを用いて選択エッチングす
ることにより貫通孔の開口部周縁にはランドを、その他
の領域には配線回路パターンを形成する工程と、前記ラ
ンドおよび配線回路パターンが形成された基板表面に、
はんだめっきを必要とする領域を除き、少なくとも配線
回路パターン上を密着被覆してソルダーレジストパター
ンを形成する工程と、前記ソルダーレジストパターンを
マスクとして、前記貫通孔内およびランド上に、後工程
で形成するはんだめっき膜厚に相当する膜厚を超える無
電解銅めっき厚膜を選択的に形成する工程と、前記無電
解銅めっき膜上に無電解はんだめっきを施すことによ
り、前記無電解銅めっき膜の一部を残しその表層部
はんだめっき膜で置換めっきする工程とを有して成る
プリント基板の製造方法によっても、達成される。
The object of the present invention is to form a through-hole in a double-sided copper-clad substrate and a catalyst applying step, and then selectively etch the copper foil on the substrate surface using a predetermined resist mask to form an opening in the through-hole. A step of forming a land on the periphery of the part and a wiring circuit pattern in the other region, and a step of forming a land and a wiring circuit pattern on the substrate surface,
A step of forming a solder resist pattern by tightly covering at least the wiring circuit pattern except for a region requiring solder plating, and a post-process in the through hole and on the land using the solder resist pattern as a mask.
Electroless copper plating thick film and a step of selectively forming, by performing an electroless solder plating on the electroless copper plating film, the electroless copper exceeding the thickness corresponding to the solder plating film thickness of in formation Leave part of the plating film in front of its surface
The present invention is also achieved by a method for manufacturing a printed circuit board having a step of performing displacement plating with the solder plating film.

【0014】さらには、内面が銅めっきされた貫通孔と
表面の銅箔上に銅めっきされた配線パターンとを有する
基板表面に、はんだめっきを必要とする領域を除きソル
ダーレジストパターンを形成する工程と、前記ソルダー
レジストパターンをマスクとして、はんだめっき膜厚に
相当する厚みの無電解銅めっき膜を選択的に形成する工
程と、次いで前記無電解銅めっき膜上に無電解はんだめ
っきを施すことにより、前記選択的に形成された無電解
銅めっき膜をはんだめっき膜で置換する工程とを有して
成るプリント基板の製造方法によっても、達成される。
Further, a step of forming a solder resist pattern on the surface of the substrate having a through hole whose inner surface is plated with copper and a wiring pattern plated with copper on the surface of the copper foil, excluding a region requiring solder plating. And, using the solder resist pattern as a mask, a step of selectively forming an electroless copper plating film having a thickness corresponding to the solder plating film thickness, and then performing electroless solder plating on the electroless copper plating film. And substituting the selectively formed electroless copper plating film with a solder plating film.

【0015】[0015]

【作用】無電解はんだめっきは電気めっきと異なり、独
立した回路にも均一な厚さで析出するため、部品実装に
対して表面凹凸の少ない表面処理が得られる。また、無
電解はんだめっきは、下地の銅を置換しながら進行する
ので、無電解はんだめっきに際しては、はんだめっき時
に溶解される分量の下地銅を事前に無電解銅めっきで析
出させる。さらには、無電解はんだめっき、無電解銅め
っきに際しては、基板上のめっき不要部分をソルダーレ
ジストでマスキングするが、これに使用するソルダーレ
ジストは、これらの両処理液に電食されることのない、
高耐薬品性のソルダーレジストを用いる。エポキシ系レ
ジストは、これらの条件を満足するものである。
[Effect] Unlike electroplating, electroless solder plating is deposited on an independent circuit with a uniform thickness, so that surface treatment with less surface irregularities can be obtained for component mounting. In addition, since the electroless solder plating proceeds while replacing the underlying copper, the amount of the underlying copper dissolved during the solder plating is previously deposited by the electroless copper plating during the electroless solder plating. Furthermore, in the electroless solder plating and the electroless copper plating, the unnecessary portion of the plating on the substrate is masked with a solder resist, but the solder resist used for this is not electrolytically eroded by both of these processing solutions. ,
Use solder resist with high chemical resistance. The epoxy resist satisfies these conditions.

【0016】[0016]

【実施例】以下、図面にしたがって本発明の一実施例を
説明する。 〈実施例1〉 図1は、本発明の一実施例となる製造工程を示したプリ
ント基板の要部断面図である。以下、一般的に行なわれ
ているサブトラクティブ法によるプリント基板の製造方
法に適用し場合を例に工程順に説明する。
An embodiment of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 is a cross-sectional view of a main part of a printed circuit board showing a manufacturing process according to an embodiment of the present invention. Hereinafter, steps in a case where the present invention is applied to a general method of manufacturing a printed circuit board by a subtractive method will be described.

【0017】先ず、図1(a)に示したように、銅張り
積層板(詳しくは絶縁板に銅箔を接着したもの)、もし
くは予め内層回路を積層形成した内層入り銅張り積層板
を基板1として準備し、この基板内の所定位置に、貫通
孔2をドリル、レーザビーム等の周知の穿孔手段により
設ける。
First, as shown in FIG. 1 (a), a copper-clad laminate (specifically, a copper foil bonded to an insulating plate) or a copper-clad laminate with an inner layer preliminarily formed by laminating an inner circuit is used as a substrate. The through hole 2 is provided at a predetermined position in the substrate by a known perforation means such as a drill or a laser beam.

【0018】次いで図1(b)に示したように、貫通孔
2の内壁を含む基板全面に通常用いられているプロセス
にて触媒処理、化学銅めっき処理を施した後、配線導体
として必要最小限の厚みの銅めっき3を電解めっき、も
しくは厚付け無電解銅めっきにて析出形成させる。
Next, as shown in FIG. 1 (b), the entire surface of the substrate including the inner wall of the through hole 2 is subjected to a catalyst treatment and a chemical copper plating treatment by a commonly used process, and then a necessary minimum amount of a wiring conductor is obtained. A copper plating 3 having a minimum thickness is deposited by electrolytic plating or thick electroless copper plating.

【0019】次いで図1(c)に示したように、必要回
路を形成するため、ドライフィルムを用いたテンティン
グ法等により回路となる部分をマスキングし、エッチン
グ工程にて回路以外の不要な銅を溶解除去する。
Next, as shown in FIG. 1C, in order to form a necessary circuit, a portion to be a circuit is masked by a tenting method using a dry film or the like, and unnecessary copper other than the circuit is etched in an etching step. Is dissolved and removed.

【0020】次いで図1(d)に示したように、部品実
装時に必要となる部分(例えば貫通孔内壁およびラン
ド)のみを露出させる形状で、エポキシ系熱硬化樹脂を
成分とする高耐薬品性ソルダーレジスト4をスクリーン
印刷法で形成させる。なお、このソルダーレジスト4の
形成は、写真技術を利用した所謂リソグラフィー技術で
形成することもでき、高密度プリント基板の製造にはむ
しろこの方が望ましい。
Next, as shown in FIG. 1 (d), only a part (for example, an inner wall of the through hole and a land) necessary at the time of component mounting is exposed, and a high chemical resistance containing an epoxy thermosetting resin as a component. The solder resist 4 is formed by a screen printing method. Note that the solder resist 4 can be formed by a so-called lithography technique using a photographic technique, and it is more preferable to manufacture a high-density printed circuit board.

【0021】次いで図1(e)に示したように、銅の露
出している部分にアルカリ、硫酸銅、キレート剤等で構
成されている市販の厚付け無電解銅めっき液にて、必要
とする厚みの銅めっき5を析出させる。この必要とする
厚みの銅めっきとは、この後の無電解はんだめっき工程
にて形成するはんだめっき厚さに相当する厚さである。
Next, as shown in FIG. 1 (e), a commercially available thick electroless copper plating solution comprising an alkali, copper sulfate, a chelating agent or the like is required for the exposed copper portion. The copper plating 5 having a thickness to be deposited is deposited. The required thickness of copper plating is a thickness corresponding to the thickness of the solder plating formed in the subsequent electroless solder plating step.

【0022】その後、図1(f)に示したように、市販
の無電解はんだめっき液、例えばシプレイファーイース
ト社製の商品名「ソルダーポジットXP-8955」を
用い、前述の析出した銅めっき5と同等厚みになるま
で、はんだめっき6を析出させ、銅めっき5をはんだめ
っき6で置換する。
Thereafter, as shown in FIG. 1 (f), using a commercially available electroless solder plating solution, for example, trade name “Solderposit XP-8955” manufactured by Shipley Far East Co., Ltd. The solder plating 6 is deposited until the thickness becomes equal to the thickness of the solder plating 6, and the copper plating 5 is replaced with the solder plating 6.

【0023】この方法では、図1(b)工程で、全面に
銅めっき3を析出させる時、同時に無電解はんだめっき
5の厚さ分も析出させれば、図1(e)工程で示したよ
うに二重の銅めっきは不要となるが、図1(c)工程で
回路を形成する際、溶解する銅の厚みが大きくなるた
め、原価高となり、また、高密度回路の形成が難しくな
る。最終的に必要があれば、はんだを溶融させる処理と
してホットオイルリフローやフュージング処理を行ない
完成となる。このようにして配線幅70μmの高密度プ
リント基板を得ることができた。
In this method, when the copper plating 3 is deposited on the entire surface in the step of FIG. 1B and simultaneously the thickness of the electroless solder plating 5 is also deposited, as shown in the step of FIG. As described above, double copper plating is not required, but when forming a circuit in the step of FIG. 1C, the thickness of the copper to be dissolved increases, which increases the cost and makes it difficult to form a high-density circuit. . If necessary, hot oil reflow or fusing is performed as a process for melting the solder, and the solder is completed. Thus, a high-density printed board having a wiring width of 70 μm was obtained.

【0024】〈実施例2〉この例は、実施例1よりもさ
らに高密度の配線パターンの形成に適したプリント基板
の構造と製造方法とを、以下に示す工程図2にしたがっ
て説明するものである。先ず、図2(a)に示したよう
に、銅張り積層板もしくは予め、内層回路を積層形成し
た内層入り銅張り積層板を基板1として準備し、この基
板内の所定位置に、貫通孔2をドリル、レーザビーム等
の周知の穿孔手段により設ける。
<Embodiment 2> In this embodiment, a structure and a manufacturing method of a printed circuit board suitable for forming a wiring pattern having a higher density than that of Embodiment 1 will be described with reference to the process chart 2 shown below. is there. First, as shown in FIG. 2A, a copper-clad laminate or a copper-clad laminate with an inner layer in which an inner layer circuit is previously formed is prepared as a substrate 1, and a through hole 2 is provided at a predetermined position in the substrate. Is provided by a known perforation means such as a drill and a laser beam.

【0025】次いで図2(b)に示したように、貫通孔
内壁を含む全面にパラジウム系触媒を付与し、その後必
要回路を形成するため、ドライフィルムを用いたテンテ
ィング法等により回路となる部分をマスキングし、エッ
チング工程にて回路以外の不要な銅箔を溶解除去し、回
路パターンを形成する。
Next, as shown in FIG. 2B, a circuit is formed by applying a palladium-based catalyst to the entire surface including the inner wall of the through-hole and then forming a necessary circuit by a tenting method using a dry film. The portion is masked, and unnecessary copper foil other than the circuit is dissolved and removed in an etching process to form a circuit pattern.

【0026】次いで図2(c)に示したように、銅めっ
きの必要な部分と部品実装時に必要となる部分のみを露
出させる形状で、エポキシ樹脂を主成分とする高耐薬品
性ソルダーレジスト4をスクリーン印刷法で形成させ
る。この時、実施例1で説明したようにソルダーレジス
トパターンの形成は、リソグラフィー技術で行うことも
できる。
Next, as shown in FIG. 2C, a high chemical resistance solder resist 4 mainly composed of an epoxy resin and having a shape exposing only a portion required for copper plating and a portion required for component mounting. Is formed by a screen printing method. At this time, as described in the first embodiment, the formation of the solder resist pattern can be performed by lithography.

【0027】次いで図2(d)に示したように、ソルダ
ーレジスト4をマスクとして、露出している銅めっきの
必要な部分に、アルカリ、硫酸銅、キレート剤等で構成
されている市販の厚付け無電解銅めっき液にて、最終的
に回路導体として必要とする厚みの銅めっきに、次の工
程で析出さるはんだめっきの厚み分を加えた厚みの銅め
っき5を析出させる。
Next, as shown in FIG. 2D, using a solder resist 4 as a mask, a commercially available thick plate made of an alkali, copper sulfate, a chelating agent, or the like is applied to an exposed portion of the copper plating that is required. Using an electroless copper plating solution, a copper plating 5 having a thickness obtained by adding the thickness of the solder plating deposited in the next step to the copper plating finally having a thickness required as a circuit conductor is deposited.

【0028】最後に図2(e)に示したように、再度ソ
ルダーレジスト4をマスクとして、市販の無電解はんだ
めっき液、例えばシプレイファーイースト社製の商品名
「ソルダーポジットXP-8955」を用いて必要厚み
のはんだめっき6を析出させる。この方法を用いれば、
実施例1のように銅めっきを二重に析出(銅めっき3と
5)させる必要がない上に、図2(b)工程に示したよ
うに回路を形成する際の銅溶解厚さ(銅箔である)が少
ないことから、低価格で高密度なプリント基板を得るこ
とが可能となる。最終的に必要があれば、はんだを溶融
させる処理としてホットオイルリフローやフュージング
処理を行ない完成となる。このようにして配線幅60μ
mの高密度プリント基板を得ることができた。
Finally, as shown in FIG. 2E, a commercially available electroless solder plating solution, for example, trade name "Solderposit XP-8955" manufactured by Shipley Far East Co., Ltd., was used again using the solder resist 4 as a mask. To deposit solder plating 6 having a required thickness. With this method,
It is not necessary to deposit copper plating twice (copper plating 3 and 5) as in Example 1, and the copper dissolution thickness (copper) when forming a circuit as shown in the step of FIG. (A foil), it is possible to obtain a low-cost, high-density printed circuit board. Finally, if necessary, hot oil reflow or fusing is performed as a process for melting the solder to complete the process. Thus, the wiring width of 60 μm
m was obtained.

【0029】以上説明したように、この例の特徴は、
(1)図1で示した実施例1よりも製造工程を短縮した
こと〔(図1(b)の無電解銅めっき工程(銅めっき
3)を省略した〕、(2)ソルダーレジスト4が被覆さ
れた基板上の配線回路は、銅めっきをせずに始めに基板
に接着した銅箔で構成したことにある。回路形成時のエ
ッチング対象が銅箔であることからエッチング工程が短
時間で済み、高精度に回路パターンが形成できる。
As described above, the features of this example are as follows.
(1) The manufacturing process is shorter than that of Example 1 shown in FIG. 1 ((Electroless copper plating process (copper plating 3) in FIG. 1B is omitted), (2) Solder resist 4 covers The wiring circuit on the substrate is made of copper foil that was first adhered to the substrate without copper plating, and the etching process was completed in a short time because the target to be etched when forming the circuit was copper foil. A circuit pattern can be formed with high accuracy.

【0030】[0030]

【発明の効果】以上説明したように本発明により所期の
目的を達成することができた。すなわち、無電解はんだ
めっきが均一な膜形成に優れているという特徴を最大限
に活かして高密度配線パターンの形成を可能とした。従
来技術では回路パターンの線幅が100μm〜120μ
m程度であったものを、本発明では60μm〜70μm
の形成を可能とした。
As described above, the intended object can be achieved by the present invention. That is, it is possible to form a high-density wiring pattern by making the most of the feature that the electroless solder plating is excellent in forming a uniform film. In the prior art, the line width of the circuit pattern is 100 μm to 120 μm.
m was changed to 60 μm to 70 μm in the present invention.
Was made possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例となるプリント基板の製造工
程を示した要部断面図。
FIG. 1 is an essential part cross sectional view showing a manufacturing step of a printed circuit board according to one embodiment of the present invention;

【図2】同じく他の実施例となるプリント基板の製造工
程を示した要部断面図。
FIG. 2 is an essential part cross sectional view showing a printed circuit board manufacturing process according to another embodiment;

【符号の説明】[Explanation of symbols]

1…銅張り積層板、 2…貫通
孔、3…銅めっき、 4…ソ
ルダーレジスト、5…無電解銅めっき、
6…無電解はんだめっき。
1 ... copper-clad laminate, 2 ... through-hole, 3 ... copper plating, 4 ... solder resist, 5 ... electroless copper plating,
6 ... Electroless solder plating.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 川上 明仁 神奈川県横浜市戸塚区戸塚町216番地 株式会社日立製作所情報通信事業部内 (72)発明者 鈴木 徹 東京都千代田区三番町三丁目8番地 シ プレイ・ファーイースト株式会社内 (72)発明者 土谷 譲二 東京都千代田区三番町三丁目8番地 シ プレイ・ファーイースト株式会社内 審査官 中川 隆司 (56)参考文献 特開 平4−239796(JP,A) 特開 平3−4595(JP,A) (58)調査した分野(Int.Cl.7,DB名) H05K 3/24 H05K 3/28 H05K 3/34 H05K 3/42 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihito Kawakami 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within the Information and Communication Business Department, Hitachi, Ltd. (72) Inventor Tohru Suzuki 3-chome, Sanbancho, Chiyoda-ku, Tokyo (72) Inventor Joji Tsuchiya Examiner, Takafumi Nakagawa, 3-8 Sanbancho, Chiyoda-ku, Tokyo (56) Inventor Takashi Nakagawa (56) References JP-A-4-239796 ( JP, A) JP-A-3-4595 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 3/24 H05K 3/28 H05K 3/34 H05K 3/42

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】内面が銅めっき上に無電解はんだめっきさ
れた貫通孔と、その開口部周縁の銅箔上に銅めっき
よび前記銅めっき層の一部を残しその表層部を無電解は
んだめっきにより置換めっきした無電解はんだめっき層
を有するランドと、基板表面の銅箔が選択エッチングに
よりパターン化された回路部と、前記銅箔回路部上を含
むはんだ接続領域外の基板表面を密着被覆したソルダー
レジストとを有して成るプリント基板。
1. A a through hole inner surface is electrolessly solder plating on the copper plating, the surface layer leaving a portion of the copper plating layer Contact <br/> spare the copper plating layer on the copper foil of the opening peripheral edge Electroless solder plating layer where the part is replaced by electroless solder plating
Having a land having a pattern, a circuit portion in which a copper foil on the substrate surface is patterned by selective etching, and a solder resist which closely covers the surface of the substrate outside the solder connection region including on the copper foil circuit portion. substrate.
【請求項2】上記無電解はんだめっきの厚みを0.5
〜10μmとして成る請求項1記載のプリント基板。
2. The thickness of the electroless solder plating layer is 0.5.
2. The printed circuit board according to claim 1, wherein the thickness of the printed circuit board is 10 to 10 [mu] m.
【請求項3】上記ソルダーレジストをエポキシ系レジス
トで構成して成る請求項1もしくは2記載のプリント基
板。
3. The printed circuit board according to claim 1, wherein said solder resist is composed of an epoxy-based resist.
【請求項4】両面銅張り基板に貫通孔を形成する工程
と、触媒付与工程を経て、基板表面の銅箔を所定のレジ
ストマスクを用いて選択エッチングすることにより貫通
孔の開口部周縁にはランドを、その他の領域には配線回
路パターンを形成する工程と、前記ランドおよび配線回
路パターンが形成された基板表面に、はんだめっきを必
要とする領域を除き、少なくとも配線回路パターン上を
密着被覆してソルダーレジストパターンを形成する工程
と、前記ソルダーレジストパターンをマスクとして、前
記貫通孔内およびランド上に、後工程で形成するはんだ
めっき膜厚に相当する膜厚を超える無電解銅めっき厚膜
を選択的に形成する工程と、前記無電解銅めっき膜上に
無電解はんだめっきを施すことにより、前記無電解銅め
っき膜の一部を残しその表層部前記はんだめっき膜で
置換めっきする工程とを有して成るプリント基板の製造
方法。
4. A step of forming a through-hole in a double-sided copper-clad substrate and a step of applying a catalyst, and then selectively etching a copper foil on the surface of the substrate using a predetermined resist mask to form a through-hole around the opening. Land, a step of forming a wiring circuit pattern in other areas, and tightly covering at least the wiring circuit pattern on the surface of the substrate on which the lands and the wiring circuit pattern are formed, except for an area requiring solder plating. Forming a solder resist pattern, and using the solder resist pattern as a mask , forming a thick electroless copper plating film in the through hole and on the land, the thickness of which exceeds a thickness corresponding to a solder plating film thickness to be formed in a later step. selectively forming, by performing an electroless solder plating on the electroless copper plating film, leaving a part of the electroless copper plating film Process and PCB fabrication method comprising a replacing plating surface layer portion in the solder plating film.
JP05197085A 1993-08-09 1993-08-09 Printed circuit board and method of manufacturing the same Expired - Fee Related JP3130707B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP05197085A JP3130707B2 (en) 1993-08-09 1993-08-09 Printed circuit board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05197085A JP3130707B2 (en) 1993-08-09 1993-08-09 Printed circuit board and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH0750470A JPH0750470A (en) 1995-02-21
JP3130707B2 true JP3130707B2 (en) 2001-01-31

Family

ID=16368480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP05197085A Expired - Fee Related JP3130707B2 (en) 1993-08-09 1993-08-09 Printed circuit board and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3130707B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5363377B2 (en) * 2010-02-19 2013-12-11 新光電気工業株式会社 Wiring board and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0750470A (en) 1995-02-21

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