JPH03175695A - Manufacture of through hole printed wiring board - Google Patents

Manufacture of through hole printed wiring board

Info

Publication number
JPH03175695A
JPH03175695A JP31555289A JP31555289A JPH03175695A JP H03175695 A JPH03175695 A JP H03175695A JP 31555289 A JP31555289 A JP 31555289A JP 31555289 A JP31555289 A JP 31555289A JP H03175695 A JPH03175695 A JP H03175695A
Authority
JP
Japan
Prior art keywords
plating
electroless
hole
copper foil
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31555289A
Other languages
Japanese (ja)
Inventor
Eiji Shimamoto
島本 栄司
Megumi Tanimoto
恵 谷本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP31555289A priority Critical patent/JPH03175695A/en
Publication of JPH03175695A publication Critical patent/JPH03175695A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize the advancement of wiring density and the improvement of performance by etching the copper foil of a printed wiring board so as to form a circuit pattern, and then performing electroless nickel plating and electroless gold plating, and then electrolessly plating its whole face, and electrically plating only the through hole and the land part selectively. CONSTITUTION:A copper foil 2 is stuck to a base material 1, and a through hole 3 is bored, and an etching resist 6 is made at the part required as a circuit, and the copper foil 2 and the etching resist 6 at the unnecessary part are removed by etching, and electroless platings of nickel and gold are applied onto the parts to become circuits so as to form electroless nickel and electroless gold plating layers 8, and then electroless copper plating is applied to the whole face of the board so as to form an electroless plating layer 5. Next, plating resists 10 are made at the parts excluding the through hole 3, requiring through hole plating, and the land part 30, and then electric copper plating is applied to form an electric copper plating layer 9. Lastly, after the plating resist 10 is separated, the electroless copper plating layer 5 is removed.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 スルホールプリント配線板の製造方法に関する。[Detailed description of the invention] <Industrial application field> The present invention relates to a method for manufacturing a through-hole printed wiring board.

〈従来の技術〉 第2図(a)乃至(d)は、従来片われてきたパネルメ
ッキ法であり、その経時的に示す模式断面図を示す。
<Prior Art> FIGS. 2(a) to 2(d) show schematic cross-sectional views over time of a panel plating method that has been conventionally used.

(a)に示すように、ベース基材1に銅箔2を貼り合わ
せ、その後スルホール3の穴あけを行う。
As shown in (a), a copper foil 2 is bonded to a base material 1, and then through holes 3 are bored.

この銅箔2の厚さは、通常18μmであり、これより薄
い9μmあるいは5μmの銅箔を用いたり、また銅張基
材全体にエツチングを行うことにより銅箔を薄くしたも
のを用いている。スルホール3の穴あけは、ドリリング
あるいはパンチングにより行う。
The thickness of this copper foil 2 is usually 18 μm, and a thinner copper foil of 9 μm or 5 μm is used, or a copper foil made thinner by etching the entire copper-clad base material is used. The through hole 3 is formed by drilling or punching.

次いで(b)に示すように、スルホール3および銅M2
に無電解銅メッキおよび電気銅メッキを行い、無電解鋼
メッキおよび電気銅メッキ層4を形成し、(C)に示す
ように、所定の部分に工・ンチングレジスト6を形成し
た後、エツチングにより不要部分の銅を除去すると、(
d)に示すように、回路7が形成される。
Then, as shown in (b), throughhole 3 and copper M2
Electroless copper plating and electrolytic copper plating are performed to form electroless steel plating and electrolytic copper plating layer 4, and as shown in FIG. When unnecessary copper is removed by (
As shown in d), a circuit 7 is formed.

〈発明が解決しようとする課題〉 tCチップ実装方法の開発に伴い、回路ピッチは、現在
工業的に安定生産が可能といわれている100μmのラ
インをすでに越えている。
<Problems to be Solved by the Invention> With the development of the tC chip mounting method, the circuit pitch has already exceeded the 100 μm line, which is said to be capable of stable industrial production.

従来の製造方法においては、15〜25μmのスルホー
ル銅メッキ層の厚さ分がベース基材に貼り合わせた銅箔
の厚さに加算されるため、パターン形成時におけるエツ
チング加工が過剰の場合、微細回路が細くなり断線した
り、また上記エツチング加工が不足の場合、回路5間隔
が狭い部分で充分に銅がエンチング除去されずタッチが
発生する。
In conventional manufacturing methods, the thickness of the through-hole copper plating layer of 15 to 25 μm is added to the thickness of the copper foil bonded to the base material, so if the etching process is excessive during pattern formation, fine etching may occur. If the circuit becomes thin and breaks, or if the etching process described above is insufficient, copper will not be sufficiently etched away in areas where the distance between the circuits 5 is narrow, resulting in a touch.

このようなパターン形成における問題点であるタッチの
発生を防ぐためには、回路間隔は銅箔およびそのメッキ
層のトータルの厚さのおよそ2倍以上を必要とする。と
ころが銅メッキ層の厚さを薄<シた場合、半田付は時の
熱ストレスによりスルホールの導通信頼性を確保するこ
とができない。
In order to prevent the occurrence of touching, which is a problem in pattern formation, the circuit spacing needs to be approximately twice or more the total thickness of the copper foil and its plating layer. However, if the thickness of the copper plating layer is reduced, it is not possible to ensure conduction reliability of the through-holes due to the thermal stress during soldering.

このような問題の解決手段として、従来、通常よりも薄
い9μmまたは5μmの銅箔をベース材に貼り合わせた
基材を用いることを行ってきた。
As a means of solving such problems, conventionally, a base material has been used in which a copper foil of 9 μm or 5 μm, which is thinner than usual, is bonded to the base material.

この銅箔はしわを防ぐためアルミ箔を貼り合わせたもの
となっている。ところがこの銅箔はコスト高であるとと
もに、上記アルミ箔を除去する工程が必要であり、製造
工程の増加をまねく。また他の手段としては、一般に使
用されている18μmの厚さの銅箔を貼り合わせた基材
を、パターン形成前にエツチングし約9μmの厚さに薄
くする方法を用いるが、この場合、基板全体を均一にし
かも所定の厚さにコントロールしてエツチングすること
は困難である。本発明ではこのような問題を解決する。
This copper foil is laminated with aluminum foil to prevent wrinkles. However, this copper foil is expensive and requires a step to remove the aluminum foil, which increases the number of manufacturing steps. Another method is to etch a generally used base material to which a copper foil of 18 μm thick is attached to a thickness of about 9 μm before forming the pattern, but in this case, the substrate It is difficult to etch the entire surface uniformly and to control it to a predetermined thickness. The present invention solves these problems.

〈課題を解決するための手段〉 スルホールプリント配線板の製造方法は、銅箔をベース
基材に貼り合わせ、スルホールを形成してなるプリント
配線板において、そのプリント配線板の上記!rl F
fiをエツチングすることにより回路パターンを形威し
、その回路パターンに無電解ニッケルメッキおよび無電
解金メッキを行った後、そのプリント配線板の全面を無
電解メッキし、さらにスルホールおよびそのランド部の
みを選択的に電気メンキし、無電解メッキ層を除去する
ことを特徴としている。
<Means for solving the problem> A method for manufacturing a through-hole printed wiring board is a printed wiring board in which copper foil is bonded to a base material to form through-holes. rl F
After shaping the circuit pattern by etching fi and electroless nickel plating and electroless gold plating on the circuit pattern, electroless plating is applied to the entire surface of the printed wiring board, and then only the through holes and their lands are plated. It is characterized by selectively electroplating and removing the electroless plating layer.

〈作用〉 本発明の製造方法では、銅箔のみをエツチングするので
微細回路の形成が容易である。またその微細回路は無電
解ニッケルメッキおよび無電解金メッキを行うことより
そのメッキ層が保護膜となる。さらにスルホールおよび
そのランド部のみを選択的にメッキすることにより、そ
のメッキ層は′スルホールにおける導通が充分に可能な
所望の厚さを確保できる。
<Function> In the manufacturing method of the present invention, since only the copper foil is etched, it is easy to form a fine circuit. Furthermore, by performing electroless nickel plating and electroless gold plating on the fine circuit, the plating layer becomes a protective film. Furthermore, by selectively plating only the through-holes and their lands, the plating layer can have a desired thickness that allows sufficient conduction in the through-holes.

〈実施例〉 第1図(a)乃至(h)は、本発明における実施例であ
り、その製造工程の模式断面図を示す。
<Example> FIGS. 1(a) to 1(h) are examples of the present invention, and show schematic cross-sectional views of the manufacturing process thereof.

(a)に示すように、ベース基材1に銅箔2を貼り合わ
せ、その後スルホール3の穴あけを行う。
As shown in (a), a copper foil 2 is bonded to a base material 1, and then through holes 3 are bored.

この銅箔2の厚さは、一般に使用されている18μmで
ある。
The thickness of this copper foil 2 is 18 μm, which is commonly used.

次いで(b)に示すように、回路として必要な部分にエ
ツチングレジスト6を形成する。
Next, as shown in FIG. 3B, an etching resist 6 is formed in the areas necessary for the circuit.

次いで(C)に示すように、エツチングにより不要部分
の銅箔2およびエツチングレジスト6を除去することに
より回路となる部分を形成する。
Next, as shown in (C), unnecessary portions of the copper foil 2 and etching resist 6 are removed by etching to form a portion that will become a circuit.

次いで(d)に示すように、次工程に必要とする例えば
触媒処理などの前処理を行った後、上記回路となる部分
上にニッケルおよび金の無電解メッキを行い、無電解ニ
ッケルおよび無電解金メッキ層8を形成する。
Next, as shown in (d), after performing pretreatment such as catalyst treatment required for the next step, electroless plating of nickel and gold is performed on the part that will become the circuit, and electroless nickel and gold are plated. A gold plating layer 8 is formed.

次いで(e)に示すように、次工程に必要とする例えば
触媒処理などの前処理をjテった後、上記基板全面に無
電解銅メッキを行い、無電解消メッキ層5を形成する。
Next, as shown in (e), after pre-treatment such as catalyst treatment required for the next step, electroless copper plating is performed on the entire surface of the substrate to form an electroless plating layer 5.

次いで(f)に示すように、上記無電解銅メ・ツキ層5
上において、スルホールメッキを必要とするスルホール
3およびそのランド部30を除いた部分にメンキレジス
ト10を形成する。
Next, as shown in (f), the electroless copper plating layer 5
At the top, a coating resist 10 is formed on the portions excluding the through-holes 3 that require through-hole plating and their land portions 30.

次いで(g)に示すように、電気銅メッキを行い、スル
ホール3内およびそのランド部30に所定の厚さのメッ
キを行い電気銅メッキ層9を形成する。この場合必要に
応じて半田メッキを行なってもよい。
Next, as shown in (g), electrolytic copper plating is performed to form an electrolytic copper plating layer 9 within the through hole 3 and its land portion 30 to a predetermined thickness. In this case, solder plating may be performed if necessary.

そして最後に(h)に示すように、メッキレジスト10
を剥離後、さらに全面にクィックエ・ンチを行い、回路
パターン11以外に付着している無電解銅メッキ層5を
除去し回路パターン11を得る。
Finally, as shown in (h), the plating resist 10
After peeling off, the entire surface is further subjected to quick etching to remove the electroless copper plating layer 5 adhering to areas other than the circuit pattern 11, thereby obtaining the circuit pattern 11.

なお回路形成において、ICのダイレクトボンディング
用として部分的に厚い回路、例えばバンプ等を設ける必
要のある場合、上記実施例において所定部分にメッキレ
ジスト10を施さないことにより、スルホール3および
そのランド部30のメッキを行うと同時に回路形成がで
きる。
In circuit formation, if it is necessary to provide a partially thick circuit, such as a bump, for direct bonding of an IC, by not applying the plating resist 10 to a predetermined portion in the above embodiment, the through hole 3 and its land portion 30 can be formed. The circuit can be formed at the same time as plating.

以上の実施例は回路ピッチがl100II以下のスルホ
ール基板に用いられるが、特に回路ピッチが25〜40
μmの場合においても5μmまたは9μmの厚さの銅箔
を使用し、実施例と同一の工程により回路パターンの形
成ができる。さらに、上記実施例は片面および両面基板
はもとより多層基板にも適用できる。
The above embodiments are used for through-hole boards with a circuit pitch of 1100II or less, but especially with a circuit pitch of 25 to 40
Even in the case of μm, the circuit pattern can be formed by using copper foil with a thickness of 5 μm or 9 μm and following the same steps as in the example. Furthermore, the above embodiments can be applied not only to single-sided and double-sided substrates but also to multilayer substrates.

〈発明の効果〉 以上説明したように、本発明による製造方法によれば、
100μm以下の回路ピッチをもつ微細回路の形成が容
易となる。またその工程において、微細回路の保護膜が
形成されるため、その後の工程における微細回路への影
響がない。さらにスルホール部分における電気銅メッキ
は所定の厚さを確保できるため、その導通信頼性が高く
なる。
<Effects of the Invention> As explained above, according to the manufacturing method of the present invention,
It becomes easy to form fine circuits with a circuit pitch of 100 μm or less. In addition, since a protective film for the microcircuit is formed in that process, there is no influence on the microcircuit in subsequent steps. Furthermore, since the electrolytic copper plating on the through-hole portion can ensure a predetermined thickness, its conduction reliability is increased.

したがって配線密度の高度化およびその性能はますます
向上する。
Therefore, the wiring density and its performance are further improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)乃至(h)は本発明方法における実施例の
模式断面図、第2図(a)乃至(d)は従来例で経時的
に示す模式断面図である。 1・・・ベース基材 2・・・銅箔 3・・・スルホール 5・・・無電解銅メッキ層 6・・・エツチングレジスト 8・・・無電解ニッケル および無電解金メッキ層 9・・・電気銅メッキ層 10・・・メッキレジスト 11・・・回路パターン 30・・・スルホールランド部 第1図 第1図
FIGS. 1(a) to (h) are schematic cross-sectional views of an embodiment of the method of the present invention, and FIGS. 2(a) to (d) are schematic cross-sectional views of a conventional example shown over time. 1... Base substrate 2... Copper foil 3... Through hole 5... Electroless copper plating layer 6... Etching resist 8... Electroless nickel and electroless gold plating layer 9... Electricity Copper plating layer 10...Plating resist 11...Circuit pattern 30...Through hole land portion Fig. 1 Fig. 1

Claims (1)

【特許請求の範囲】[Claims] 銅箔をベース基材に貼り合わせ、スルホールを形成して
なるプリント配線板において、そのプリント配線板の上
記銅箔をエッチングすることにより回路パターンを形成
し、その回路パターンに無電解ニッケルメッキおよび無
電解金メッキを行った後、そのプリント配線板の全面を
無電解メッキし、さらにスルホールおよびそのランド部
のみを選択的に電気メッキし、無電解メッキ層を除去す
ることを特徴とするスルホールプリント配線板の製造方
法。
In a printed wiring board formed by bonding copper foil to a base material and forming through holes, a circuit pattern is formed by etching the copper foil of the printed wiring board, and the circuit pattern is coated with electroless nickel plating and non-electrolytic nickel plating. A through-hole printed wiring board characterized in that after performing electrolytic gold plating, the entire surface of the printed wiring board is electrolessly plated, and further, only the through holes and their lands are selectively electroplated, and the electroless plating layer is removed. manufacturing method.
JP31555289A 1989-12-04 1989-12-04 Manufacture of through hole printed wiring board Pending JPH03175695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31555289A JPH03175695A (en) 1989-12-04 1989-12-04 Manufacture of through hole printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31555289A JPH03175695A (en) 1989-12-04 1989-12-04 Manufacture of through hole printed wiring board

Publications (1)

Publication Number Publication Date
JPH03175695A true JPH03175695A (en) 1991-07-30

Family

ID=18066719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31555289A Pending JPH03175695A (en) 1989-12-04 1989-12-04 Manufacture of through hole printed wiring board

Country Status (1)

Country Link
JP (1) JPH03175695A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7726016B2 (en) 2003-05-07 2010-06-01 International Business Machines Corporation Manufacturing method of printed circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7726016B2 (en) 2003-05-07 2010-06-01 International Business Machines Corporation Manufacturing method of printed circuit board
US7834277B2 (en) 2003-05-07 2010-11-16 International Business Machines Corporation Printed circuit board manufacturing method and printed circuit board

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