JPH11135940A - Manufacture of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a highly precise circuit by narrowing the interval of a circuit pattern, and improve repairability by increasing peeling resistance of a pad part, by forming a circuit pattern of an outermost layer of a copper foil alone, and forming a copper plating layer only in an inner wall surface of a through hole or a via hole. SOLUTION: Copper plating 60 is formed only in an inner wall surface of a small hole if copper plating is applied to a lamination. After the copper plating 60 is formed to a specified thickness, plating resist is peeled. A circuit pattern 24A is formed in a copper foil of the lamination by photoetching, etc. As a result, a via hole 52A and a through hole 54A are formed. Since the circuit pattern 24A of an outermost layer formed in this way is formed of a copper foil alone, its peeling resistance is large. Therefore, if heating is carried out for removing a part mounted on a pad of the circuit pattern 24A of an outermost layer, the pad is hardly peeled from an insulation plate and repairability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board using a build-up method.

[0002]

2. Description of the Related Art A build-up method is known in which a conductor pattern and an insulating layer are sequentially stacked while a circuit pattern of an inner layer is formed for each layer to manufacture a multilayer printed wiring board.

FIG. 4 is a view showing a method of manufacturing a multilayer printed wiring board using a conventional build-up method. In this method, first, a circuit pattern of the second layer 12 and the third layer 14 serving as a core layer is formed on both surfaces of the insulating plate 10 (step A).
In this case, for example, using a double-sided copper-clad laminate, a circuit pattern is formed on both surfaces thereof by a photoetching method using a known dry film or a photoresist solution to form a second layer 12 and a third layer 14, respectively. Can be. Instead of the photo-etching method, a method of printing and etching an etching resist by printing may be used.

Next, insulating substrates 16 and 16 are laminated on the second and third layers 12 and 14 (step B). Insulating substrates 16, 16
A known prepreg may be laminated and cured, or an insulating plate may be bonded with an epoxy adhesive or the like. The small holes 1 for via holes are formed in the insulating substrates 16 and 16 thus laminated.
8, 18 are processed (process C). This processing can be performed by, for example, vertically irradiating a laser beam with a reduced diameter to the processing position of the via hole. Since the laser beam cannot process the circuit pattern (copper foil) of the lower second layer 12 or the third layer 14, the small holes 18 reaching the second and third layers 12 and 14 can be processed.

Next, after removing the hardening of the resin (resin residue) generated around the small holes 18 when the small holes 18 are processed by the laser beam, a panel plating 20 is applied to the surface (step D). The panel plating 20 is formed on the insulating substrate 16,
The electroless copper plating is applied to the surface of the surface 16 and the inner wall surface of the small hole 18 to impart conductivity, and then the electrolytic copper plating is performed to obtain a required copper plating thickness. By forming the panel plating 20 on the inner wall surface of the small hole 18, a via hole 18A is formed.

Then, a circuit pattern 20A is formed on the panel plating 20 (step E). This circuit pattern 20
For the processing of A, a known tenting method or a hole filling method can be used. In the tenting method, a film type photoresist is used as an etching resist, and the small holes 18 of the via holes are covered with a resist film like a tent, and etching is performed while leaving the resist film in another circuit pattern. In the hole filling method, a resist ink is filled in small holes 18 for through holes, and then a resist is screen-printed on both surfaces and etched.

According to the method shown in FIG. 4, the conductor thickness of the circuit pattern 20A as the outermost layer can be reduced. Therefore, it is possible to form a high-definition circuit with high etching accuracy.

FIG. 5 is a diagram showing another conventional build-up method. In this method, after forming a circuit pattern of the second layer 12 and the third layer 14 serving as a core layer on both surfaces of the insulating substrate 10 (Step A), the single-sided copper-clad insulating plates 22, 22 are laminated on both surfaces (Step A). B). 24 and 24 are copper foils. Instead of the copper-clad insulating plate 22, a resin-coated copper foil may be bonded.

Next, a hole 26 is formed in the copper foil 24 at a position where a via hole is to be formed by etching (step C). Then, when the laser beam is vertically irradiated from above the copper foil 24, the insulating plate 22 below the hole 26 is removed and a small hole 28 is formed (step D). The small holes 28 reach the second and third lower layers 12 and 14.

Next, copper plating layers 30 are formed on both surfaces of the laminate (step E). The copper plating layer 30 is formed by applying conductivity to the inner wall surface of the small hole 28 by electroless copper plating and then performing electrolytic copper plating. Finally, if the outermost circuit pattern 30A is processed by etching, a via hole 28A connecting the inner layer circuit patterns 12, 14 and the outermost circuit pattern 30A is formed (step F).

According to the method shown in FIG.
Alternatively, since a resin-coated copper foil or a copper foil laminate is used, the adhesive strength between the copper foil 24 and the insulating plate 22 increases,
Increases peel strength. For this reason, even when the components mounted on the surface are exchanged and heated for melting solder, the circuit pattern 30A of the outermost layer, that is, the pad portion is not easily peeled off. That is, it is excellent in the repairability (repairability) of the mounted component.

[0012]

Problems of the Prior Art According to the method shown in FIG.
Since the outermost circuit pattern 20A is formed of a copper plating layer directly plated on an insulating plate, it is difficult to increase the peel strength of a pad portion for mounting components. Therefore, there is a problem that the repairability is poor.

According to the method shown in FIG. 5, the outermost circuit pattern 30A has a thick conductor since the copper plating layer 30 is formed on the copper foil 24. Therefore, there is a problem that it is difficult to form a high definition circuit.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and improves the repairability by increasing the peel strength of a pad portion on which components are mounted. It is an object of the present invention to provide a method for manufacturing a printed wiring board that enables formation of a fine circuit.

[0015]

According to the present invention, it is an object of the present invention to provide a method for manufacturing a printed wiring board using a build-up method in which a conductor layer and an insulating layer are sequentially stacked while forming a circuit of each layer, and (A) an outer layer is formed. Forming a laminate in which copper foils are laminated; (B) forming small holes for forming at least one of a through hole and a via hole in the laminate;
(C) attaching a catalyst for electroless plating to the inner wall surface of the small hole; (D) covering the outer layer copper foil with a plating resist except for the opening of the small hole; (E) the laminate Electroless copper plating and electrolytic copper plating are sequentially applied to (F)
(G) forming a circuit pattern on the copper foil of the outer layer; a method for manufacturing a printed wiring board, comprising the above steps.

That is, the circuit pattern of the outermost layer is formed only of copper foil, and the copper plating layer is formed only on the inner wall surface of the through hole or the via hole. The copper plating layer is formed not only on the inner wall surface of the through hole and via hole but also on the outermost layer circuit pattern where there is no need to narrow the line interval, for example, over a copper foil at a part of the pad part etc. Is also good.

Here, small holes for forming through holes or via holes can be processed using a laser beam or a plasma beam. For example, a small hole is formed in the outermost copper foil by etching, and a small hole for a through hole or a via hole can be processed by irradiating a laser beam or a plasma beam on the small hole.

[0018]

1 is a diagram showing the first half of the process of the present invention, FIG. 2 is a diagram showing the second half of the process, and FIG. 3 is a partially enlarged view of III in FIG. 2 showing the structure of a via hole.

First, similarly to the conventional method described with reference to FIG. 5, a second layer 12 and a second layer 14 serving as core layers are formed on both surfaces of an insulating substrate 10, and a single-sided copper-clad insulating plate 22,
The laminated body 50 is prepared by bonding and laminating 22 (step A in FIG. 1). Here, instead of using the single-sided copper-clad insulating plate 22, a copper foil with resin may be used.

The copper foils 24, 24 of the laminate 50 have small holes 5 for via holes in the same manner as in steps C, D of FIG.
2 and small holes 54 for through holes are formed (step B in FIG. 1). That is, the copper foils 24, 24 are etched.
Small holes are formed at positions corresponding to the via holes and through holes, and the small holes 52 and 54 can be processed by irradiating a laser beam or a plasma beam from above.

The catalyst 5 is provided on the surface of the laminate 50 in which the small holes 52 and 54 are processed and on the inner wall surfaces of the small holes 52 and 54.
6 is given (step C in FIG. 1). This application of the catalyst 56 is a pretreatment step of electroless copper plating performed later, and after the degreasing, soft etching (surface roughening) and the like, the surface of the copper foil 24 and the inner wall surfaces of the small holes 52 and 54 are formed. Pb-S
n (alloy core) colloid particles are adsorbed. The colloid particles are hydrolyzed in the next washing step, and are activated by the accelerator treatment solution to form a base for electroless copper plating.

The laminated body 5 thus provided with the catalyst 56
0 is covered with a plating resist 58 (step D in FIG. 1). The plating resist 58 can be formed by, for example, screen printing. In this case, the resist ink can be supplied only to the surface of the copper foil 24 by rubbing the resist ink while closing the openings of the small holes 52 and 54 with the stencil screen.

If the laminate 50 is immersed in an electroless copper plating bath and then immersed in an electrolytic copper plating bath to perform copper plating, the small holes 52 and 54 provided with active Pb-Sn nucleus colloid particles are formed. Copper plating 60 is formed only on the inner wall surface (step E in FIG. 2). After forming the copper plating 60 to a predetermined thickness, the plating resist 58 is peeled off (Step F in FIG. 1). Then, a circuit pattern 24A is formed on the copper foils 24, 24 of the laminate 50 by known photoetching or the like (step G in FIG. 2). In this case, a tenting method or a hole filling method is used to close the openings of the small holes 52, 54. Can be used. As a result, a via hole 52A and a through hole 54A having the structure shown in step G of FIG. 2 and FIG. 3 are formed.

Since the outermost circuit pattern 24A formed in this way is formed only of the copper foil 24, the peel strength is large. That is, the copper foil 24 is firmly bonded to the insulating plate in advance as the one-sided copper-clad insulating plate 22, or is firmly bonded and laminated to the core layer as a resin-coated copper foil. For this reason, when the component mounted on the pad portion of the circuit pattern 24A of the outermost layer is heated to remove the component, the pad portion is not easily peeled off the insulating plate 22 and the repairability is excellent. Further, since the thickness of the circuit pattern 24A formed only of the copper foil 24 is sufficiently thin, the line spacing of the circuit pattern is sufficiently narrowed to achieve high definition.

In the above embodiment, since the entire surface of the copper foil 24 is covered with the plating resist 58 in the step D of FIG. 1, the circuit pattern 24A of the outermost layer is entirely formed of only the copper foil 24. . However, according to the present invention, a portion of the circuit pattern 24A that does not need to be narrowed in line spacing (circuit pattern interval), for example, a portion of a pad portion is not covered with a plating resist, and this portion is plated with copper. May be. Of course, the circuit pattern is not limited to four layers.

[0026]

As described above, according to the first aspect of the present invention, copper plating is applied only to the inner wall surfaces of the through holes and the via holes (the portions where it is not necessary to reduce the line interval between these inner wall surfaces and the outermost circuit pattern). As a result, the peel strength of the pad portion on which the component is mounted is increased, and the repairability is excellent. In addition, since the circuit pattern is made of only copper foil without being subjected to copper plating, the conductor thickness of the circuit pattern can be made sufficiently thin to achieve high definition.

If the portion to be covered with the plating resist is not the entire surface of the copper foil but only the portion of the circuit pattern that needs to be narrowed, the copper plating is applied only to the portion of the circuit pattern that requires high definition. Since only copper foil can be used without performing the above, the object of the present invention can be achieved similarly (claim 2).

In processing small holes for via holes and through holes in step B, a laser beam or a plasma beam can be used (claim 3). In this case, a small hole may be formed in the copper foil by etching, and a small hole extending from the copper foil to the insulating layer may be formed by irradiating the small hole with a laser beam or a plasma beam.

[Brief description of the drawings]

FIG. 1 shows the first half of the steps of the method of the present invention.

FIG. 2 is a view showing the latter half of the process.

FIG. 3 is an enlarged view of a portion III in FIG. 2;

FIG. 4 is a diagram showing steps of a conventional method.

FIG. 5 is a diagram showing steps of a conventional method.

[Explanation of symbols]

 10, 22 Insulating plate 12 Circuit pattern of second layer 14 Circuit pattern of third layer 24 Copper foil 24A Circuit pattern of outermost layer 50 Stack 52 Small hole for via hole 52A Via hole 54 Small hole for through hole 54A Through hole 56 Catalyst 58 Plating resist 60 Copper plating

Claims (3)

[Claims] 1. A method of manufacturing a printed wiring board using a build-up method in which a conductor layer and an insulating layer are sequentially stacked while forming a circuit of each layer, wherein: (A) forming a laminate in which copper foil as an outer layer is stacked; (B) forming small holes for forming at least one of a through hole and a via hole in the laminate; (C) attaching a catalyst for performing electroless plating to the inner wall surface of the small hole; (D) covering the outer layer copper foil except for the openings of the small holes with a plating resist; (E) sequentially applying electroless copper plating and electrolytic copper plating to the laminate; (F) removing the plating resist (G) forming a circuit pattern on the outer layer copper foil; a method for manufacturing a printed wiring board, comprising the above steps. 2. The method for manufacturing a printed wiring board according to claim 1, wherein in the step (D), the plating resist covers the copper foil except for the openings of the small holes and portions where it is not necessary to reduce the line spacing of the outer layer circuit pattern. . 3. In the step (B), a small hole for forming at least one of a through hole and a via hole is formed by: (Ba) forming a small hole in an outer copper foil by etching; (Bb) a laser beam or 2. The method for manufacturing a printed wiring board according to claim 1, wherein a small hole is formed in the insulating layer below the small hole formed in the copper foil in the step (Ba) using a plasma beam.