JP2001189536A - Wiring substrate - Google Patents

Wiring substrate

Info

Publication number
JP2001189536A
JP2001189536A JP37267199A JP37267199A JP2001189536A JP 2001189536 A JP2001189536 A JP 2001189536A JP 37267199 A JP37267199 A JP 37267199A JP 37267199 A JP37267199 A JP 37267199A JP 2001189536 A JP2001189536 A JP 2001189536A
Authority
JP
Japan
Prior art keywords
copper
metal core
wiring board
metal
thermal expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP37267199A
Other languages
Japanese (ja)
Inventor
Nobuyuki Ushifusa
信之 牛房
Terutaka Mori
照享 森
Takehiko Hasebe
健彦 長谷部
Kiyomitsu Suzuki
清光 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP37267199A priority Critical patent/JP2001189536A/en
Publication of JP2001189536A publication Critical patent/JP2001189536A/en
Pending legal-status Critical Current

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  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable high-density wiring by forming a metal core with a material having a low thermal expansion coefficient. SOLUTION: An external layer is formed by laminating a copper-clad insulating sheet, which is formed by forming an insulating layer on a copper foil, to a single side or both sides of a metal-core copper-clad laminate, on which circuits have been formed on its single side or both sides. The copper foil in unnecessary regions of the external layer is removed by etching. The insulating layer in specified regions are removed, and via holes are formed, through which electrical continuity is made to form a metal-core multilayer laminate, on which semiconductor components are mounted. The purpose is achieved by using for the metal core a copper material compounded with copper oxide which is a material having a low thermal expansion coefficient or a clad material which is formed by laminating the copper material compounded with copper oxide to adhere to an iron-nickel alloy.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は配線基板に関し、特
に低熱膨張係数の金属コアを有する配線基板に関する。
The present invention relates to a wiring board, and more particularly to a wiring board having a metal core having a low coefficient of thermal expansion.

【0002】[0002]

【従来の技術】近年電子機器の小型化に伴い、それに用
いられる配線基板についても、小型化、高密度化、軽量
化、高信頼性などが求められており、配線基板における
配線幅、配線間隙、スルーホールおよびビアホールの微
細化、高信頼性への要求が高まっている。これらのうち
配線幅、配線間隙については、感光性エッチングレジス
トやエッチング液の開発がなされ、導体箔や絶縁層を薄
くするために、例えば特開昭59-155994公報記載の印刷
配線板の製造方法など、様々な技術が提案されている。
2. Description of the Related Art In recent years, with the miniaturization of electronic devices, wiring boards used for them have also been required to be smaller, denser, lighter, and more reliable. There is an increasing demand for miniaturization and high reliability of through holes and via holes. Of these, for the wiring width and wiring gap, photosensitive etching resists and etching solutions have been developed, and in order to reduce the thickness of conductive foils and insulating layers, for example, a method of manufacturing a printed wiring board described in JP-A-59-155994 Various technologies have been proposed.

【0003】また、電子機器に使用されるスイッチング
電源として、DC/DCコンバータおよびインバータな
どの軽薄短小化が進展しており、これらスイッチング電
源DC/DCコンバータおよびインバータなどには半導
体チップが搭載されていて、この半導体チップから発生
する多量の熱を放熱するために従来からアルミコア基板
などの金属コア基板が用いられている。
In addition, as switching power supplies used in electronic equipment, DC / DC converters, inverters, and the like have become lighter and smaller, and these switching power supply DC / DC converters and inverters have semiconductor chips mounted thereon. Conventionally, a metal core substrate such as an aluminum core substrate has been used to radiate a large amount of heat generated from the semiconductor chip.

【0004】このような金属コア基板を用いた金属コア
銅張積層板としては、従来、片面使用のプリント配線板
が一般的に用いられている。また、両面を使用する場合
としてはノンスルーホールプリント配線板が考えられ
る。
As a metal core copper-clad laminate using such a metal core substrate, a single-sided printed wiring board has been generally used. When using both sides, a non-through-hole printed wiring board is conceivable.

【0005】例えば、両面スルーホールの場合は、コア
となる金属板に対し、スルーホール形成部分に予め穴を
加工し、その後、その金属板の両面にプリプレグを介し
て銅箔を熱プレスにて積層することにより両面銅張積層
板を形成する。これにより金属板に加工された穴内にプ
リプレグが充填される。次に、プリプレグが充填された
穴の中央に予め加工した穴に比べて小さい径の穴を加工
し、その穴内および銅箔面全体に銅メッキを施し、その
後に外層銅箔をエッチングして外層回路を形成すること
により金属コア多層配線板が完成される。
[0005] For example, in the case of a double-sided through hole, a hole is previously formed in a portion where a through hole is formed in a metal plate serving as a core, and then a copper foil is hot-pressed on both surfaces of the metal plate via a prepreg. By laminating, a double-sided copper-clad laminate is formed. As a result, the prepreg is filled in the holes formed in the metal plate. Next, in the center of the hole filled with the prepreg, a hole having a smaller diameter than the hole processed in advance is machined, copper plating is performed in the hole and the entire copper foil surface, and then the outer layer copper foil is etched and the outer layer is etched. The metal core multilayer wiring board is completed by forming the circuit.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、前記従
来の金属コア配線板は熱膨張係数が大きく、配線板に搭
載する半導体素子との熱膨張係数差が大きいためにベア
チップ実装の信頼性がなく、高密度実装ができないとい
う問題がある。
However, the conventional metal core wiring board has a large thermal expansion coefficient and a large difference in thermal expansion coefficient from the semiconductor element mounted on the wiring board, so that the reliability of bare chip mounting is not high. There is a problem that high-density mounting cannot be performed.

【0007】よって本発明は上記事情を考慮してなされ
たものであり、低熱膨張係数を有する金属コア多層配線
板の提供を目的とする。
The present invention has been made in view of the above circumstances, and has as its object to provide a metal core multilayer wiring board having a low coefficient of thermal expansion.

【0008】[0008]

【課題を解決するための手段】本発明は、上記目的を達
成するために、金属コアを有する配線基板において、該
金属コアが低熱膨張係数の金属材料よりなるものであ
る。
According to the present invention, there is provided a wiring board having a metal core, wherein the metal core is made of a metal material having a low thermal expansion coefficient.

【0009】より具体的には、片面または両面に回路を
形成した金属コア銅張積層板の片面または両面に対し、
銅箔面に絶縁層を形成した銅張絶縁シートをラミネート
することにより外層を形成し、前記銅張絶縁シートの所
要部分の銅箔をエッチング除去するとともに、所定部分
の絶縁層を除去しビアホールを形成して導通を得ること
により形成した金属コア銅張積層板において、前記金属
コアが低熱膨張係数の金属材料よりなる金属コア多層配
線板である。また、低熱膨張係数を有する金属コア材料
としては、酸化銅を複合した銅材料、もしくは、鉄−ニ
ッケル合金の両面に前記酸化銅を複合した銅材料を積層
接着して形成したクラッド材からなる金属コア多層配線
板である。
More specifically, one side or both sides of a metal core copper-clad laminate having a circuit formed on one or both sides,
An outer layer is formed by laminating a copper-clad insulating sheet having an insulating layer formed on a copper foil surface, and a predetermined portion of the copper-clad insulating sheet is etched and removed, and a predetermined portion of the insulating layer is removed to form a via hole. In the metal core copper-clad laminate formed by forming and obtaining conduction, the metal core is a metal core multilayer wiring board made of a metal material having a low coefficient of thermal expansion. Further, as the metal core material having a low coefficient of thermal expansion, a copper material compounded with copper oxide, or a metal formed of a clad material formed by laminating and bonding the copper material compounded with copper oxide on both surfaces of an iron-nickel alloy It is a core multilayer wiring board.

【0010】本発明では、金属コアが低熱膨張係数の金
属材料よりなるため、金属コア多層配線板の熱膨張係数
を低減できるとともに、前記金属コアの金属コア多層配
線板に占める割合を制御することにより金属コア多層配
線板の熱膨張係数を任意に設定しうるため、従来の金属
コア配線板では困難であったベアチップ実装の信頼性が
得られ、高密度実装が可能となる。
In the present invention, since the metal core is made of a metal material having a low coefficient of thermal expansion, the coefficient of thermal expansion of the metal core multilayer wiring board can be reduced, and the ratio of the metal core to the metal core multilayer wiring board can be controlled. Thus, the coefficient of thermal expansion of the metal core multilayer wiring board can be set arbitrarily, so that the reliability of bare chip mounting, which was difficult with the conventional metal core wiring board, is obtained, and high-density mounting is possible.

【0011】[0011]

【発明の実施の形態】以下、本発明の実施例について説
明する。なお、本発明は、これらの実施例に限定される
ものではない。また、以下の実施例は、内層に回路を有
する多層配線板に関するものであるが、本発明は、両面
に銅箔を有する銅張積層板や、片面のみに回路を有する
片面配線板などの製造にも適用しうる。
Embodiments of the present invention will be described below. Note that the present invention is not limited to these examples. Although the following examples relate to a multilayer wiring board having a circuit in an inner layer, the present invention relates to the manufacture of a copper-clad laminate having copper foil on both sides, a single-sided wiring board having a circuit on only one side, and the like. It can also be applied to

【0012】<実施例1>本実施例における多層配線基
板の製造工程を図1に示す。
Embodiment 1 FIG. 1 shows a manufacturing process of a multilayer wiring board in this embodiment.

【0013】まず、所定の位置にスルーホールをエッチ
ング処理により形成したメタルコア基板1の表裏両面
に、厚さ約18μmの銅箔2と80μm厚程度の絶縁樹脂層3
(エポキシ系))とを積層させた樹脂付き銅箔11を積
層接着し、積層体12を得た(図1(a))。
First, a copper foil 2 having a thickness of about 18 μm and an insulating resin layer 3 having a thickness of about 80 μm are formed on both sides of a metal core substrate 1 having through holes formed at predetermined positions by etching.
(Epoxy-based)) and a resin-coated copper foil 11 were laminated and bonded to obtain a laminate 12 (FIG. 1A).

【0014】次に多層積層板上の配線およびランド部と
なる部分にエッチングレジスト7(エッチングレジスト
JSR製FDR-2500)をラミネートし、パターンを焼き付
け、現像し、不要の銅箔を塩化第二鉄により除去し、第
1層配線4を形成した後、所定の位置に炭酸ガスレーザ
を照射して,その照射箇所の絶縁樹脂層を溶解・気化・
分解し、貫通孔5を形成した。次に、貫通孔5の内壁に
対して、過マンガン酸カリウム法による樹脂残さ除去処
理を行った後、無電解銅めっき用触媒に浸漬し、積層体
12の表面全体および貫通孔5の内壁にめっき触媒6を
付着させた(図1(b))。なお、触媒液には、アルカ
リ性パラジウム触媒を用いた。市販されている触媒液と
しては、アトテック製アクチベーターネオガント834を
挙げることができる。
Next, an etching resist 7 (etching resist)
After laminating JSR FDR-2500), baking and developing the pattern, removing unnecessary copper foil with ferric chloride, forming the first layer wiring 4, and irradiating a predetermined position with a carbon dioxide laser. , Dissolve / vaporize the insulating resin layer
It was decomposed to form a through hole 5. Next, after performing a resin residue removal treatment on the inner wall of the through hole 5 by the potassium permanganate method, the inner wall of the through hole 5 is immersed in a catalyst for electroless copper plating. The plating catalyst 6 was attached (FIG. 1 (b)). Note that an alkaline palladium catalyst was used as the catalyst liquid. Activator Neogant 834 manufactured by Atotech can be mentioned as a commercially available catalyst liquid.

【0015】続いて多層積層板上の配線およびランド部
となる部分にエッチングレジスト7(エッチングレジス
トJSR製FDR-2500)をラミネートし(図1(c))、パ
ターンを焼き付け、現像し、不要の銅箔を塩化第二鉄に
より除去すると共に、当該箇所の銅上に付着しためっき
触媒6も除去した。このとき使用するエッチングレジス
トやエッチング液は市販されているものでよい。エッチ
ングレジストJSR製FDR-2500は高解像度であり、これを
用いた場合、配線幅・配線間隔は共に25μm以下にまで
細線化することができる。
Subsequently, an etching resist 7 (FDR-2500 manufactured by etching resist JSR) is laminated on portions of the multilayer laminated board which will be the wirings and lands (FIG. 1C), and the pattern is baked, developed and unnecessary. The copper foil was removed with ferric chloride, and the plating catalyst 6 adhering to the copper at that location was also removed. The etching resist and the etching solution used at this time may be commercially available. The etching resist JDR FDR-2500 has a high resolution, and when it is used, both the wiring width and the wiring interval can be reduced to 25 μm or less.

【0016】次いで、厚膜無電解銅めっきにより銅めっ
き膜8を析出させて、表面の第1層配線4と裏面の第1
層配線4′とを導通可能に接続するビアホールを形成す
ると同時に、配線パターンおよびランド部の銅箔厚を増
加させた。続いて、エッチングレジスト7を剥離した
(図1(d))。さらに、上記の工程を繰り返し、第2
層配線10を形成するとともに、第1層配線4と第2層
配線10とを導通可能に接続するビアホールを形成した
後、所望部にソルダレジスト9(タムラ製作所製USR-2G
FA-58-300)を形成した(図1(e))。これにより、
層間接続のためのビアホールを有する多層配線基板13
を得ることができた。
Next, a copper plating film 8 is deposited by thick-film electroless copper plating, and the first layer wiring 4 on the front surface and the first layer wiring 4 on the back surface are deposited.
At the same time as forming a via hole for connecting the layer wiring 4 'so as to be conductive, the thickness of the wiring pattern and the copper foil of the land were increased. Subsequently, the etching resist 7 was removed (FIG. 1D). Further, the above steps are repeated, and the second
After forming the layer wiring 10 and forming a via hole for connecting the first layer wiring 4 and the second layer wiring 10 in a conductive manner, a solder resist 9 (USR-2G manufactured by Tamura Seisakusho) is formed in a desired portion.
FA-58-300) (FIG. 1 (e)). This allows
Multilayer wiring board 13 having via holes for interlayer connection
Could be obtained.

【0017】本実施例により作製された多層配線基板1
3は、金属コアに酸化銅と銅の複合材料を用いた場合に
は、熱膨張係数が10μm/m・℃と低減でき、金属コ
アに鉄−ニッケル合金の両面に酸化銅と銅の複合材料を
積層接着して形成したクラッド材を用いた場合には、熱
膨張係数が6μm/m・℃と非常に低減できた。また、
さらに金属コアに形成したスルーホールに複数個の貫通
孔を形成することができることにより高密度配線を実現
できた。さらに無電解銅めっき工程の前に不要箇所の触
媒を除去したため、配線間隙において高い絶縁信頼性を
示し該孔部において良好な電気接続がなされていた。ま
た、この多層配線基板13に半導体素子を搭載し、樹脂
封止して樹脂封止型半導体装置を作製したところ、いず
れの場合おいても接続信頼性に優れた良好な製品を得る
ことができた。
The multilayer wiring board 1 manufactured according to this embodiment
No. 3 shows that when a composite material of copper oxide and copper is used for the metal core, the thermal expansion coefficient can be reduced to 10 μm / m · ° C., and the composite material of copper oxide and copper is formed on both surfaces of the iron-nickel alloy in the metal core. When a clad material formed by laminating and bonding was used, the coefficient of thermal expansion was extremely reduced to 6 μm / m · ° C. Also,
Further, a plurality of through holes can be formed in the through holes formed in the metal core, thereby realizing high-density wiring. Further, since the catalyst at an unnecessary portion was removed before the electroless copper plating step, high insulation reliability was exhibited in the wiring gap, and good electrical connection was made in the hole. In addition, when a semiconductor element is mounted on the multilayer wiring board 13 and sealed with a resin to produce a resin-sealed semiconductor device, a good product having excellent connection reliability can be obtained in any case. Was.

【0018】<実施例2>本実施例では、図2に示すよ
うに、ソルダレジストの塗布と、無電解めっきとの処理
順を逆にした以外は、実施例1と同様の手順で多層配線
基板を作製した(図2(a)〜(c))。
<Embodiment 2> In this embodiment, as shown in FIG. 2, multi-layer wiring is performed in the same procedure as in Embodiment 1 except that the processing order of solder resist coating and electroless plating is reversed. A substrate was produced (FIGS. 2A to 2C).

【0019】本実施例では、実施例1と同様にして第1
層配線4を形成し、エッチング箇所の銅上に付着した触
媒6も除去した後、所定箇所にソルダレジスト9を塗布
した(図2(d))。次に、無電解銅めっきにより銅め
っき膜8を析出させることによりビアホールを形成する
と共に配線パターン厚を増加させた(図2(e))。
In the present embodiment, the first
After the layer wiring 4 was formed and the catalyst 6 attached to the copper at the etching location was also removed, a solder resist 9 was applied to a predetermined location (FIG. 2D). Next, a via hole was formed by depositing a copper plating film 8 by electroless copper plating, and the wiring pattern thickness was increased (FIG. 2E).

【0020】この製造方法によると無電解銅めっき工程
において、ソルダレジスト9により配線間隙部とめっき
液との接触を完全に遮断し、かつ、配線パターン部にお
けるめっきの成長方向を限定することができる。本実施
例では、実施例1よりもさらに導体配線間の電気絶縁信
頼性に優れた多層配線基板14を得ることができた。な
お、そのコストや配線密度については、実施例1と同様
であった。
According to this manufacturing method, in the electroless copper plating step, the contact between the wiring gap and the plating solution can be completely cut off by the solder resist 9 and the plating growth direction in the wiring pattern can be limited. . In this embodiment, a multilayer wiring board 14 having more excellent electrical insulation reliability between the conductor wirings than in the first embodiment was obtained. The cost and the wiring density were the same as in the first embodiment.

【0021】<実施例3>本実施例では、貫通孔5の内
壁に対して、過マンガン酸カリウム法による樹脂残さ除
去処理を行う代わりに、サンドブラスト法により樹脂残
さ除去処理を行った以外は、実施例1および実施例2と
同様にして多層配線基板を作製した。
<Embodiment 3> In this embodiment, a resin residue removal treatment is performed on the inner wall of the through hole 5 by a sand blast method instead of a resin residue removal treatment by a potassium permanganate method. A multilayer wiring board was manufactured in the same manner as in Example 1 and Example 2.

【0022】本実施例では、汎用装置であるサンドブラ
スト装置を樹脂除去処理工程に用いたため、実施例1お
よび実施例2に比べてさらに低コストで多層配線基板を
得ることができた。得られた多層配線基板は、上記実施
例と同様の高密度配線を有し、配線間隔における高い絶
縁信頼性や該孔部における良好な電気接続信頼性を示し
た。
In this embodiment, a multi-layered wiring board can be obtained at a lower cost than in the first and second embodiments because a sandblasting device, which is a general-purpose device, is used in the resin removing step. The obtained multilayer wiring board had the same high-density wiring as in the above example, and exhibited high insulation reliability at wiring intervals and good electrical connection reliability at the hole.

【0023】<実施例4>本実施例では、貫通孔5に導
電性樹脂ペーストをスクリーン印刷法により充填し、表
面の第1層配線4と裏面の第1層配線4′及び第1層配
線4と第2層配線10との接続を形成した以外は、実施
例1乃至実施例3と同様にして多層配線基板を作製し
た。
<Embodiment 4> In this embodiment, a conductive resin paste is filled into the through holes 5 by screen printing, and the first layer wiring 4 on the front surface, the first layer wiring 4 'on the rear surface, and the first layer wiring are formed. A multilayer wiring board was manufactured in the same manner as in Examples 1 to 3, except that the connection between the wiring 4 and the second layer wiring 10 was formed.

【0024】本実施例では、汎用装置であるスクリーン
印刷装置を層間接続工程に用いたため、実施例1乃至実
施例3に比べてさらに低コストで多層配線基板を得るこ
とができた。得られた多層配線基板は、上記実施例と同
様の高密度配線を有し、配線間隔における高い絶縁信頼
性や該孔部における良好な電気接続信頼性を示した。
In this embodiment, since a screen printing device, which is a general-purpose device, is used in the interlayer connection step, a multilayer wiring board can be obtained at a lower cost than in the first to third embodiments. The obtained multilayer wiring board had the same high-density wiring as in the above example, and exhibited high insulation reliability at wiring intervals and good electrical connection reliability at the hole.

【0025】以上の実施例に示した金属コア多層配線板
によれば、片面または両面に回路を形成した金属コア銅
張積層板の片面または両面に対し、銅箔面に絶縁層を形
成した銅張絶縁シートをラミネートすることにより外層
を形成し、前記銅張絶縁シートの所要部分の銅箔をエッ
チング除去するとともに、所定部分の絶縁層を除去しビ
アホールを形成して導通を得ることにより形成した金属
コア銅張積層板において、前記金属コアに低熱膨張係数
の金属材料(酸化銅を複合した銅材料、もしくは、鉄−
ニッケル合金の両面に前記酸化銅を複合した銅材料を積
層接着して形成したクラッド材)を用いることにより金
属コア多層配線板の熱膨張係数を低減できるとともに、
前記金属コアの金属コア多層配線板に占める割合を制御
することにより金属コア多層配線板の熱膨張係数を任意
に設定しうるため、従来の金属コア配線板では困難であ
ったベアチップ実装の信頼性が得られ、高密度実装が実
現できた。
According to the metal core multilayer wiring board shown in the above embodiment, a copper core having an insulating layer formed on a copper foil surface is provided on one or both sides of a metal core copper clad laminate having a circuit formed on one or both surfaces. An outer layer was formed by laminating a clad insulating sheet, and a copper foil of a required portion of the copper-clad insulating sheet was removed by etching, and a predetermined portion of the insulating layer was removed to form a via hole, thereby obtaining conductivity. In the metal core copper-clad laminate, a metal material having a low coefficient of thermal expansion (a copper material compounded with copper oxide, or
The thermal expansion coefficient of the metal core multilayer wiring board can be reduced by using a clad material formed by laminating and bonding a copper material composite of the copper oxide on both surfaces of a nickel alloy,
By controlling the ratio of the metal core to the metal core multilayer wiring board, the coefficient of thermal expansion of the metal core multilayer wiring board can be set arbitrarily. And high-density mounting was achieved.

【0026】[0026]

【発明の効果】本発明によれば、ベアチップ実装の信頼
性を向上させることが可能となる。
According to the present invention, the reliability of bare chip mounting can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1における金属コア多層配線板
の製造工程を示す説明図である。
FIG. 1 is an explanatory view showing a manufacturing process of a metal core multilayer wiring board in Example 1 of the present invention.

【図2】本発明の実施例2における金属コア多層配線板
の製造工程を示す説明図である。
FIG. 2 is an explanatory view showing a manufacturing process of a metal core multilayer wiring board in Embodiment 2 of the present invention.

【符号の説明】[Explanation of symbols]

1…金属コア基板 2…銅箔 3…絶縁樹脂層 4…表面の第1層配線 4′…裏面の第1層配線 5…貫通孔(レーザ加工) 6…めっき触媒 7…エッチングレジスト 8…無電解銅めっき膜 9…ソルダレジスト 10…第2層配線 11…樹脂付き銅箔 12…積層体 13…多層配線板 14…多層配線板 DESCRIPTION OF SYMBOLS 1 ... Metal core board 2 ... Copper foil 3 ... Insulating resin layer 4 ... First layer wiring on the front surface 4 '... First layer wiring on the back surface 5 ... Through-hole (laser processing) 6 ... Plating catalyst 7 ... Etching resist 8 ... None Electrolytic copper plating film 9 ... Solder resist 10 ... Second layer wiring 11 ... Copper foil with resin 12 ... Laminated body 13 ... Multilayer wiring board 14 ... Multilayer wiring board

───────────────────────────────────────────────────── フロントページの続き (72)発明者 長谷部 健彦 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 鈴木 清光 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 Fターム(参考) 5E315 AA05 AA11 BB01 BB04 BB05 BB06 BB14 GG07  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takehiko Hasebe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Research Laboratory (72) Inventor Kiyomitsu Suzuki 7-1-1 Omikacho, Hitachi City, Ibaraki Prefecture No. 1 F-term in Hitachi Research Laboratory, Hitachi, Ltd. (Reference) 5E315 AA05 AA11 BB01 BB04 BB05 BB06 BB14 GG07

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】金属コアを有する配線基板において、該金
属コアが低熱膨張係数の金属材料よりなることを特徴と
する配線基板。
1. A wiring board having a metal core, wherein the metal core is made of a metal material having a low coefficient of thermal expansion.
【請求項2】前記金属コアは、酸化銅を複合した銅材料
からなることを特徴とする請求項1記載の配線基板。
2. The wiring board according to claim 1, wherein said metal core is made of a copper material in which copper oxide is compounded.
【請求項3】前記金属コアは、鉄−ニッケル合金の両面
に酸化銅を複合した銅材料を積層接着して形成したクラ
ッド材からなることを特徴とする請求項1記載の配線基
板。
3. The wiring board according to claim 1, wherein said metal core is made of a clad material formed by laminating and bonding a copper material compounded with copper oxide on both surfaces of an iron-nickel alloy.
JP37267199A 1999-12-28 1999-12-28 Wiring substrate Pending JP2001189536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP37267199A JP2001189536A (en) 1999-12-28 1999-12-28 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP37267199A JP2001189536A (en) 1999-12-28 1999-12-28 Wiring substrate

Publications (1)

Publication Number Publication Date
JP2001189536A true JP2001189536A (en) 2001-07-10

Family

ID=18500855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP37267199A Pending JP2001189536A (en) 1999-12-28 1999-12-28 Wiring substrate

Country Status (1)

Country Link
JP (1) JP2001189536A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095623B2 (en) 2002-05-27 2006-08-22 Hitachi, Ltd. Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus
JP2009152535A (en) * 2007-12-18 2009-07-09 Samsung Electro Mech Co Ltd Method of manufacturing semiconductor package, and semiconductor plastic package using the same
KR101092587B1 (en) * 2009-11-25 2011-12-13 삼성전기주식회사 Core substrate and method of manufacturing core substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095623B2 (en) 2002-05-27 2006-08-22 Hitachi, Ltd. Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus
US7170012B2 (en) 2002-05-27 2007-01-30 Hitachi, Ltd. Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus
JP2009152535A (en) * 2007-12-18 2009-07-09 Samsung Electro Mech Co Ltd Method of manufacturing semiconductor package, and semiconductor plastic package using the same
KR101092587B1 (en) * 2009-11-25 2011-12-13 삼성전기주식회사 Core substrate and method of manufacturing core substrate

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