JPS6339119B2 - - Google Patents

Info

Publication number
JPS6339119B2
JPS6339119B2 JP57217288A JP21728882A JPS6339119B2 JP S6339119 B2 JPS6339119 B2 JP S6339119B2 JP 57217288 A JP57217288 A JP 57217288A JP 21728882 A JP21728882 A JP 21728882A JP S6339119 B2 JPS6339119 B2 JP S6339119B2
Authority
JP
Japan
Prior art keywords
holes
hole
resistant
thin film
copper foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57217288A
Other languages
Japanese (ja)
Other versions
JPS59106191A (en
Inventor
Sukeo Kai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP21728882A priority Critical patent/JPS59106191A/en
Publication of JPS59106191A publication Critical patent/JPS59106191A/en
Publication of JPS6339119B2 publication Critical patent/JPS6339119B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 この発明は配線基板の製造方法に関し、特には
スルーホールを有する配線基板の製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a wiring board, and particularly to a method of manufacturing a wiring board having through holes.

今日、配線基板は電子部品の高密度実装という
観点からスルーホールを有する配線基板とするこ
とが多く、それに伴つてスルーホールの導通状態
の信頼性向上が要求されている。信頼性ではCC
−4法と称される製造方法が優れているが量産性
の点で好ましいものではない。そこで、一般には
エツチドフオイル法またはアデイテイブ法と称さ
れる方法によつてスルーホールを有する多くの配
線基板が製造されている。
Today, wiring boards often have through holes from the viewpoint of high-density mounting of electronic components, and accordingly, there is a demand for improved reliability in the conduction state of the through holes. CC for reliability
Although the manufacturing method called the -4 method is excellent, it is not preferable in terms of mass productivity. Therefore, many wiring boards having through holes are manufactured by a method generally called an etched oil method or an additive method.

エツチドフオイル法はまず、両面銅張り積層板
の所望の位置にスルーホール用の透孔部を穿設す
る。次いで穿設した孔の側面に表面活性化の処理
をおこなつて、銅の無電解メツキを行う。続いて
銅張り表面上および無電解メツキが施された孔の
側面を電気メツキによつてメツキ銅を析出、成長
させていく。そして、銅張り表面上のメツキ銅上
の配線部にレジスト膜でマスキングし、最後にエ
ツチング液で非マスク部を取り除き、スルーホー
ルを有する所望の配線基板を得る。
In the etched oil method, first, holes for through holes are bored at desired positions in a double-sided copper-clad laminate. Next, the side surfaces of the drilled holes are subjected to surface activation treatment, and electroless copper plating is performed. Next, plating copper is deposited and grown on the copper-plated surface and the side surfaces of the holes that have been electrolessly plated by electroplating. Then, the wiring portions on the plated copper on the copper-plated surface are masked with a resist film, and finally the unmasked portions are removed with an etching solution to obtain a desired wiring board having through holes.

アデイーテイブ法はプラスチツク基板にスルー
ホール用の透孔部を穿設し、孔の側面を含む基板
全面に無電解メツキを行い、次いで所望のパター
ンメツキレジスト膜を形成し、最後にメツキレジ
ストを除去してスルーホールを有する所望の配線
基板を得る。
The additive method involves drilling holes for through holes in a plastic substrate, applying electroless plating to the entire surface of the substrate including the sides of the holes, then forming a plating resist film in the desired pattern, and finally removing the plating resist. A desired wiring board having through holes is obtained.

しかしながら、この方法によつて製造された基
板は配線に必要な銅箔を全てメツキによつて得る
ため、銅箔と基板との界面に十分な化学的、物理
的吸着力を期待することは出来ない。そのため経
時的にいわゆるパターン剥がれ等が生じ、高品質
の配線基板を生産出来ない欠点がある。一方、エ
ツチドフオイル法と称される製造方法は両面銅張
り積層板を用いるため、パターン剥がれは生じな
いが配線パターンを2層構造にするため使用銅量
が多くてエツチング時間が長くなり、線幅の細か
い高密度なパターンニングが出来ない欠点を有す
る。
However, since all of the copper foil required for wiring in boards manufactured by this method is obtained by plating, it is not possible to expect sufficient chemical and physical adsorption power at the interface between the copper foil and the board. do not have. As a result, so-called pattern peeling occurs over time, making it impossible to produce high-quality wiring boards. On the other hand, the manufacturing method called the etched oil method uses double-sided copper-clad laminates, so pattern peeling does not occur, but since the wiring pattern has a two-layer structure, the amount of copper used is large, the etching time is long, and the line width is It has the disadvantage that fine, high-density patterning is not possible.

そこで本出願人は、先に特願昭第56−116566号
において両面銅張り積層板の利点を保有しつつ、
上記の欠点を除去した第1図のような配線基板の
製造方法を提案した。第1図の製造方法は以下の
通りである。出発基材としては、同図Aに示すよ
うにエポキシ材あるいはフエノール材からなる基
板1の両面上に約35μmの銅箔2が接着された銅
張り積層板を用いる。同図Bの工程で配線部をレ
ジスト膜6でマスキングし、非マスク部をエツチ
ングすると、同図Cに示す配線パターンが得られ
る。次いで、所定の箇所にスルーホール用の透孔
3を穿設すると同図Dのようになる。そして、次
にこの透孔3を除く基板表面を同図Eのように導
電性薄膜の一例である導電性インク7と耐酸若し
くは耐アルカリ薄膜の一例である耐酸若しくは耐
アルカリインク8とでマスキングする。インクに
よるマスキングを施した後、パラジウム等による
活性化処理後無電解メツキを行つて同図Fのよう
に透孔3の側面に薄膜状の導電性層4を形成す
る。なお無電解メツキ工程は導電性インクを印刷
する前あるいは印刷直後に行うようにしてもよ
い。また、導電性インクに代えて導電性フイルム
を用いてもよい。同図Gの工程で導電性インク7
を一方の電極として電気メツキを行い、導電性薄
膜4上に概ね35μm程度のメツキ銅を析出させ
る。最後に、同図Eの工程で積層形成した導電性
インク7および耐酸若しくは耐アルカリインク8
を除去することによつて同図Hのようなスルーホ
ールを有する配線基板が得られる。
Therefore, the present applicant previously proposed in Japanese Patent Application No. 56-116566, while retaining the advantages of double-sided copper-clad laminates,
A method of manufacturing a wiring board as shown in FIG. 1 was proposed, which eliminates the above-mentioned drawbacks. The manufacturing method shown in FIG. 1 is as follows. As the starting substrate, a copper-clad laminate is used, as shown in FIG. 1A, in which copper foil 2 of about 35 μm is adhered on both sides of a substrate 1 made of epoxy or phenol material. By masking the wiring portion with a resist film 6 and etching the unmasked portion in the step shown in FIG. 2B, the wiring pattern shown in FIG. 2C is obtained. Next, holes 3 for through-holes are drilled at predetermined locations, resulting in a structure as shown in figure D. Then, the surface of the substrate excluding the through holes 3 is masked with a conductive ink 7, which is an example of a conductive thin film, and an acid-resistant or alkali-resistant ink 8, which is an example of an acid-resistant or alkali-resistant thin film, as shown in FIG. . After masking with ink, activation treatment with palladium or the like, electroless plating is performed to form a thin film-like conductive layer 4 on the side surface of the through hole 3 as shown in FIG. Note that the electroless plating step may be performed before or immediately after printing the conductive ink. Furthermore, a conductive film may be used instead of the conductive ink. Conductive ink 7 in the process of G in the same figure.
Electroplating is performed using the electrode as one electrode to deposit approximately 35 μm of plated copper on the conductive thin film 4. Finally, conductive ink 7 and acid-resistant or alkali-resistant ink 8 are laminated in the process shown in FIG.
By removing , a wiring board having through-holes as shown in FIG. 2H can be obtained.

しかしながら上記のような製造方法では従来の
製造方法の欠点は解消されるが、第1図Eの工程
のマスキングは一般に精度があまりよくない。導
電性インク7および耐酸、耐アルカリインク8の
マスキングは、通常、印刷等の手段によつて行わ
れるため、その精度1mm程度以下に設定すること
は極めて困難となるからである。同図Eにおいて
導電性インク7を透孔3を除く基板表面全体にマ
スキングするのは、形成した配線パターン間を導
通させて、その導電性インク7を一方のメツキ電
極として電気メツキを行うためである。したがつ
て基板全体の大きさに比して相対的に非常に小さ
いスルーホールのうち、表面および裏面で他の部
分と接続されないリング状パターンを有するスル
ーホールに対しては、導電性インクのマスキング
がせいぜい1〜2mm程度の幅しかないリング状銅
箔パターンを過不足なくカバーするのは非常に困
難で、マスキングが不足した場合には、そのスル
ーホールの透孔3の側面にはメツキ銅が析出しな
くなり、また反対にマスキングがオーバして透孔
3を導電性インク7で覆つてしまうと、透孔3の
側面に対する電気メツキが行えなくなる不都合が
あつた。また、透孔3が導電性インク7によつて
塞がれなくても導電性インク7が透孔3の内部に
少し侵入するだけで、透孔3の側面の電気メツキ
は不完全なものとなる欠点があつた。
However, although the manufacturing method described above overcomes the drawbacks of the conventional manufacturing method, the masking accuracy in the step of FIG. 1E is generally not very good. This is because masking with the conductive ink 7 and the acid-resistant and alkali-resistant ink 8 is usually performed by means such as printing, so it is extremely difficult to set the accuracy to about 1 mm or less. The reason why the conductive ink 7 is masked on the entire surface of the substrate except for the through holes 3 in FIG. be. Therefore, among through holes that are relatively very small compared to the overall size of the board, through holes with ring-shaped patterns that are not connected to other parts on the front and back sides are masked with conductive ink. However, it is extremely difficult to cover a ring-shaped copper foil pattern with a width of only 1 to 2 mm at most, and if the masking is insufficient, the side of the through hole 3 is covered with plated copper. If the deposition ceases or if the masking is excessive and the conductive ink 7 covers the through hole 3, there is a problem that electroplating cannot be performed on the side surface of the through hole 3. Further, even if the through hole 3 is not blocked by the conductive ink 7, the conductive ink 7 will only slightly enter the inside of the through hole 3, and the electroplating on the side surface of the through hole 3 will be incomplete. There was a drawback.

この発明の目的は上記の実情に鑑み、パターン
剥がれを生じず、エツチング時間が短くて高精度
なパターンニングが出来、しかも、導電性薄膜で
マスキングする工程の精度が緩和されて、より生
産能率が向上したスルーホールを有する配線基板
製造方法を提供することにある。
In view of the above-mentioned circumstances, the purpose of this invention is to enable highly accurate patterning without pattern peeling, short etching time, and to reduce the precision of the masking process with a conductive thin film, thereby increasing production efficiency. An object of the present invention is to provide a method for manufacturing a wiring board having improved through holes.

この発明は、要約すると、両面銅張り積層板を
選択的にエツチングして、所望の配線パターンを
形成する工程で、他の部分と接続しない独立のス
ルーホールとすべき透孔部の周囲に、端子状突起
を有するリング状銅箔パターンを形成することを
特徴とする。
To summarize, this invention is a process of selectively etching a double-sided copper-clad laminate to form a desired wiring pattern, in which a through-hole is formed around a through-hole that is to be an independent through-hole that is not connected to other parts. It is characterized by forming a ring-shaped copper foil pattern having terminal-like protrusions.

以下、この発明の実施例を図面を参照して説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

第2図はこの発明に係る配線基板製造方法の要
部を工程順に示すものである。なお、第1図と構
成において同一ないし相当部分には同一符号を付
している。
FIG. 2 shows the main parts of the wiring board manufacturing method according to the present invention in the order of steps. Note that the same or equivalent parts in the configuration as in FIG. 1 are given the same reference numerals.

第2図Aの工程は第1図A,Bの工程に相当す
るものである。エポキシ材あるいはフエノール材
を基板とする35μm両面銅張り積層板の銅箔2上
に、スルーホールとすべき透孔部を含めた配線部
をエポキシ系インクでスクリーン印刷を施し、メ
ツキレジスト膜6a,6bを得る。この場合、他
の部分と接続しない独立のスルーホールとすべき
透孔部を包含したメツキレジスト膜6bは、円形
周囲の一個所に端子状突起6cを設けたレジスト
パターンとする。第2図Bの工程は第1図C,D
の工程に相当するものである。レジスト膜6a,
6bを施した後、エツチング液で非マスク部を取
り除くとエポキシ材あるいはフエノール材の基材
1が露呈する。そして、レジスト膜を施した部分
にはレジスト膜6a,6bと同形の銅箔パターン
2a,2bが形成される。他の部分と接続しない
独立のスルーホールとすべき透孔部を包含した銅
箔パターン2bは円形周囲の一個所に端子状突起
2cを有したものとなる。銅箔パターン2a,2
bを形成した後、スルーホールとすべき部分には
透孔3が穿設される。この段階で他の部分と接続
しない独立の銅箔パターン2bはリング状にな
る。第2図Cの工程は第1図Eの工程に相当する
ものである。銅箔パターン2a,2bに透孔3を
穿設して基板表面の形成がほぼ完成すると、透孔
3の側面の処理に移る。透孔3の側面に電気メツ
キを施して、基板両面を導通させるため、その銅
箔パターン2a,2b間を導電性インク7をスク
リーン印刷手法で印刷する。この印刷は電気メツ
キのとき銅箔パターン2a,2bを一方の電極と
して作用させるため、銅箔パターン間を導通させ
ておく必要があるためである。導電性インク7は
透孔3を除く基板表面全体に印刷されるが、透孔
3の中に導電性インク7が侵入すると電気メツキ
が完全に行われないので、リング状の銅箔パター
ン2a,2bを全体として避けるように施され
る。しかし、他の部分と接続しない独立のスルー
ホールとすべき透孔3を包含したリング状の銅箔
パターン2bは、端子状突起2cによつて導電性
インク7と接触する。このため、第2図Cに示す
ように透孔3の部分を避けて、基板全体を導電性
インク7でマスキングする印刷工程の精度を大幅
に緩和しても、次の電気メツキ工程に影響が無
い。したがつてこの導電性インク7でマスキング
する工程は大幅にスピードアツプできることにな
る。
The process shown in FIG. 2A corresponds to the processes shown in FIGS. 1A and 1B. On the copper foil 2 of a 35 μm double-sided copper-clad laminate with an epoxy material or phenol material as a substrate, wiring parts including through holes to be made into through holes are screen printed with epoxy ink, and a plating resist film 6a, Get 6b. In this case, the plating resist film 6b, which includes a through-hole section that should be an independent through-hole that is not connected to other parts, has a resist pattern in which a terminal-like protrusion 6c is provided at one location around the circle. The process in Figure 2B is shown in Figures 1C and D.
This corresponds to the process of resist film 6a,
After applying 6b, the non-masked portions are removed using an etching solution to expose the base material 1 made of epoxy or phenolic material. Then, copper foil patterns 2a, 2b having the same shape as the resist films 6a, 6b are formed in the portions where the resist film is applied. The copper foil pattern 2b, which includes a through-hole portion which should be an independent through-hole that is not connected to other parts, has a terminal-like protrusion 2c at one location around the circle. Copper foil pattern 2a, 2
After forming b, a through hole 3 is bored in a portion to be a through hole. At this stage, the independent copper foil pattern 2b that is not connected to other parts becomes ring-shaped. The process shown in FIG. 2C corresponds to the process shown in FIG. 1E. When the formation of the substrate surface by forming the through holes 3 in the copper foil patterns 2a and 2b is almost completed, processing of the side surfaces of the through holes 3 is started. The side surfaces of the through holes 3 are electroplated, and conductive ink 7 is printed between the copper foil patterns 2a and 2b by screen printing in order to make both sides of the board conductive. This is because the copper foil patterns 2a and 2b act as one electrode during electroplating, so it is necessary to maintain continuity between the copper foil patterns. The conductive ink 7 is printed on the entire surface of the substrate except for the through holes 3, but if the conductive ink 7 enters the through holes 3, electroplating will not be completed completely, so the ring-shaped copper foil pattern 2a, 2b is avoided as a whole. However, the ring-shaped copper foil pattern 2b that includes the through hole 3, which should be an independent through hole that is not connected to other parts, comes into contact with the conductive ink 7 through the terminal-like protrusion 2c. For this reason, even if the accuracy of the printing process is greatly relaxed, which involves masking the entire board with conductive ink 7 while avoiding the through holes 3 as shown in Figure 2C, it will not affect the next electroplating process. None. Therefore, the process of masking with this conductive ink 7 can be greatly speeded up.

導電性インク7でマスキングを終えると、先に
本出願人が提案した方法と同様の処理を行う。透
先3を除く全面、すなわち、導電性インク7上と
導電性インク7がマスキングされなかつた基材1
上および銅箔パターン2a,2b上とに、耐酸若
しくは耐アルカリインクをマスキングする。そし
て、透孔3の側面に無電解メツキを行つて導電性
薄膜を形成し、導電性インク7によつて導通され
た銅箔パターン2a,2bを一方の電極として電
気メツキを行い、導電性薄膜上に概ね35μm程度
のメツキ銅を析出させる。最後に、積層形成した
導電性インク7および耐酸若しくは耐アルカリイ
ンクを除去することによつてスルーホールを有す
る配線基板が得られる。
After masking with the conductive ink 7, a process similar to the method previously proposed by the applicant is performed. The entire surface of the base material 1 excluding the tip 3, that is, the top of the conductive ink 7 and the base material 1 where the conductive ink 7 is not masked
Acid-resistant or alkali-resistant ink is masked on the top and on the copper foil patterns 2a and 2b. Then, electroless plating is performed on the side surface of the through hole 3 to form a conductive thin film, and electroplating is performed using the copper foil patterns 2a and 2b, which are electrically connected by the conductive ink 7, as one electrode, to form a conductive thin film. Approximately 35 μm of plated copper is deposited on top. Finally, by removing the laminated conductive ink 7 and acid-resistant or alkali-resistant ink, a wiring board having through holes is obtained.

このように、この発明の配線基板製造方法によ
れば、他の部分と接続しない独立のスルーホール
とすべき透孔部の周囲に端子状突起を有するリン
グ状の銅箔パターンを形成するので、導電性イン
ク7でマスキングする工程の精度が大幅に緩和さ
れるとともに、全てのスルーホールに対して確実
な電気メツキを施すことが出来る。したがつて、
導電性インク7でマスキングする工程はスピード
アツプが可能となり、全体として生産能率が向上
する利点を有する。
As described above, according to the wiring board manufacturing method of the present invention, a ring-shaped copper foil pattern having terminal-like protrusions is formed around the through-hole that should be an independent through-hole that is not connected to other parts. The precision of the process of masking with the conductive ink 7 is greatly reduced, and all through holes can be reliably electroplated. Therefore,
The process of masking with the conductive ink 7 can be speeded up, which has the advantage of improving production efficiency as a whole.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の前提となるスルーホールを
有する配線基板の製造方法を工程順に示す図、第
2図はこの発明に係るスルーホールを有する配線
基板製造方法の要部を工程順に示す図である。 1……基材、2……銅箔、2a,2b……リン
グ状の銅箔パターン、2c,6c……端子状突
起、3……透孔、4……銅箔膜、5……メツキ
銅、6……レジスト膜、7……導電性インク、8
……耐酸若しくは耐アルカリインク。
FIG. 1 is a diagram showing in order of steps a method for manufacturing a wiring board having through holes, which is the premise of the present invention, and FIG. be. 1...Base material, 2...Copper foil, 2a, 2b...Ring-shaped copper foil pattern, 2c, 6c...Terminal-like protrusion, 3...Through hole, 4...Copper foil film, 5...Plating Copper, 6... Resist film, 7... Conductive ink, 8
...Acid-resistant or alkali-resistant ink.

Claims (1)

【特許請求の範囲】 1 (a) 両面銅張り積層板を選択的にエツチング
して所望の配線パターンを形成する。 (b) 所定の箇所にスルーホール用の透孔部を穿設
する。 (c) 前記透孔部を除く基板の表面を洗浄または剥
離可能な導電性薄膜と、洗浄または剥離可能な
耐酸若しくは耐アルカリ薄膜とでマスキングす
る。 (d) 無電解メツキにより前記透孔部に導電性層を
形成する。 (e) 前記導電性薄膜を一方の電極として、電気メ
ツキにより前記導電性層上に適当な厚さの金属
箔を形成する。 (f) 前記導電性薄膜と耐酸若しくは耐アルカリ薄
膜とを除去する。 以上の(a)〜(f)の工程を有する配線基板製造方法
において、前記(a)工程で、他の部分と接続しない
独立のスルーホールとすべき透孔部の周囲に端子
状突起を有するリング状銅箔パターンを形成する
ことを特徴とするスルーホールを有する配線基板
製造方法。
[Claims] 1 (a) A double-sided copper-clad laminate is selectively etched to form a desired wiring pattern. (b) Drill holes for through holes at designated locations. (c) Masking the surface of the substrate except for the through holes with a conductive thin film that can be cleaned or peeled off, and an acid-resistant or alkali-resistant thin film that can be washed or peeled off. (d) Forming a conductive layer in the through hole portion by electroless plating. (e) Using the conductive thin film as one electrode, a metal foil of an appropriate thickness is formed on the conductive layer by electroplating. (f) removing the conductive thin film and the acid-resistant or alkali-resistant thin film; In the wiring board manufacturing method having the above steps (a) to (f), in the step (a), a terminal-like protrusion is provided around the through hole that should be an independent through hole that is not connected to other parts. A method for manufacturing a wiring board having through holes, the method comprising forming a ring-shaped copper foil pattern.
JP21728882A 1982-12-10 1982-12-10 Method of producing circuit board with through hole Granted JPS59106191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21728882A JPS59106191A (en) 1982-12-10 1982-12-10 Method of producing circuit board with through hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21728882A JPS59106191A (en) 1982-12-10 1982-12-10 Method of producing circuit board with through hole

Publications (2)

Publication Number Publication Date
JPS59106191A JPS59106191A (en) 1984-06-19
JPS6339119B2 true JPS6339119B2 (en) 1988-08-03

Family

ID=16701783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21728882A Granted JPS59106191A (en) 1982-12-10 1982-12-10 Method of producing circuit board with through hole

Country Status (1)

Country Link
JP (1) JPS59106191A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0450401B2 (en) * 1989-07-11 1992-08-14 Hekisa Purosesu Kk
JPH0525701A (en) * 1991-07-09 1993-02-02 Aavan Raifu:Kk Partial wig and fitting thereof
JPH0681205A (en) * 1992-08-14 1994-03-22 Nippon Sutera Kk Wig and method for fitting wig

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60250289A (en) * 1984-05-25 1985-12-10 Seiko Epson Corp Electronic timepiece

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085872A (en) * 1973-12-03 1975-07-10
JPS5097859A (en) * 1973-12-28 1975-08-04

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5633165Y2 (en) * 1973-02-27 1981-08-06

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085872A (en) * 1973-12-03 1975-07-10
JPS5097859A (en) * 1973-12-28 1975-08-04

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0450401B2 (en) * 1989-07-11 1992-08-14 Hekisa Purosesu Kk
JPH0525701A (en) * 1991-07-09 1993-02-02 Aavan Raifu:Kk Partial wig and fitting thereof
JPH0681205A (en) * 1992-08-14 1994-03-22 Nippon Sutera Kk Wig and method for fitting wig

Also Published As

Publication number Publication date
JPS59106191A (en) 1984-06-19

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