JPH05327184A - Manufacture of board on which electronic components are mounted - Google Patents

Manufacture of board on which electronic components are mounted

Info

Publication number
JPH05327184A
JPH05327184A JP12637392A JP12637392A JPH05327184A JP H05327184 A JPH05327184 A JP H05327184A JP 12637392 A JP12637392 A JP 12637392A JP 12637392 A JP12637392 A JP 12637392A JP H05327184 A JPH05327184 A JP H05327184A
Authority
JP
Japan
Prior art keywords
copper
plating layer
pattern
layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12637392A
Other languages
Japanese (ja)
Inventor
Masanori Kawade
雅徳 川出
Kenro Kimata
賢朗 木俣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP12637392A priority Critical patent/JPH05327184A/en
Publication of JPH05327184A publication Critical patent/JPH05327184A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a method for manufacturing a board on which electronic components are mounted in which reliability of the board can be improved without burr on a conductor pattern. CONSTITUTION:A method for manufacturing a board on which electronic components are mounted comprises the steps of forming a gold-plated layer 8 of Sn, Sn-Pb alloy, Ni, Ni-Au, etc., at least on one copper surface of a copper- clad laminated layer 3, then removing copper of an unnecessary part by etching and forming a conductor pattern 9 and further comprises the steps of forming a dry film 5 when the layer 8 is formed, then forming a pattern-placed layer 6 on the patterned part, and then forming the layer 8 on the layer 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は導体パターンを形成する
ために、エッチングレジストとして銅のエッチング液に
不溶の金属メッキ層を用いた電子部品搭載用基板の製造
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic component mounting board using a metal plating layer insoluble in a copper etching solution as an etching resist for forming a conductor pattern.

【0002】[0002]

【従来の技術】従来、この種の方法で電子部品搭載用基
板を製造する際は、まず、銅張積層板にスルーホール用
の穴あけを行った後、パネル銅メッキを施し、メッキレ
ジストとして感光性のドライフィルムの張り付け及びパ
ターンの焼き付けを行う。次いでエッチングレジストと
してのニッケルメッキ及び金メッキを施した後、前記ド
ライフィルムの剥離を行い、次にエッチングによる導体
パターンの形成を行った後、ソルダレジストを施し、次
に外形加工を行って電子部品搭載用基板を製造してい
た。
2. Description of the Related Art Conventionally, when manufacturing a board for mounting electronic components by this type of method, first, a copper clad laminate is perforated for through holes, and then a panel copper plating is performed, and a plating resist is exposed. A dry film is applied and a pattern is printed. Next, nickel plating and gold plating are applied as etching resists, the dry film is peeled off, the conductor pattern is formed by etching, solder resist is applied, and then external processing is performed to mount electronic components. Was manufacturing a substrate for.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、図4及
び図5に示すように、上記の製造工程を経て製造された
電子部品搭載用基板の導体パターン21の一部、即ち金
メッキ層22及びパネル銅メッキ層23の間に形成され
たニッケルメッキ層24にはヒゲ状のバリ25が発生す
る場合があった。前記ニッケルメッキ層24にバリ25
が発生した場合には、絶縁基材26上で隣接する導体パ
ターン(ニッケルメッキ層24)21のバリ25同士が
接触して短絡するおそれがあり、特に高密度化のための
導体パターン同士が接近している場合に信頼性の面で問
題があった。
However, as shown in FIGS. 4 and 5, a part of the conductor pattern 21 of the electronic component mounting board manufactured through the above manufacturing steps, that is, the gold plating layer 22 and the panel copper. Bearded burrs 25 were sometimes generated on the nickel plating layer 24 formed between the plating layers 23. Burrs 25 on the nickel plating layer 24
In the case of occurrence of the above, burrs 25 of adjacent conductor patterns (nickel plating layer 24) 21 on the insulating base material 26 may come into contact with each other to cause a short circuit. If so, there was a problem in terms of reliability.

【0004】前記バリの発生の原因は、図6に示すよう
に、パネル銅メッキ層23とドライフィルム27との密
着性が不十分である場合に、ニッケル−金メッキの前処
理としての脱脂、酸処理工程で処理液がパネル銅メッキ
層23とドライフィルム27との間に浸入して隙間がで
きる。そして、この状態でニッケルメッキを行うため、
図7に示すように、ニッケルメッキ層24を形成する際
に、ニッケルメッキが前記ドライフィルム27とパネル
銅メッキ層23との間に入り込んでバリ25が発生する
と考えられる。
As shown in FIG. 6, when the adhesion between the panel copper plating layer 23 and the dry film 27 is insufficient, the cause of the burr is degreasing and acid as a pretreatment for nickel-gold plating. In the treatment process, the treatment liquid enters between the panel copper plating layer 23 and the dry film 27 to form a gap. And because nickel plating is performed in this state,
As shown in FIG. 7, it is considered that when the nickel plating layer 24 is formed, the nickel plating enters between the dry film 27 and the panel copper plating layer 23 to generate a burr 25.

【0005】本発明は上記の事情に鑑みてなされたもの
であって、その目的は導体パターンにバリを発生させな
いで電子部品搭載用基板の信頼性の向上を図ることが可
能な電子部品搭載用基板の製造方法を提供することにあ
る。
The present invention has been made in view of the above circumstances, and an object thereof is to mount an electronic component on which a reliability of a substrate for mounting an electronic component can be improved without generating burrs in a conductor pattern. It is to provide a method for manufacturing a substrate.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、本発明では、銅張積層板の少なくとも一方の銅表面
に、Sn,Sn−Pb系,Ni,Ni−Au等の金属メ
ッキからなるエッチングレジストを形成した後、不要部
分の銅をエッチング除去して導体パターンを形成してな
る電子部品搭載用基板の製造方法において、上記エッチ
ングレジストを形成する際のメッキレジストパターンを
形成した後、パターン部分に銅メッキを施し、その銅メ
ッキ層の上にエッチングレジストを形成するようにし
た。
In order to achieve the above object, according to the present invention, at least one copper surface of a copper-clad laminate is plated with a metal such as Sn, Sn-Pb, Ni, Ni-Au. After forming an etching resist that becomes, in the method of manufacturing an electronic component mounting substrate that forms a conductive pattern by etching away unnecessary portions of copper, after forming a plating resist pattern when forming the etching resist, Copper was applied to the pattern portion, and an etching resist was formed on the copper plated layer.

【0007】[0007]

【作用】本発明によれば、エッチングレジストを形成す
る際のメッキレジストパターンが形成された後、パター
ン部分に銅メッキが施こされ、その銅メッキ層の上にエ
ッチングレジストが形成される。
According to the present invention, after the plating resist pattern for forming the etching resist is formed, the pattern portion is plated with copper, and the etching resist is formed on the copper plating layer.

【0008】[0008]

【実施例】以下、本発明を具体化した一実施例を図1〜
図3に基づいて説明する。電子部品搭載用基板を製造す
る際は、まず、絶縁基材1に銅箔2が積層された銅張積
層板3にスルーホール(図示せず)用の穴をあけた後、
無電解メッキを施してパネル銅メッキ層4を形成する
(図1(a))。次いでメッキレジスト用ドライフィル
ム5を熱圧着により前記パネル銅メッキ層4へ張り付け
た後、パターン形成する(図1(b))。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. When manufacturing a board for mounting electronic components, first, a hole for a through hole (not shown) is formed in a copper clad laminate 3 in which a copper foil 2 is laminated on an insulating base material 1, and then,
Electroless plating is applied to form the panel copper plating layer 4 (FIG. 1A). Next, a dry film 5 for a plating resist is attached to the panel copper plating layer 4 by thermocompression bonding, and then a pattern is formed (FIG. 1 (b)).

【0009】次にパターン部分と対応する前記パネル銅
メッキ層4の上に銅メッキを施してパターン銅メッキ層
6を形成する(図1(c))。次いで、パターン銅メッ
キ層6の上にエッチングレジストとしてのニッケルメッ
キ層7及び金メッキ層8を形成する(図2(a))。そ
の後、前記ドライフィルム5を剥離し(図2(b))、
エッチングを行って導体パターン9を形成する(図2
(c))。
Next, copper plating is performed on the panel copper plating layer 4 corresponding to the pattern portion to form a pattern copper plating layer 6 (FIG. 1 (c)). Next, a nickel plating layer 7 and a gold plating layer 8 as etching resists are formed on the patterned copper plating layer 6 (FIG. 2A). Then, the dry film 5 is peeled off (FIG. 2B),
Etching is performed to form the conductor pattern 9 (see FIG. 2).
(C)).

【0010】図2(c)及び図3に示すように、前記の
ようにして形成された導体パターン9は、従来とは異な
りバリは発生しなかった。これは、パネル銅メッキ層4
に対するドライフィルム5の密着が不十分な場合にも、
従来とは異なりニッケルメッキ層7がパネル銅メッキ層
4とドライフィルム5との間の隙間に入り込むことがな
いためである。即ち、パネル銅メッキ層4とドライフィ
ルム5との間に隙間が生じても、パターン銅メッキ6を
形成する際にパネル銅メッキ層4とドライフィルム5と
の間の隙間に入り込んだ部分はエッチング工程で確実に
除去されるため、導体パターン9にバリが発生すること
が確実に防止される。
As shown in FIGS. 2 (c) and 3, the conductor pattern 9 formed as described above did not cause burrs unlike the prior art. This is the panel copper plating layer 4
Even if the dry film 5 does not adhere sufficiently to the
This is because unlike the conventional case, the nickel plating layer 7 does not enter the gap between the panel copper plating layer 4 and the dry film 5. That is, even if a gap is formed between the panel copper plating layer 4 and the dry film 5, the portion that enters the gap between the panel copper plating layer 4 and the dry film 5 when forming the pattern copper plating 6 is etched. Since the conductor pattern 9 is reliably removed in the process, it is possible to surely prevent burrs from being generated in the conductor pattern 9.

【0011】なお、本発明は上記実施例に限定されるも
のではなく、発明の趣旨を逸脱しない範囲で例えば、エ
ッチングレジストとしてのSn−Pb系の半田メッキ層
10に代えてSn系の半田メッキ層としたり、ニッケル
メッキ層7及び金メッキ層8に代えてニッケルメッキ層
7のみでエッチングレジストを形成してもよい。
The present invention is not limited to the above-described embodiments. For example, Sn-Pb-based solder plating layer 10 as an etching resist may be used instead of Sn-Pb-based solder plating layer without departing from the spirit of the invention. The etching resist may be formed as a layer or instead of the nickel plating layer 7 and the gold plating layer 8 only with the nickel plating layer 7.

【0012】[0012]

【発明の効果】以上詳述したように、本発明によれば、
導体パターンのバリの発生を確実に防止でき、電子部品
搭載用基板の信頼性の向上を図ることができるという優
れた効果を奏する。
As described in detail above, according to the present invention,
It is possible to surely prevent burrs from being formed in the conductor pattern and to improve the reliability of the electronic component mounting board.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を具体化した一実施例を示し、電子部品
搭載用基板の製造工程を示す模式断面図である。
FIG. 1 is a schematic cross-sectional view showing an embodiment of the present invention and showing a manufacturing process of a board for mounting electronic components.

【図2】図1に続く電子部品搭載用基板の製造工程を示
す模式断面図である。
FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the electronic component mounting substrate, which is subsequent to FIG.

【図3】導体パターンの状態を示す部分概略斜視図であ
る。
FIG. 3 is a partial schematic perspective view showing a state of a conductor pattern.

【図4】従来のバリが発生した導体パターンを示す部分
概略斜視図である。
FIG. 4 is a partial schematic perspective view showing a conventional conductor pattern having burrs.

【図5】バリが発生した導体パターンを示す模式断面図
である。
FIG. 5 is a schematic cross-sectional view showing a conductor pattern having burrs.

【図6】パネル銅メッキ層にドライフィルムの接着後、
ニッケル−金メッキの前処理としての脱脂、酸処理工程
を行った後の状態を示す模式断面図である。
[Fig. 6] After adhesion of a dry film to the panel copper plating layer,
It is a schematic cross section showing a state after performing degreasing and acid treatment steps as a pretreatment of nickel-gold plating.

【図7】脱脂、酸処理工程を行った後、ニッケルメッキ
層及び金メッキ層を形成した際の状態を示す模式断面図
である。
FIG. 7 is a schematic cross-sectional view showing a state when a nickel plating layer and a gold plating layer are formed after performing a degreasing and acid treatment process.

【符号の説明】[Explanation of symbols]

3…銅張積層板、4…パネル銅メッキ層、5…メッキレ
ジストパターンとしてのドライフィルム、6…銅メッキ
層としてのパターンメッキ層、7エッチングレジストと
してのニッケルメッキ層、8…エッチングレジストとし
ての金メッキ層、9,11…導体パターン、10…エッ
チングレジストとしての半田メッキ層。
3 ... Copper clad laminate, 4 ... Panel copper plating layer, 5 ... Dry film as plating resist pattern, 6 ... Pattern plating layer as copper plating layer, 7 Nickel plating layer as etching resist, 8 ... As etching resist Gold plating layer, 9, 11 ... Conductor pattern, 10 ... Solder plating layer as etching resist.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 銅張積層板の少なくとも一方の銅表面
に、Sn,Sn−Pb系,Ni,Ni−Au等の金属メ
ッキからなるエッチングレジストを形成した後、不要部
分の銅をエッチング除去して導体パターンを形成してな
る電子部品搭載用基板の製造方法において、 上記エッチングレジストを形成する際のメッキレジスト
パターンを形成した後、パターン部分に銅メッキを施
し、その銅メッキ層の上にエッチングレジストを形成す
ることを特徴とする電子部品搭載用基板の製造方法。
1. An etching resist made of metal plating such as Sn, Sn—Pb system, Ni, Ni—Au, etc. is formed on at least one copper surface of a copper clad laminate, and then unnecessary portions of copper are removed by etching. In the method for manufacturing an electronic component mounting substrate having a conductive pattern formed by forming a conductive resist pattern, a plating resist pattern is formed when the etching resist is formed, copper is plated on the pattern portion, and the copper plating layer is etched. A method of manufacturing a substrate for mounting electronic parts, which comprises forming a resist.
JP12637392A 1992-05-19 1992-05-19 Manufacture of board on which electronic components are mounted Pending JPH05327184A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12637392A JPH05327184A (en) 1992-05-19 1992-05-19 Manufacture of board on which electronic components are mounted

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12637392A JPH05327184A (en) 1992-05-19 1992-05-19 Manufacture of board on which electronic components are mounted

Publications (1)

Publication Number Publication Date
JPH05327184A true JPH05327184A (en) 1993-12-10

Family

ID=14933570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12637392A Pending JPH05327184A (en) 1992-05-19 1992-05-19 Manufacture of board on which electronic components are mounted

Country Status (1)

Country Link
JP (1) JPH05327184A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165816A (en) * 2005-11-15 2007-06-28 Mitsui Mining & Smelting Co Ltd Printed wiring board, its manufacturing method, and its using method
WO2011122645A1 (en) * 2010-03-30 2011-10-06 Jx日鉱日石金属株式会社 Copper foil for printed wiring board with excellent etching properties and layered body using same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165816A (en) * 2005-11-15 2007-06-28 Mitsui Mining & Smelting Co Ltd Printed wiring board, its manufacturing method, and its using method
WO2011122645A1 (en) * 2010-03-30 2011-10-06 Jx日鉱日石金属株式会社 Copper foil for printed wiring board with excellent etching properties and layered body using same
JP2011211008A (en) * 2010-03-30 2011-10-20 Jx Nippon Mining & Metals Corp Copper foil for printed wiring board and layered body which have superior etching property

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