JP2002324968A - Method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board in which the thickness of a conductive layer is substantially uniform on the wiring board which has a resin insulation layer; a field via which passes the layer and is formed by filling with plating; and the conductive layer formed thereon by plating. SOLUTION: A method for manufacturing a wiring board comprises: a step of forming a forming electrolytic Cu plating layer 35 with a field via plating agent; a step of thinning the first electrolytic Cu plating layer 35; a step of forming a plating resist layer 41 thereon; the step of forming a second electrolytic Cu plating layer 37 with conformal plating; a step of forming a guard metal layer 45 thereon; a step of removing a plating resist layer 41; the step of removing an unrequired plating layer by etching; and a step of removing a guard metal layer 45.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a wiring board having a resin insulating layer, a via penetrating therethrough, and a conductor layer formed on the resin insulating layer and the via. Further, the present invention relates to a method for manufacturing a wiring board in which a conductive layer is formed by plating and the via is a filled via filled with plating.

[0002]

2. Description of the Related Art Conventionally, there has been known a wiring board in which a substantially plate-shaped resin insulating layer is filled with a filled via penetrating therethrough by plating, and a conductive layer of a predetermined pattern is formed on the filled via by plating. I have. For example, there is a wiring board 101 whose partial enlarged sectional view on the main surface 102 side is shown in FIG.
The wiring substrate 101 includes a substantially plate-shaped core substrate (resin insulating layer) 103 at the center thereof. A first resin insulating layer 105 is stacked on both surfaces of the core substrate 103, and a second resin insulating layer 107 is further stacked thereon. On the second resin insulation layer 107, a solder resist layer (resin insulation layer) 109 is laminated.

A plurality of substantially cylindrical through-hole conductors 111 penetrating the core substrate 103 are formed at predetermined positions. In addition, the first resin insulating layer 105 includes
A plurality of first via-holes 113 penetrating therethrough are formed at predetermined positions, and each first via-hole 113 is filled with a first filled via 115 by plating.
Similarly, a plurality of second via-holes 117 are formed at predetermined positions in the second resin insulating layer 107, and a second filled via 119 is formed in each second via-hole 117. In the solder resist layer 109, a plurality of pad openings 121 penetrating therethrough are formed at predetermined positions.

A first conductor layer 123 having a predetermined pattern such as wiring and pads is formed between the core substrate 103 and the first resin insulation layer 105, and the through-hole conductor 111 of the core substrate 103 and the first resin insulation layer 105 are formed. 105 first filled via 1
15 is connected. Further, a second conductor layer 125 having a predetermined pattern such as a wiring 126 and a pad 124 is also formed between the first resin insulating layer 105 and the second resin insulating layer 107, and the first filled via of the first resin insulating layer 105 is formed. 115 and the second filled via 119 of the second resin insulating layer 107. Further, a third conductor layer 127 having a predetermined pattern such as a wiring and a pad 128 is formed between the second resin insulating layer 107 and the solder resist layer 109, and is connected to the second filled via 119 of the second resin insulating layer 107. are doing.
A part of the pad 128 of the third conductor layer 127 is exposed in the pad opening 121 of the solder resist layer 109 for mounting an electronic component on the wiring board 101.

In such a wiring board 101, the first filled via 115 inside or on the surface of the first resin insulating layer 105.
The second conductor layer 125 is formed as follows. That is, first, the through-hole conductor 111 is formed on the core substrate 103 by a known method, the first conductor layer 123 is formed on the core substrate 103, and the first via-through hole 113 is formed thereon. A substrate 131 on which the first resin insulating layer 105 is formed is prepared (see FIG. 10).

Next, the substrate 131 is subjected to electroless Cu plating to form an electroless Cu plating layer indicated by a bold line in the drawing on the surface of the first resin insulating layer 105 and in the first via hole 113. I do. Then, a plating resist layer 133 having a predetermined pattern is formed on the electroless Cu plating layer.
0). Thereafter, when plating is performed on a portion including the hole, a plating solution having a property that plating grows in the hole rather than outside the hole (hereinafter, in this specification, a plating solution having such a property is also referred to as a plating solution for filled via). Say))
This substrate 131 is subjected to electrolytic Cu plating. Then,
As shown in FIG. 10, the first via-hole 113 is filled with plating to form a first filled via 115, and on the first filled via 115 and on the electroless Cu plating layer of the first resin insulating layer 105. Then, an electrolytic Cu plating layer is formed.

[0007] In order to promote the plating growth inside the holes and suppress the plating growth outside the holes, a leveler (plating inhibitor) such as an N-based polymer compound is usually used in the plating solution for filled vias. include. After the electrolytic Cu plating, the plating resist layer 133 is removed, and the electroless Cu plating layer covered by the plating resist layer 133 is removed by etching, whereby the second conductor layer 125 having a predetermined pattern is formed. Thus, the first filled via 115 and the second conductor layer 125 are formed in the first resin insulating layer 105.

Thereafter, the first resin insulating layer 105 and the second resin
A second resin insulating layer 107 is laminated on the conductor layer 125,
The second filled via 1 is newly added in the same manner as described above.
19 and the third conductor layer 127 are formed. Then, if a solder resist layer 109 having a pad opening 121 is formed on the second resin insulating layer 107 and the third conductor layer 127, the wiring board 101 shown in FIG. 9 is obtained.

[0009]

However, if the first filled via 115 and the second conductor layer 125 are formed using a filled via plating solution, the state of the second conductor layer 125 varies depending on the location in the substrate 131, and the problem arises. Is generated. This is considered to be due to the fact that the current density is uneven in the substrate 131 during electrolytic Cu plating.

[0010] Regarding this problem, the substrate 1 shown in FIG.
More specifically, the wiring 126 to be formed will be described.
In the portion where the arrangement of the pads 124 and the like are rough, that is, in the portion where the pattern of the plating resist layer 133 is rough (the portion on the left side in the figure), the current density becomes high during electrolytic Cu plating, and the leveler in the plating solution is reduced. It is easy to adsorb to this part. Therefore, the first filled via 115 on the left side in FIG.
When L and the vicinity of the pad 124L of the second conductor layer 125 thereon are observed, as shown in a partially enlarged sectional view of FIG. 11, the growth of plating particles is suppressed in the pad 124L, and as a result, the thickness of the plating layer ( The pad 124L, that is, the thickness of the second conductor layer 125) is also relatively thin. Further, as a result of suppressing the growth of the plating particles, a region where plating particles having extremely small particle sizes such as 0.1 μm or less may be unevenly distributed may be generated.

On the other hand, a portion where the arrangement of the wiring 126 and the pad 124 becomes dense, that is, the plating resist layer 133
The part where the pattern is dense (the right part in the figure) is the electrolytic C
The current density during u plating is low, and it is difficult to adsorb levelers in the plating solution. Therefore, when observing the vicinity of the wiring 126R of the second conductor layer 125 on the right side in FIG.
As shown in a partially enlarged sectional view of FIG. 12, the plating particles grow relatively large, and the thickness of the plating layer (the thickness of the wiring 126R, that is, the thickness of the second conductor layer 125) also becomes relatively large.

Further, the plating resist layer 133 has such a property that the leveler is hard to be attracted by looking at only the individual pads 124 and the wirings 126. Therefore, as shown in FIG. 11 and FIG. The plating particles grow relatively large, and the thickness of the plating layer also becomes relatively thick. On the other hand, the portion (central portion) away from the plating resist layer 133 easily absorbs the leveler, so that the growth of plating particles is suppressed and the thickness of the plating layer is relatively thin. As a result, for example, the pad 124L shown in FIG. 11 has a shape in which the peripheral edge portion jumps up from the central portion. Also, the wiring 126R shown in FIG. 12 also has a shape in which both edges thereof jump up from the center.

Further, in the vicinity of a connection point (not shown) of the substrate 131 with the electrode for electrolytic plating, the current density becomes relatively high and the leveler is easily absorbed, so that the growth of plating particles is suppressed. Although the thickness of the plating layer is also relatively thin, the current density is low and the leveler is difficult to adsorb at a location away from the connection point of this electrode, so that plating particles grow and the thickness of the plating layer is relatively thick . As described above, the conductor layer (the second conductor layer 125) becomes thicker or thinner depending on the location, or has a shape that jumps up at the peripheral portion of the pad 124, both edges of the wiring 126, or the like. Causes poor appearance. Further, it is not preferable in terms of electrical characteristics. This can be similarly applied to the third conductor layer 127.

Further, before laminating the second resin insulation layer 107 on the second conductor layer 125 or the like, or before the third conductor layer 1
If the surface of the second conductor layer 125 or the third conductor layer 127 is roughened by etching before the solder resist layer 109 is laminated on the second conductor layer 125, the second conductor layer 125,
Roughness unevenness occurs due to uneven distribution of plating particles on the surface of No. 7, resulting in poor appearance. In addition, for example, 0.1 μm
In a portion where fine plating particles are gathered as described below, a good roughened surface is not formed, and the adhesion strength between the second conductor layer 125 and the second resin insulating layer 107 or the third conductor layer 1
In some cases, the adhesion strength between the solder resist 27 and the solder resist layer 109 may be reduced. In addition, for example, in the peripheral portion of the second conductor layer 125 surrounded by a broken line in FIG. 9 which is raised in a convex shape, the insulation with the third conductor layer 127 formed thereon via the second resin insulation layer 107 is provided. The distance may be so small that an electrical failure such as a short circuit may occur between the upper and lower conductor layers.

The present invention has been made in view of the above situation, and has a resin insulating layer, a filled via penetrating through the resin insulating layer, and a conductive layer having a predetermined pattern formed thereon by plating. It is an object of the present invention to provide a method of manufacturing a wiring board having a conductive layer having a substantially uniform thickness.

[0016]

Means for Solving the Problems, Action and Effect The solution is to provide a resin insulating layer, a filled via formed by plating in a through hole penetrating the resin insulating layer, and a method of forming a via on the resin insulating layer and the filled via. A conductive layer having a predetermined pattern formed by plating on the wiring board, comprising: a resin insulating layer having the through hole; and a resin insulating layer formed in the through hole and on the resin insulating layer. Electrolytic plating layer, of the substrate comprising, on the electroless plating layer, when performing plating on the portion including the hole, subjected to electrolytic plating with a first plating solution in which plating grows in the hole rather than outside the hole, Filling the through holes by plating to form the filled vias, and forming a first electrolytic plating layer on substantially the whole of the filled vias and the electroless plating layer of the resin insulating layer; A degree, a first electroless plating layer thinning step of thinning the first electroless plating layer, thinned the first
A plating resist layer forming step of forming a plating resist layer having a predetermined pattern on the electrolytic plating layer; and forming a plating resist layer on the first electrolytic plating layer exposed from the plating resist layer. A second electroplating step of performing electroplating with a second plating solution in which plating grows to the same degree or more outside the hole to form a second electroplate layer having a predetermined pattern; Forming a guard metal layer of a pattern, forming a guard metal layer, removing the plating resist layer, removing the plating resist layer, and exposing the first electrolytic plating layer using an etchant that does not dissolve the guard metal layer. And a patterning step of etching and removing the electroless plating layer thereunder; removing the guard metal layer to form a second electrolytic plating layer and a first electrolytic plating layer. A guard metal layer removing step of forming a conductive layer of the predetermined pattern consisting of a key layer and the electroless plating layer, a method of manufacturing a wiring board comprising a.

In the present invention, first, the first electrolytic plating layer is formed on the electroless plating layer of the substrate together with the filled via by using the first plating solution in which the plating grows in the hole rather than the outside (see FIG. 1 electroplating step). The first plating solution can efficiently fill the inside of the through-hole with plating by making the growth of plating different from place to place, which is convenient for forming a filled via. Also, in this step, unlike the conventional case, since the plating resist layer is not formed on the substrate, there is no variation in the thickness of the conductor layer such as a difference in thickness or a jump due to a location due to the presence of the plating resist layer.

After the first electrolytic plating step, the first electrolytic plating layer formed on substantially the entire surface is thinned (first electrolytic plating layer thinning step). For example, when the first electrolytic plating layer is thinned by etching, even if the first electrolytic plating layer is partially thickened, such a portion may cause a rapid growth of plating at the time of forming the plating, and a plating particle Is larger, the amount of plating removed by etching is larger than in other parts. Therefore, the thickness of the first electrolytic plating layer does not fluctuate or becomes small, and the thickness becomes substantially uniform. Further, for example, if the first electrolytic plating layer is thinned by mechanical polishing, the thickness of the first electrolytic plating layer can be made substantially uniform even if the thickness of the first electrolytic plating layer varies. Can be.

After the first electrolytic plating layer thinning step, a plating resist layer is formed (plating resist layer forming step), and plating is performed on the thinned first electrolytic plating layer outside the holes to the same extent as in the holes. A second electrolytic plating layer is formed using a second plating solution that grows or plating grows outside the holes rather than inside the holes (second electrolytic plating step). At this time, the plating grows substantially uniformly, so that the second electrolytic plating layer having a uniform thickness can be formed. Therefore, even when the first electrolytic plating layer and the second electrolytic plating layer are viewed together, the thickness is substantially uniform.

After the second electrolytic plating step, a guard metal layer that does not dissolve in the etchant is formed on the second electrolytic plating layer (guard metal layer forming step). Therefore, in the subsequent patterning step, only the first electrolytic plating layer covered with the plating resist layer and the electroless plating layer thereunder can be removed by etching. This is because the portion of the second and first electrolytic plating layers and the electroless plating layer that is covered with the guard metal layer is protected from the etchant. By employing such a method, since the surface of the second electrolytic plating layer in a portion which will later become a conductor layer of a predetermined pattern does not dissolve, it is possible to reliably remove only the unnecessary first electrolytic plating layer and the unnecessary electroless plating layer. it can.

After the patterning step, the guard metal layer is removed to form a conductor pattern having a predetermined pattern (guard metal layer removing step). When the conductor layer is formed in this way,
Since both the first and second electrolytic plating layers have substantially uniform thicknesses, the thickness of the entire conductor layer including the very thin electroless plating layer becomes substantially uniform, and the appearance is improved. In addition, since the patterning is performed while protecting the surface of the second electrolytic plating layer with the guard metal layer, the second
The electroplated layer does not become thin, and therefore the entire conductor layer does not become thin.

The guard metal layer may be any metal layer as long as it is insoluble in the etching solution used in the patterning step. For example, solder, Sn, Ni, Cr
And the like. Of these, Sn
Since the guard metal layer made of / Pb solder or Sn can be easily removed with a nitric acid-based or fluorine-based stripping solution in the guard metal layer removing step, it is preferable to use these metals.

As the etchant used in the patterning step, any etchant may be used as long as it does not dissolve the guard metal layer. The above-mentioned solder and S
n, Ni, Cr, etc. cannot be used, that is,
Since these dissolve metals, the choice of metals used for the guard metal layer is reduced. Therefore, solder or S
It is preferable to use an alkaline etching solution that does not dissolve n, Ni, Cr and the like.

Further, in the above-mentioned method for manufacturing a wiring board, the first electrolytic plating layer thinning step may include the step of:
The total thickness of the electrolytic plating layer and the electroless plating layer is about 3
It is preferable to adopt a method for manufacturing a wiring board in which the first electrolytic plating layer is thinned so as to have a thickness of 10 to 10 μm. More preferably, the total thickness of the first electrolytic plating layer and the electroless plating layer is about 3 to 5 μm.

In the first electrolytic plating layer thinning step,
If the electrolytic plating layer is extremely thin, holes and baldness are likely to be formed in a part of the plating layer (the thinned first electrolytic plating layer and the electroless plating layer thereunder) due to the variation in the thickness. On the other hand, if the first electrolytic plating layer is not too thin, that is, if the first electrolytic plating layer remains thick, it is necessary to consider side etching during patterning, so that the precision of the pattern must be lowered. In contrast,
In the present invention, in the first electrolytic plating layer thinning step, the first
The total thickness of the electrolytic plating layer and the electroless plating layer is about 3
Since the first electrolytic plating layer is thinned so as to have a thickness of at least μm, holes and baldness hardly occur in the plating layer. On the other hand, the total thickness of the first electrolytic plating layer and the electroless plating layer is about 10 μm.
Since the first electrolytic plating layer is thinned so as to be not more than m, side etching during patterning is reduced, and pattern accuracy can be improved. Also,
It is preferable to reduce the thickness of the first electrolytic plating layer so that the total thickness of the first electrolytic plating layer and the electroless plating layer is about 5 μm or less, because the pattern accuracy can be further improved.

Further, in the above-mentioned method for manufacturing a wiring board, in the patterning step, the exposed first electrolytic plating layer and a portion under the first electrolytic plating layer are etched using the etching solution having an etching rate of about 1 to 5 μm / min. It is preferable to use a method for manufacturing a wiring board in which the electroless plating layer is removed by etching.

For example, an alkaline etching solution containing a copper-ammonia complex, which has been widely used, has a high etching rate of about 30 to 45 μm / min. Therefore,
Unnecessary plating layers (the first electrolytic plating layer and the electroless plating layer) are completely removed by etching in a short time.
For this reason, the etching conditions slightly change, such as a slight change in the etching time and a slight change in the concentration of the etchant, so that the portion of the conductor layer that is not protected by the guard metal layer, that is, the conductor layer The degree of digging of the side portions such as the wiring and the pads differs. In addition, an unnecessary plating layer may remain without being completely removed. That is,
It is difficult to control the etching conditions, and the width of the wiring and pads of the conductor layer varies widely.

On the other hand, in the present invention, patterning is performed using an etching solution having an etching rate of about 1 to 5 μm / min. If an etching solution with a low etching rate is used, the etching takes a relatively long time, so that the etching conditions are slightly changed, such as a slight change in the etching time or a slight change in the concentration of the etching solution. Even if it changes, unnecessary plating layers (the first electrolytic plating layer and the electroless plating layer) can be surely removed, and irregularities in the degree of digging (side etching) on the side surfaces of the wiring and pads of the conductor layer. Variation). That is, according to the present invention, a conductor layer having a predetermined shape can be formed more reliably.

As the etchant, it is preferable to use an alkaline etchant containing an organic acid such as formic acid and a complexing agent such as an amine.
This is because such an etchant has a lower etch rate than an etchant containing an ammonia complex or the like.

Further, in the above-described method for manufacturing a wiring board, in the patterning step, the exposed first electrolytic plating layer and the electroless plating layer thereunder may be formed to a thickness of about 0.1 mm.
It is preferable to use a method for manufacturing a wiring board in which etching is removed in 5 to 5 minutes.

As described above, in the patterning step, unnecessary plating layers (first electrolytic plating layer and electroless plating layer) are removed by etching in a short time, specifically, in a time shorter than about 0.5 minute. Even if the etching conditions are slightly changed, the variation in the degree of digging on the side surfaces of the wiring and pads of the conductor layer becomes particularly large. In addition, an unnecessary plating layer may remain without being completely removed. On the other hand, if the etching time is too long, specifically, if it is longer than about 5 minutes, the time required for the patterning step becomes longer, resulting in poor productivity. On the other hand, in the present invention, the exposed unnecessary plating layer is removed by etching in about 0.5 to 5 minutes, so that even if the etching conditions slightly change, the unnecessary plating layer can be reliably removed. In addition, variations in the degree of digging (variations due to side etching) on the side surfaces of the wiring and pads of the conductor layer are reduced. Therefore,
A conductor layer having a predetermined shape can be more reliably formed.
Further, the patterning step can be shortened, and the productivity can be improved.

Further, in the method for manufacturing a wiring board according to any one of the above, a roughening step of etching and roughening the surface of the conductor layer after the guard metal layer removing step is provided. It is preferable to provide a method of manufacturing a wiring board, comprising: an upper insulating layer forming step of forming an upper resin insulating layer on the conductor layer and the resin insulating layer.

Since the plating particles near the surface of the conductor layer before the roughening step (plating particles of the second electrolytic plating layer) have a substantially uniform size, the surface of the conductor layer is etched and roughened in the roughening step. Then, the surface becomes a roughened surface having a substantially uniform roughness. Therefore, when the upper resin insulating layer is formed in the upper insulating layer forming step, there is no uneven adhesion strength between the roughened conductor layer and the upper resin insulating layer.

Further, in the above-described method for manufacturing a wiring board, it is preferable that the second electrolytic plating step includes forming the second electrolytic plating layer made of plated particles having a particle size of about 1 μm or more. good.

If the plating particles of the second electrolytic plating layer in the vicinity of the surface of the conductor layer are extremely small, a roughened surface having a desired roughness cannot be obtained in the roughening step. Adhesion strength may decrease. On the other hand, in the present invention, the particle size of the plating particles of the second electrolytic plating layer forming the vicinity of the surface of the conductor layer is increased to about 1 μm or more. A surface can be formed. Therefore, the adhesion strength between the conductor layer and the upper resin insulation layer can be improved.

Further, in any one of the above-described methods for manufacturing a wiring board, it is preferable that the method further includes an upper conductor layer forming step of forming an upper conductor layer on the upper resin insulating layer.

As described above, the thickness of the conductor layer does not vary and can be made substantially uniform. Therefore, even if an upper insulating layer is formed thereon and an upper conductor layer is further formed thereon, the conventional conductor layer and the upper conductor layer formed with the upper resin insulating layer interposed therebetween have a conventional structure. There is no place where the insulation interval is reduced as described above. Therefore, electrical defects such as a short circuit and a decrease in insulation resistance between these upper and lower conductor layers hardly occur. Further, the electric characteristics are stabilized.

[0038]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a partially enlarged cross-sectional view of the wiring board 1 of the present embodiment on the main surface 2 side. The wiring board 1 has a substantially rectangular substantially plate shape having a main surface 2 and a back surface (not shown), and has a substantially plate-like thickness formed of a composite material obtained by impregnating a glass fiber cloth with an epoxy resin at the center thereof. A core substrate (resin insulating layer) 5 of about 600 μm is provided. A first resin insulating layer 7 made of an epoxy resin or the like is laminated on both surfaces thereof, and
Similarly, a second resin insulation layer 9 made of epoxy resin or the like and having a thickness of about 35 μm is laminated. Also, the second resin insulation layer 9
A solder resist layer (resin insulating layer) 11 made of epoxy resin or the like and having a thickness of about 25 μm is laminated thereon.

The core substrate 5 has a plurality of through-hole conductor through-holes 14 having a diameter of about 250 μm penetrating therethrough at predetermined positions, and the inner peripheral surface thereof has a substantially cylindrical through-hole conductor. 15 are formed respectively. Each through-hole conductor 15 is filled with a substantially cylindrical resin filling material 16 made of epoxy resin or the like. The first resin insulating layer 7 has a diameter of about 7
0 μm, first via hole 1 with height (length) of about 35 μm
8 are formed at predetermined positions, and each first via through hole 1
8, a substantially filled first filled via 19 is filled and formed by Cu plating. Similarly, the second resin insulating layer 9 also has a diameter of about 70 μm and a height of about 35 μ
A plurality of m second via-holes 22 are formed at predetermined positions, and a substantially cylindrical second filled via 23 filled with Cu plating is formed in each second via-hole 22. In the solder resist layer 11, a plurality of pad openings 25 penetrating therethrough are formed at predetermined positions.

A first conductor layer 27 having a predetermined pattern such as wiring and pads is formed between the core substrate 5 and the first resin insulation layer 7, and the through-hole conductor 15 of the core substrate 5 and the first resin insulation layer 7 are formed. 7 is connected to the first filled via 19. A second conductor layer 29 having a predetermined pattern such as a wiring 30 and a pad 28 is also formed between the first resin insulating layer 7 and the second resin insulating layer 9, and the first filled via of the first resin insulating layer 7 is formed. 19 and the second filled via 23 of the second resin insulating layer 9. Further, a third conductor layer 31 having a predetermined pattern such as a wiring 34 and a pad 32 is also formed between the second resin insulating layer 9 and the solder resist layer 11, and the second filled via 23 of the second resin insulating layer 9 is formed. Connected. Some of the pads 32 of the third conductor layer 31 are used to mount electronic components such as IC chips on the wiring board 1.
It is exposed in one pad opening 25. It should be noted that a Ni plating layer is formed on the surface of the pad 32 to prevent oxidation, and an Au plating layer is formed thereon (not shown). The pad opening 25 may be made of, for example, an Sn-Ag solder material, and may be formed with a solder bump (not shown) protruding from the solder resist layer 11.

The first resin insulating layer 7 of the wiring board 1
Filled via 19 and second conductor layer 2 inside and on the surface of
9 will be described in detail with reference to FIGS. FIG.
1 shows the first filled via 19L shown on the left side in FIG. 1 and the vicinity of the pad 28L of the second conductor layer 29 formed thereon. This first filled via 19L is filled with a first via through-hole 18 using a filled via plating solution (first plating solution) having a property that plating grows in the hole rather than outside the hole when the portion including the hole is plated. Is filled with Cu plating. For this reason, plating grows quickly in the first via through hole 18 and the average particle diameter of the plating particles is about 1%.
大 き く 2 μm, which is relatively large, and the particle size distribution is almost uniform.

Pad 2 on first filled via 19L
8L is an electroless C having a thickness of about 0.7 μm indicated by a thick line in the figure.
It has a u plating layer 33 and two electrolytic Cu plating layers.
That is, the first filled via 19 is located below the pad 28L.
On the upper and electroless Cu plating layers 33, there is a first electrolytic Cu plating layer 35 formed by a filled via plating solution as in the case of the first filled via 19L, and a portion including a hole is plated thereon. Sometimes there is a second electrolytic Cu plating layer 37 formed by a conformal plating solution (second plating solution) having a property that plating grows to the same extent or more outside the hole.

Since the first electrolytic Cu plating layer 35 is formed by using a filled via plating solution, the plating growth may vary depending on the location. However, the upper surface 36 is substantially flat after being etched, and has a uniform thickness of about 5 μm. On the other hand, since the second electrolytic Cu plating layer 37 is formed by using a conformal plating solution, the plating particles have a substantially uniform size of about 1 to 2 μm regardless of the location. The distribution is substantially uniform irrespective of the location, and the thickness is also substantially uniform at about 15 μm.

Therefore, even if the pad 28L is viewed as a whole,
Unlike the conventional (see FIG. 11), there is no jumping up,
The thickness is almost uniform and the appearance is good. Specifically, conventionally, when a conductor layer having a thickness of about 20 μm is formed, a difference in thickness of up to about 18 μm has occurred. In the present embodiment, only a difference of up to about 2 μm has occurred. .

If the etching at the time of forming the pad 28L is insufficient, an unnecessary plating layer may remain on the first resin insulating layer 7, but in this wiring board 1, such a plating layer No residue is present. Also, pad 28
The side surface of L may be slightly hollowed out by etching when forming the pad 28L, but has no variation in the shape of the hollowing and has a predetermined shape. The surface of the pad 28L is roughened by etching so that the center line average surface roughness Ra is reduced to about 0.5 μm in order to improve the adhesion strength between the second conductor layer 29 and the second resin insulating layer 9. Moreover, it is evenly roughened.

FIG. 3 shows the vicinity of the wiring 30R of the second conductor layer 29 shown on the right side in FIG. Similar to the pad 28L, the wiring 30R has an electroless Cu plating layer 33 indicated by a thick line in the drawing, a first electrolytic Cu plating layer 35 formed thereon by a filled via plating solution, and a capacitor And a second electrolytic Cu plating layer 37 formed by a formal plating solution.

The first electrolytic Cu plating layer 35 has a substantially flat upper surface 36 etched similarly to the pad 28L, and has a thickness of about 5 μm and is substantially uniform. Also, similarly to the pad 28L, the second electrolytic Cu plating layer 37 of the wiring 30R has a substantially uniform size of plating particles of about 1 to 2 μm irrespective of the location, and has a thickness of about 1 to 2 μm. It is almost uniform at 15 μm. Therefore, unlike the conventional wiring (see FIG. 12), the wiring 30R as a whole has a substantially uniform thickness and a good appearance.

If the etching at the time of forming the wiring 30R is insufficient, an unnecessary plating layer may remain on the first resin insulating layer 7; No residue is present. Further, the side surface of the wiring 30R may be slightly hollowed out by etching when forming the wiring 30R, but the shape of the hollowing does not show any variation and has a predetermined shape. The surface of the wiring 30R is also roughened by etching roughening similarly to the pad 28, and the center line average surface roughness Ra is about 0.5 μm.
Is almost uniform.

Further, in the conventional wiring board 101, the portion where the wirings 126 and the pads 124 and the like are densely arranged has a faster plating growth and the thickness of the plating layer than the portion where the wirings 126 and the pads 124 are coarsely arranged. (FIGS. 11 and 1
2). On the other hand, in the wiring board 1 of the present embodiment,
Like the wiring 30R shown in FIG.
8 and the pad 28L shown in FIG.
The wiring 30 and the pad 28 have a substantially uniform thickness with the rough portion. In addition, the second electrolytic Cu formed thereon
The plating layer 37 also has a substantially uniform thickness. Therefore,
The thickness of the second conductor layer 29 such as the wiring 30 and the pad 28 is substantially uniform regardless of the location. Although detailed description is omitted, the same can be said for the second filled via 23 and the third conductor layer 31 formed in the second resin insulating layer 9 as for the first filled via 19 and the second conductor layer 29 (FIG. 2 and FIG. 3).

Next, a method for manufacturing the wiring board 1 will be described with reference to the drawings. First, a substantially double-sided copper-clad core substrate 5 in which a Cu foil is stretched on both surfaces of the core substrate 5 is prepared, and a plurality of through-hole conductor through holes 14 are formed at predetermined positions (see FIG. 4). Next, by a known method,
A plating layer is formed on substantially the entire surface of both sides of the core substrate 5, and a substantially cylindrical through-hole conductor 15 is formed on the inner peripheral surface of the through-hole conductor through-hole 14. Thereafter, a resin filling material 16 made of epoxy resin or the like is filled and formed in the through-hole conductor 15. Thereafter, an etching resist layer having a predetermined pattern is formed on the plating layer, and the plating layer exposed from the resist layer is removed by etching to form a first conductor layer 27 having a predetermined pattern on the core substrate 5 (FIG. 4). reference).

Next, in the first insulating layer forming step, the first via hole 18 is formed on the core substrate 5 and the first conductor layer 27.
Is formed (see FIG. 4). Specifically, a sheet-shaped uncured resin made of a photosensitive epoxy resin or the like is overlaid on both surfaces of the core substrate 5 and is semi-cured by heat treatment. Then, using a mask of a predetermined pattern,
The semi-cured resin insulating layer is exposed and developed, and is further heated and cured to form the first resin insulating layer 7 having the first via hole 18. The via-holes such as the first via-hole 18 may be formed by laser processing. Next, in the electroless plating step, the electroless Cu plating layer 33 having a thickness of about 0.7 μm is formed on the surface of the first resin insulating layer 7 and in the first via through hole 18 as shown by a thick line in the drawing. Is formed (see FIG. 4).

Next, in a first electrolytic plating step, the substrate 43 is subjected to electrolytic Cu plating, and as shown in FIG.
Plating is formed on the electroless Cu plating layer 33 until the first via-hole 18 is completely filled with plating. In this step, a plated via plating solution (first plating solution) is used in which plating is performed in the hole rather than outside the hole when the portion including the hole is plated. As a result, the first via-through hole 18 is filled with plating to form the first filled via 19 and the first filled via 1
9 and the electroless Cu plating layer 33 on the surface of the first resin insulating layer 7, a first electrolytic Cu plating layer 35 having a thickness of about 12 μm.
Is formed.

In this step, unlike the related art, since the plating resist layer is not formed on the substrate 43, the concentration of levelers (plating inhibitor) in the plating solution caused by the presence of the plating resist layer. Due to the difference in ease,
The thickness of the first electrolytic Cu plating layer 35 does not change depending on the location, or the first electrolytic Cu plating layer 35 does not jump up. However, the first filled via 19
The thickness of the first electrolytic Cu plating layer 35 may be slightly varied, for example, the first electrolytic Cu plating layer 35 may become slightly thicker, for example, because the plating growth is likely to vary in the vicinity of.

Next, in the first electrolytic plating layer thinning step, as shown in FIG. 5, the first electrolytic Cu plating layer 35 is thinned by etching. Specifically, the etching is performed until the thickness of the first electrolytic Cu plating layer 35 becomes about 4 μm. Thereby, the total thickness of the electroless Cu plating layer 33 and the first electrolytic plating layer 35 is about 4.7 μm. If the combined thickness of the first electrolytic plating layer 35 and the electroless plating layer 33 is set to about 3 μm or more, a hole may be formed in a part of the first electrolytic plating layer 35 during processing. The first resin insulating layer 7 as a base is not exposed due to generation of baldness.

In the first electrolytic plating step, the first electrolytic Cu
If the plating layer 35 is formed to have a substantially uniform thickness, the first electrolytic Cu plating layer 35 is substantially uniformly etched to have a substantially uniform thickness. On the other hand, even when the first electrolytic Cu plating layer 35 has a slight change in thickness, the thick portion is etched more than the other portions because the plating particles are large, and as a result, the thickness does not change, Alternatively, the first electrolytic Cu plating layer 35
Has a substantially uniform thickness. The etching solution used in this step is a sulfuric acid-hydrogen peroxide based acidic etching solution.

Next, in a plating resist layer forming step, a plating resist layer 41 having a predetermined pattern is formed on the thinned first electrolytic Cu plating layer 35 (see FIG. 6). In the first electrolytic plating layer thinning step, the plating layers (the first electrolytic Cu plating layer 35 and the electroless Cu plating layer 33) on the first resin insulating layer 7 are left thin without being completely removed. ing. Therefore, it is not necessary to separately form an electroless Cu plating layer on the first resin insulating layer 7 before this plating resist layer forming step, and therefore, the wiring board 1 can be manufactured efficiently.

Next, in a second electrolytic plating step, electrolytic Cu plating is performed, and as shown in FIG. 6, a second electrolytic Cu plating having a predetermined pattern is formed on the first electrolytic Cu plating layer 35 exposed from the plating resist layer 41. The plating layer 37 is formed. At this time, unlike the first electrolytic plating step, the plating solution is a conformal plating solution (a second plating solution) in which when a portion including a hole is plated, plating grows to the same extent or more outside the hole. 2 plating solution). In this step, the second electrolytic Cu plating layer 37 having a thickness of about 15 μm is formed.
Is formed on the first electrolytic Cu plating layer 35. Since the second electrolytic Cu plating layer 37 is formed with a substantially uniform thickness, the first electrolytic Cu plating layer 35 and the second electrolytic Cu plating layer 37 have a substantially uniform thickness when viewed together. .

Next, in the guard metal layer forming step, S
N plating is performed, and a guard metal layer 45 having a predetermined pattern made of Sn, which is insoluble in an etchant described later, is formed on the second electrolytic Cu plating layer 37 as shown in FIG. The thickness of the guard metal layer 45 is about 5 μm. Next, in the plating resist layer removing step, the plating resist layer 4 is removed.
Remove one.

Next, in the patterning step, an etching solution is sprayed onto the substrate, and as shown in FIG. 8, the conductor layer (first electrolytic plating layer 35 and electroless plating Layer 33) is etched away. The etching time is about 3 minutes. Here, an etchant that dissolves Cu but does not dissolve the guard metal layer 45 made of Sn and has an etch rate of about 1 to 5 μm / min is used. For example, Mec Bright SF-
5420 or Mech-etch bond CZ-8500 may be used. These etching solutions are alkaline etching solutions containing an organic acid such as formic acid and a complexing agent such as an amine, and have an etching rate of about 1.5 to 1.5.
It is as low as 3 μm / min, and does not dissolve the guard metal layer 39 made of Sn.

When an etching solution with a low etching rate is used, the exposed conductor layer is etched over a relatively long time, so that the etching time slightly changes or the concentration of the etching solution slightly decreases. Even if the etching conditions change, such as changes, the unnecessary plating layer can be reliably removed, and the patterned conductor layers (the second electrolytic plating layer 37, the first electrolytic plating layer 35, and the electroless plating layer The variation in the degree of gouging on the side surface portion of 33) is reduced. In particular, in the present embodiment, the thickness (about 4.7 μm) of the plating layer (the first electrolytic plating layer 35 and the electroless Cu plating layer 33) to be removed by etching suppresses a decrease in pattern accuracy due to side etching.
It is as thin as about 10 μm or less. However, since the etching rate of the etching solution is as low as about 1 to 5 μm / min, the etching can be performed for a relatively long time. Therefore,
Even if the etching conditions change, unnecessary plating layers can be reliably removed, and variations in the degree of digging (variations due to side etching) on the side surfaces of the patterned conductor layer are reduced. In this embodiment,
In this patterning step, the exposed unnecessary plating layer is removed by etching in about 0.5 to 5 minutes, so that even if the etching conditions slightly change, the unnecessary plating layer can be reliably removed, and Variations in the degree of gouging on the side surfaces of the layer wiring and pads are reduced. on the other hand,
Since a long time is not required for the patterning step, productivity is high.

Next, in a guard metal layer removing step, the guard metal layer 45 is removed by a Mech Remover S-1728 manufactured by Mec Co., Ltd.
7. First electrolytic plating layer 35 and electroless Cu plating layer 33
A second conductor layer 29 having a predetermined pattern is formed (see FIGS. 1 to 3). As described above, both the first electrolytic Cu plating layer 35 and the second electrolytic Cu plating layer 37 have substantially uniform thicknesses. Therefore, the second conductor layer 29 also has a substantially uniform thickness and an appearance. Good.

The wiring and pads of the second conductor layer 29 are reduced in the degree of digging on their side surfaces in the above-described patterning step. Further, since the surface of the second conductor layer 29 is protected from etching by the guard metal layer 45, the thickness of the second conductor layer 29 is also prevented from becoming thin. That is, the second conductor layer 29 can be reliably formed. Also, the guard metal layer 45
Is composed of Sn, so that it can be easily removed with a nitric acid-based or fluorine-based stripping solution as in the above-mentioned Mech Remover S-1728.

Next, in the roughening step, the second conductor layer 29
Is roughened by etching so that its center line average surface roughness Ra is about 0.5 μm (see FIGS. 2 and 3). In this case, the plating particles in the vicinity of the surface of the second conductor layer 29, that is, in the second electrolytic Cu plating layer 37, are large and uniform, about 1 to 2 μm, so that the roughened surface is hardly uneven, and the desired An etched rough surface having a uniform roughness can be obtained.

Next, in the second insulating layer forming step, the first insulating layer is formed.
Similarly to the resin insulating layer forming step, the second resin insulating layer 9 having the second via through-hole 22 is formed on the first resin insulating layer 7 and the second conductor layer 29. At this time, in the above-described roughening step, the surface of the second conductor layer 29 is made to have a substantially uniform roughened surface with a large surface roughness. There is no unevenness in the adhesion strength, and the adhesion strength is increased.

Thereafter, according to the method of forming the first filled via 19 and the second conductor layer 29 in the first resin insulating layer 7,
The second filled via 23 and the third conductor layer 31 are formed in the second resin insulating layer 9. That is, an electroless plating step, a first electrolytic plating step, a first electrolytic plating layer thinning step, a plating resist layer forming step, a second electrolytic plating step, a guard metal layer forming step, a plating resist layer removing step, a patterning step,
The guard metal layer removing step and the roughening step are sequentially performed.

Thereafter, in a solder resist layer forming step, a solder resist layer 11 having a pad opening 25 is formed on the second resin insulating layer 9 and the third conductor layer 31. Specifically, the second resin insulation layer 9 and the third conductor layer 31
A semi-cured solder resist layer is formed thereon, and is exposed and developed using a mask having a predetermined pattern corresponding to the opening. Thereafter, the solder resist layer 11 having a pad opening 25 is formed by further heating and curing.

As described above, the second filled via 23 and the third conductor layer 31 are formed by the first filled via 19 and the second conductor layer 2.
Since it is formed according to the forming method of No. 9, the same effects as those described above can be obtained. Further, the third conductor layer 31
Is formed, the second conductor layer 29 has a substantially uniform thickness and does not have a convex jump. Therefore, the insulation interval between the second conductor layer 29 and the third conductor layer 31 is sufficient over the entire substrate. Is secured. Therefore, electrical failure such as short-circuiting and reduced insulation failure between these upper and lower conductor layers hardly occurs. Further, the electric characteristics are stabilized.

After the formation of the solder resist layer 11,
In the Ni-Au plating step, the solder resist layer 1
The pad 32 and the like exposed from 1 are coated with Ni to prevent oxidation.
A plating layer is formed, and an Au plating layer is further formed thereon. Thus, the wiring board 1 is completed. In addition,
The pads 32 exposed from the solder resist layer 11 include:
The pins may be erected with solder or the like, or solder bumps may be formed.

In the above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments, and it is needless to say that the present invention can be appropriately modified and applied without departing from the gist thereof. Nor. For example, in the above embodiment, in the first electrolytic plating layer thinning step, the first electrolytic Cu plating layer 35 was thinned by etching, but it can be thinned by mechanical polishing. Also in this case, the first electrolytic Cu plating layer 35 can have a uniform thickness, so that the entire second conductor layer 29 can also have a uniform thickness. The same applies to the case where the third conductor layer 31 is formed.

In the above embodiment, the guard metal layer 4
Although a material made of Sn was formed as 5, other metals can be used as long as they do not dissolve in the etching solution. For example, solder such as Sn / Pb, Ni, Cr
For example, a guard metal layer made of such as may be formed.

Any etchant may be used as long as it dissolves the conductor layer and does not dissolve the guard metal layer 45 and has a low etching rate (about 1 to 5 μm / min). However, it is preferable to use an alkali-based etchant in consideration of the selection range of the metal used for the guard metal layer 45. Among them, an alkaline etching solution containing an organic acid and a complexing agent is particularly preferable because of its low etching rate.

[Brief description of the drawings]

FIG. 1 is a partially enlarged cross-sectional view of a wiring board according to an embodiment.

FIG. 2 is a partial enlarged cross-sectional view of a first filled via and a pad of a second conductor layer in the vicinity of a pad in the wiring board according to the embodiment;

FIG. 3 is a partially enlarged cross-sectional view of a wiring board according to an embodiment, in the vicinity of a wiring of a second conductor layer.

FIG. 4 is an explanatory view showing a state after performing electrolytic Cu plating with a first plating solution in the method for manufacturing a wiring board according to the embodiment;

FIG. 5 is an explanatory view showing a state after the first electrolytic Cu plating layer is thinned in the method for manufacturing a wiring board according to the embodiment.

FIG. 6 is an explanatory view showing a state after performing electrolytic Cu plating with a second plating solution in the method of manufacturing a wiring board according to the embodiment.

FIG. 7 is an explanatory view showing a state after a guard metal layer is formed in the method for manufacturing a wiring board according to the embodiment.

FIG. 8 is an explanatory view showing a state after patterning in the method of manufacturing a wiring board according to the embodiment;

FIG. 9 is a partially enlarged cross-sectional view of a wiring board according to the related art.

FIG. 10 relates to a method for manufacturing a wiring board according to the related art.
It is explanatory drawing which shows a mode that the electrolytic Cu plating layer was formed.

FIG. 11 relates to a method for manufacturing a wiring board according to the related art;
FIG. 4 is a partially enlarged cross-sectional view showing the vicinity of pads of a first filled via and a second conductor layer in a substrate having an electrolytic Cu plating layer formed thereon.

FIG. 12 relates to a method for manufacturing a wiring board according to the related art;
FIG. 4 is a partially enlarged cross-sectional view showing the vicinity of a wiring of a second conductor layer in a substrate on which an electrolytic Cu plating layer is formed.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 wiring board 5 core board 7 first resin insulating layer 9 second resin insulating layer 11 solder resist layer (resin insulating layer) 19 first filled via 23 second filled via 27 first conductor layer 29 second conductor layer 33 electroless Cu plating Layer 35 First electrolytic Cu plating layer (of second conductor layer) 37 Second electrolytic Cu plating layer (of second conductor layer) 31 Third conductor layer

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H05K 3/38 H05K 3/38 B 5E346 3/42 620 3/42 620B 3/46 3/46 BNF term (Reference) 4K024 BB11 5E314 AA24 BB01 CC01 FF01 GG11 GG12 5E317 AA24 BB02 BB12 CC32 CC33 CD15 CD23 CD25 CD27 CD32 GG01 GG03 GG09 5E339 AB02 AC01 AD03 AD05 AE01 BC02 BD02 BD03 BD08 BE13 CD52 CE17 5E343 A52 DD33 A52 DD33 ER12 ER18 GG01 GG04 GG06 GG08 5E346 AA06 AA12 AA15 AA32 AA43 AA51 BB15 CC32 CC54 CC55 CC58 DD23 DD24 DD32 DD33 DD47 DD48 EE06 EE18 EE19 EE33 EE38 FF13 FF14 GG15 GG17 H28 GG18 H25 GG18

Claims (7)

[Claims] A resin insulating layer; a filled via formed by plating in a through hole penetrating the resin insulating layer; a conductor layer having a predetermined pattern formed by plating on the resin insulating layer and the filled via; A method of manufacturing a wiring board, comprising: a resin insulating layer having the through hole; and an electroless plating layer formed in the through hole and on the resin insulating layer. On the plating layer, when a portion including a hole is plated, electrolytic plating is performed with a first plating solution in which plating grows in the hole rather than outside the hole, and the through hole is filled with plating to form the filled via. At the same time, a first electrolytic plating layer is formed on substantially the entire surface of the filled via and on the electroless plating layer of the resin insulating layer.
An electrolytic plating step, a first electrolytic plating layer thinning step of thinning the first electrolytic plating layer, and a plating resist layer forming step of forming a plating resist layer of a predetermined pattern on the thinned first electrolytic plating layer Electroplating with a second plating solution in which, when plating is performed on a portion including a hole on the first electrolytic plating layer exposed from the plating resist layer, plating grows outside the hole at least as much as inside the hole. A second electrolytic plating step of forming a second electrolytic plating layer of a predetermined pattern, a guard metal layer forming step of forming a guard metal layer of a predetermined pattern on the second electrolytic plating layer, Using a plating resist layer removing step for removing, and an etching solution that does not dissolve the guard metal layer,
A patterning step of etching and removing the exposed first electrolytic plating layer and the electroless plating layer thereunder; removing the guard metal layer, and forming the second electrolytic plating layer, the first electrolytic plating layer and the electroless plating; A guard metal layer removing step of forming a conductor layer having the above-mentioned predetermined pattern. 2. The method of manufacturing a wiring board according to claim 1, wherein in the first electrolytic plating layer thinning step, a total thickness of the first electrolytic plating layer and the electroless plating layer is about 3 to 1
A method for manufacturing a wiring board, wherein the thickness of the first electrolytic plating layer is reduced to 0 μm. 3. The method for manufacturing a wiring board according to claim 2, wherein in the patterning step, the exposed first electrolytic plating is performed using the etching solution having an etching rate of about 1 to 5 μm / min. A method for manufacturing a wiring board, wherein a layer and an electroless plating layer thereunder are removed by etching. 4. The method for manufacturing a wiring board according to claim 1, wherein in the patterning step, the exposed first electrolytic plating layer and the electroless plating layer thereunder are reduced to about 0%. .5-
A method of manufacturing a wiring board in which etching is removed in 5 minutes. 5. The method for manufacturing a wiring board according to claim 1, wherein the surface of the conductor layer is etched and roughened after the step of removing the guard metal layer. A method of manufacturing a wiring board, comprising: a step of forming an upper insulating layer on the roughened conductor layer and the resin insulating layer. 6. The method of manufacturing a wiring board according to claim 5, wherein in the second electrolytic plating step, the second electrolytic plating layer is formed of plated particles having a particle size of about 1 μm or more. Production method. 7. The method for manufacturing a wiring board according to claim 5, wherein said method further comprises a step of forming an upper conductor layer on said upper resin insulating layer.