JP2003133726A - Method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board capable of surely forming a wiring layer at the time of forming a wiring layer by so called, a subtractive method. SOLUTION: This method for manufacturing a wiring board 1 comprises a process for carrying out plating to a base layer 31 having a via hole 17 opened to a base layer surface 32 in order to form a Cu plating layer (conductive layer) 37 on the base layer surface, and for forming a filled via 19 in the via hole 17, a process for forming an etching resist layer 41 of a prescribed pattern on a Cu plating layer 37 and the filled via 19, and a process for forming a wiring layer 25 by etching removing the Cu plating layer 37 exposed from the etching resist layer 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board manufacturing method, and more particularly to a wiring board manufacturing method for forming a wiring layer by a so-called subtractive method.

[0002]

2. Description of the Related Art Conventionally, in manufacturing a wiring board, a wiring layer is often formed by a so-called subtractive method. That is, the resin insulation layer 1 is formed on the surface.
A base layer 101 having 03 is prepared (see FIG. 7). Then, this is subjected to electroless plating to form an electroless plated layer on substantially the entire surface of the resin insulating layer 103. Next, this base layer 101 is subjected to electrolytic plating to form an electrolytic plated layer on the electroless plated layer, and as shown in FIG. 7, a plated layer 105 including an electroless plated layer and an electrolytic plated layer is formed. When the via hole 107 is formed in the resin insulating layer 103, the electroless plating layer and the electrolytic plating layer are also formed on the inner peripheral surface of the via hole 107. In other words, a bowl-shaped via conductor 109 that follows the inner peripheral surface of the via hole 107 is formed.

Next, in order to pattern the wiring layer, as shown in FIG. 8, the plating layer 10 on the surface of the base layer 101 is formed.
An etching resist layer 111 corresponding to the pattern of the wiring layer is formed on the wiring 5 and on the via conductor 109. Specifically, a semi-cured etching resist layer is formed on the plated layer 105 and the via conductors 109, and is exposed and developed using a mask having a predetermined pattern corresponding to the wiring layer. afterwards,
Further, it is heated and cured to form an etching resist layer 111 having a predetermined pattern. Next, the plating layer 105 exposed from the etching resist layer 111 is removed by etching to pattern the plating layer 105. After that, by removing the etching resist layer, a wiring layer having a predetermined pattern is formed.

[0004]

However, the etching resist layer 11 having a predetermined pattern is formed on the plating layer 105.
When forming No. 1, swelling (tenting) may occur in the portion 111t of the etching resist layer 111 formed on the via conductor 109. When such a bulge occurs, the etching resist layer 1 is radiated from around the via conductor 109.
11 becomes easy to peel off. Therefore, when the plating layer 105 is etched, the etching resist layer 111 may be peeled off, and the etching liquid may soak into the lower part of the etching layer 111, whereby the plating layer 105 may be excessively removed by etching. As a result, open defects occur in the wiring layer. In particular, when the etching resist layer 111 to be formed is thin, the adhesion between the etching resist layer 111 and the plating layer 105 is generally poor, and the thinning of the etching resist layer 111 also causes tenting on the via conductor 109. Cheap. Therefore, when the plating layer 105 is etched, the etching resist layer 111 is particularly likely to peel off, and an open defect or the like is particularly likely to occur in the wiring layer.

The present invention has been made in view of the above circumstances, and provides a method of manufacturing a wiring substrate which can surely form a wiring layer when the wiring layer is formed by a so-called subtractive method. With the goal.

[0006]

[Means for Solving the Problems, Actions and Effects] The means for solving the problem is to plate a base layer having a via hole opening on the surface of the base layer to form a conductor layer on the surface of the base layer and to fill the via hole with a filled via. Forming step, an etching resist layer forming step of forming an etching resist layer of a predetermined pattern on the conductor layer and the filled via, and the conductor layer exposed from the etching resist layer is removed by etching to form a wiring layer. And a step of forming an etching step for forming a wiring board.

As described above, when there is a bowl-shaped via conductor that follows the inner peripheral surface of the via hole on the surface of the base layer, when the etching resist layer is formed, it is between the etching resist layer and the via conductor. A space is formed, and swelling (tenting) is likely to occur in the etching resist layer. Then, the etching resist layer may be peeled off due to the bulge, and finally an open defect of the wiring layer may occur. Therefore, in the present invention, the via conductor is a filled via in which the via hole is filled with plating. Therefore, the swelling of the etching resist layer does not occur on the filled via when the etching resist layer is formed. In addition, since the filled via does not have a recess, the entire filled via is in close contact with the etching resist layer, and thus the adhesiveness between these is high.

Usually, filled vias are used in the case where it is desired to connect via conductors on a lower layer via conductor in order to increase the wiring density in the wiring substrate with the miniaturization and higher performance of the wiring substrate. Is sometimes referred to as Via on Via) or as a via conductor for forming a flat pad directly on the via conductor (such a form is sometimes referred to as Pad on Via). Form. Therefore, the wiring layer of the wiring substrate having the filled vias is usually formed by a so-called semi-additive method, which enables formation of a finer pitch wiring layer. On the other hand, the present invention is characterized in that the via conductor is intentionally a filled via when the wiring layer is formed by the so-called subtractive method. It is not intended to improve the wiring density by Via on Via or Pad on Via.

When the conductor layer is formed on the surface of the base layer with a plating solution for a filled via, the surface roughness of the conductor layer tends to be smaller than that in the case where an ordinary bowl-shaped via conductor is formed. Therefore, the adhesion between the conductor layer and the etching resist layer is also improved. Therefore, when the conductor layer is removed by etching, the resist layer is less likely to be peeled off, and the wiring layer can be formed more reliably.

In the present specification, the base layer means a substrate which is obtained in the process of manufacturing a wiring board and has a via hole opened on the surface thereof. For example, a substrate in which a resin insulating layer is laminated on one side or both sides of a core substrate, in which a via hole is formed in the resin insulating layer can be cited. Further, a substrate in which a copper foil or the like is previously attached to the surface of the resin insulating layer of such a substrate may be used. In addition, a substrate in which a plurality of resin insulating layers are further laminated and a via hole is formed in the outermost resin insulating layer is also included.

Further, in the above-described wiring board manufacturing method, it is preferable that the wiring board manufacturing method is such that, in the etching resist layer forming step, the thin etching resist layer having a thickness of 20 μm or less is formed.

The thin etching resist layer is generally inferior in adhesion to the conductor layer and the via conductor, and is liable to be swollen (tenting) on the via conductor, so that it is easily peeled off when the conductor layer is removed by etching. . As a result, the etchant is likely to penetrate into the lower portion of the peeled etching resist layer, and the conductor layer is excessively etched to cause a problem such as a short circuit in the wiring layer.

On the other hand, in the present invention, since the via conductor is a filled via, the adhesiveness between the via conductor and the etching resist layer is high, and the via layer is not easily peeled off when the conductor layer is removed by etching. Furthermore, as described above, since the conductor layer on the surface of the base layer is also formed by the plating solution for forming the filled via, the surface roughness of the conductor layer is small and the adhesion between the conductor layer and the etching resist layer is improved. Therefore, when the conductor layer is removed by etching, the resist layer is less likely to be peeled off, and the wiring layer can be formed more reliably.

Moreover, by forming a thin etching resist and etching the conductor layer, so-called side etching is reduced. Therefore, it is possible to form a relatively fine wiring layer while forming the wiring by the subtractive method. The etching resist layer to be formed preferably has a thickness of 10 μm or less. This is because it is possible to more reliably form a wiring layer having finer wiring.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a partially enlarged sectional view of the main surface 3 side of the wiring board 1 manufactured in the present embodiment. The wiring board 1 has a substantially rectangular plate shape having a main surface 3 and a back surface (not shown). At the center thereof, a substantially plate-shaped core substrate (resin insulating layer) 5 is provided. A resin insulation layer 7 made of epoxy resin or the like is laminated on both surfaces thereof. Further, on the resin insulation layer 7, a solder resist layer (resin insulation layer) made of an epoxy resin or the like.
9 are laminated respectively.

Of these, a plurality of through holes 11 penetrating the core substrate 5 are formed at predetermined positions, and substantially cylindrical through hole conductors 13 are formed on the inner peripheral surface thereof. Then, in the through-hole conductor 13,
The resin filling bodies 15 each having a substantially columnar shape are filled. Further, a plurality of via holes 17 having an opening diameter of about 60 μm penetrating the resin insulating layer 7 are formed at predetermined positions, and filled vias 19 are formed in each via hole 17.
Further, in the solder resist layer 9, a plurality of pad openings 21 penetrating the solder resist layer 9 are formed at predetermined positions.

Between the core substrate 5 and the resin insulation layer 7,
The first wiring layer 23 is formed. The first wiring layer 23 is
It is connected to the through-hole conductor 13 and the filled via 19. The second wiring layer 25 is also formed between the resin insulating layer 7 and the solder resist layer 9. Second wiring layer 2
5 is connected to the filled via 19. Furthermore, the second
Some pads 25p of the wiring layer 25 are exposed in the pad openings 21 of the solder resist layer 9. A Ni plating layer is formed on the pad 25p to prevent oxidation, and an Au plating layer is further formed on the Ni plating layer (not shown).

Such a wiring board 1 is manufactured as follows. First, the double-sided copper-clad core substrate 5 (thickness of about 800
μm) is prepared. Then, a plurality of through holes 11 (opening diameter of about 350 μm) are drilled at predetermined positions with a drill (see FIG. 2). Then, electroless Cu is formed on the core substrate 5.
Plating and electrolytic Cu plating are sequentially performed to form a Cu plating layer on substantially the entire surface of the copper foil, and a substantially cylindrical through hole conductor 13 is formed on the inner peripheral surface of the through hole 11.

After that, the resin filling body 15 is filled in the through-hole conductor 13. Specifically, through-hole conductor 1
The resin paste is printed and filled in the through-hole conductor 13 using a mask having a predetermined pattern having holes corresponding to the positions 3 and the openings, and then the resin paste is thermally cured to form the resin filling body 15. And the resin filling body 1
The end portion of 5 is polished and removed to make the surface of the core substrate 5 flush.

After the resin filling body 15 is formed, the Cu layer composed of the copper foil and the Cu plating layer is patterned to form the first wiring layer 23 (thickness: about 25 μm) on both surfaces of the core substrate 5. Specifically, a semi-cured etching resist layer is formed on the Cu layer, and exposed and developed using a mask having a predetermined pattern corresponding to the first wiring layer 23. Then, it is further heated and cured to form the etching resist layer into a predetermined pattern. And Cu exposed from this resist layer
The layer is etched away. After etching, the etching resist layer is peeled off.

Next, the resin insulation layer 7 having the via holes 17 with an opening diameter of about 60 μm is formed on the core substrate 5 and the first wiring layer 23. Specifically, a semi-cured resin insulating layer is formed on the core substrate 5 and the first wiring layer 23, and is exposed and developed using a mask having a predetermined pattern corresponding to the via hole 17.
Then, it is further heat-treated and cured to form the resin insulating layer 7 having the via hole 17 at a predetermined position. In this way, the substrate (base layer) 31 shown in FIG. 2 is formed.

Next, in the plating step, first, electroless Cu plating is performed to show the surface (base layer surface) 32 of the resin insulating layer 7 of the substrate 31 and the inner peripheral surface of the via hole 17 by a thick line in FIG. An electroless Cu plating layer 33 having a thickness of about 0.7 μm is formed. After that, electrolytic Cu plating is performed using a known electrolytic plating solution for forming filled vias that is preferentially deposited in the holes, and as shown in FIG. 33, thickness about 20 μm
The electrolytic Cu plating layer 35 is formed. As a result, a Cu plating layer (conductor layer) 37 including the electroless Cu plating layer 33 and the electrolytic Cu plating layer 35 and having a thickness of about 21 μm is formed. Along with this, an electrolytic Cu plated conductor 39 is formed on the electroless plated layer 33 on the inner peripheral surface of the via hole 17,
The via hole 17 is completely filled. This allows electroless C
The filled via 19 including the u-plated layer 33 and the electrolytic Cu-plated conductor 39 is formed. These Cu plating layers 37
Since the surface of the filled via 19 and the filled via 19 are formed by the electrolytic plating solution for forming the filled via, the surface is smooth and has a small surface roughness.

Next, in the etching resist layer forming step, as shown in FIG. 4, a Cu plating layer (conductor layer) 37 is formed.
Then, an etching resist layer 41 having a predetermined pattern is formed on the filled via 19. Etching resist layer 41
Is very thin with a thickness of about 7 μm. In particular,
A semi-cured etching resist layer is formed on the Cu plated layer 37 and the filled via 19, and is exposed and developed using a mask having a predetermined pattern corresponding to the second wiring layer 25. Then, it is further heated and cured to form an etching resist layer 41 having a predetermined pattern.

In this step, if the via conductor 19 is a bowl-shaped via conductor that follows the inner peripheral surface of the via hole 17, the etching resist layer 41 and the via are not formed when the etching resist layer 41 is formed. A space is formed between the conductor 19 and the etching resist layer 41 is likely to swell (tenting). In particular, when the etching resist layer 41 is thin as in the present embodiment, the adhesion with the Cu plating layer 37 is poor, and the thinning of the etching resist layer 41 also tends to cause tenting.

On the other hand, in this embodiment, the via conductor 1
9 is a filled via 19 in which the via hole 17 is filled with a Cu-plated conductor. Therefore, when the etching resist layer 41 is formed, the tenting of the etching resist layer 41 does not occur on the filled via 19. Moreover,
Since the entire filled via 19 is in close contact with the etching resist layer 41, the adhesion between them is high. Further, as described above, when the Cu plating layer 37 is formed by the plating solution for the filled via, the surface of the Cu plating layer 37 is smooth and the surface roughness becomes small. Therefore, the adhesion between the Cu plating layer 37 and the etching resist layer 41 The property is also improved.

Next, in the etching step, the Cu plating layer 37 exposed from the etching resist layer 41 is removed by etching to form the second wiring layer 25. that time,
If tenting occurs during the formation of the etching resist layer 41, the etching resist layer 41 may be peeled off from the periphery of the via conductor 19 and the etching solution may soak into the lower portion of the via conductor 19 to remove the Cu plating layer 37 by extra etching. There is. As a result, an open defect or the like occurs in the wiring layer. In particular, when the etching resist layer 41 is thin as in the present embodiment, this problem is likely to occur.

However, in this embodiment, as described above, the adhesion between the etching resist layer 41 and the Cu plating layer 37 and the filled via 19 is high, and the etching resist layer 41 is not tented. Therefore, even when the Cu plating layer 37 is etched, the etching resist layer 41 is not peeled off, and the second wiring layer 25 can be reliably patterned. Moreover, the thickness is 20μ
The second wiring layer 25 is patterned by forming a very thin etching resist layer 41 (thickness of about 7 μm) having a thickness of 10 μm or less and further 10 μm or less. Therefore, so-called side etching is reduced. Therefore,
While using the subtractive method, the second wiring layer 25
In addition, for example, fine wiring having a line width of about 20 μm can be formed without causing problems such as opening.

After the etching, the etching resist layer 41 is peeled off as shown in FIG. Then, next, the solder resist layer 9 having the pad openings 21 is formed on the resin insulating layer 7 and the second wiring layer 25. Specifically, a semi-cured solder resist layer is formed on the resin insulating layer 7 and the second wiring layer 25, exposed and developed using a mask having a predetermined pattern corresponding to the pad opening 21. Then, it is further heat-treated and cured to form a solder resist layer 9 having a predetermined pattern. Then, a Ni plating layer is formed on the pad 25p exposed from the solder resist layer 9, and an Au plating layer is further formed thereon. As described above, the wiring board 1 shown in FIG. 1 is completed.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that the invention can be appropriately modified and applied without departing from the scope of the invention. Nor. In the above embodiment, C
Although the u-plated layer 37, the filled via 19 and the like are formed by Cu plating, they may be formed by other metal plating.

[Brief description of drawings]

FIG. 1 is a partially enlarged cross-sectional view of a wiring board according to an embodiment.

FIG. 2 is an explanatory diagram showing a state of a substrate (base layer) on which a resin insulating layer is formed in the method for manufacturing a wiring board according to the embodiment.

FIG. 3 is an explanatory view showing a state where a Cu plating layer (conductor layer) and a filled via are formed in a resin insulating layer in the method for manufacturing a wiring board according to the embodiment.

FIG. 4 relates to a method for manufacturing a wiring board according to an embodiment,
It is explanatory drawing which shows a mode that the etching resist layer was formed on the u plating layer (conductor layer) and the filled via | veer.

FIG. 5 relates to a method for manufacturing a wiring board according to an embodiment,
It is explanatory drawing which shows a mode that the u plated layer (conductor layer) was etched.

FIG. 6 is an explanatory diagram showing a state after the etching resist layer has been peeled off, in the method for manufacturing the wiring board according to the embodiment.

FIG. 7 is an explanatory diagram showing a board in which a Cu plating layer and a via conductor are formed in a resin insulating layer in a method for manufacturing a wiring board according to a conventional technique.

FIG. 8 relates to a method for manufacturing a wiring board according to the related art, in which C
It is explanatory drawing which shows a mode that the etching resist layer was formed on the u plating layer and the via conductor.

[Explanation of symbols]

1 wiring board 7 Resin insulation layer 17 Via hole 19 Fildovia 25 Second wiring layer 31 substrate (base layer) 33 Electroless Cu plating layer 35 Electrolytic Cu plating layer 37 Cu plating layer (conductor layer) 39 Electrolytic Cu plating layer body 41 Etching resist layer

Claims (2)

[Claims] 1. A plating step for forming a conductor layer on the surface of the base layer by forming a base layer having a via hole opening on the surface of the base layer, and forming a filled via in the via hole; and a plating step on the conductor layer and the filled via. Manufacturing of a wiring board, comprising: an etching resist layer forming step of forming an etching resist layer having a predetermined pattern on the top; and an etching step of forming a wiring layer by etching away the conductor layer exposed from the etching resist layer. Method. 2. The method of manufacturing a wiring board according to claim 1, wherein a thickness of 20 is formed in the etching resist layer forming step.
A method of manufacturing a wiring board, wherein the etching resist layer having a thickness of not more than μm is formed.