US20080128288A1 - Method of manufacturing a multi-layer wiring board using a metal member having a rough surface - Google Patents
Method of manufacturing a multi-layer wiring board using a metal member having a rough surface Download PDFInfo
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- US20080128288A1 US20080128288A1 US11/811,066 US81106607A US2008128288A1 US 20080128288 A1 US20080128288 A1 US 20080128288A1 US 81106607 A US81106607 A US 81106607A US 2008128288 A1 US2008128288 A1 US 2008128288A1
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- wiring patterns
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4658—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern characterized by laminating a prefabricated metal foil pattern, e.g. by transfer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1152—Replicating the surface structure of a sacrificial layer, e.g. for roughening
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
Definitions
- Wiring boards typically have a wiring layer formed on the surface of an insulating substrate such that the thickness of the wiring layer protrudes above the surface of the insulating substrate. In boards which have high wiring pattern densities, such structures are prone to short-circuiting problems, particularly where contacts to the wiring layers are formed.
- Wiring boards are known in which the surfaces of wiring patterns themselves are embedded in the insulating material at the surface of the substrate so as to be coplanar (located at the same plane) with the surface of the insulating material. Examples of such wiring board structures are described in Japanese Examined Patent Application Publication H 6-21619.
- FIGS. 4(A) through 4(G) show one example of the production steps in a method of manufacturing a wiring board having such structure.
- a transfer technique is used to make a wiring board in which exposed surfaces of the insulating material and the wiring layer embedded therein are coplanar.
- a three-layer metal member is prepared by providing a nickel layer b as an etch stop layer overlying a copper carrier layer a, and a copper layer c overlying the surface of the nickel layer b as a layer from which wiring patterns will be formed.
- a thin metallic film h is formed by electrolessly plating the entire exposed surface of the wiring board, and subsequently a photoresist layer i is formed and patterned as a mask for forming the through holes.
- FIG. 4(F) shows the condition after this copper layer j is formed.
- this photoresist layer is removed and the thin layer h formed by electroless plating is removed to complete the wiring board ( FIG. 4(G) ) which includes a copper layer j covering through holes g to connect the wiring patterns exposed at opposite surfaces of the wiring board.
- the electrodes of electronic parts are connected by means of solder, etc. to the copper layer j, etc., in areas of the wiring board not covered by a selectively-formed solder resist.
- a selective electrolytic etching process used to form the resist layer i interferes with the additive process of forming the copper layer j, making copper layer j prone to poor connection, poor bonding, and peeling.
- a patternable member which includes a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer.
- a metal layer overlying the etch stop layer.
- the metal layer is etched selectively to a material of the etch stop layer to form a plurality of wiring patterns and to expose the rough surface of the etch stop layer between the wiring patterns.
- An insulating layer is joined to the wiring patterns and to the exposed rough surface of the etch stop layer.
- the carrier layer and the etch stop layer are removed from the insulating layer to expose the wiring patterns and expose a rough major surface of the insulating layer between the wiring patterns. Openings are then formed in the insulating layer in contact with at least some of the wiring patterns.
- a layer of metal is electrolessly plated onto the rough major surface of the insulating layer and within the openings in the insulating layer.
- a conductive wiring pattern is selectively electrolytically plated over the electrolessly plated layer and within the openings to form plated openings which conductively interconnect at least some of the wiring patterns. Portions of the electrolessly plated layer exposed by the conductive wiring pattern can then be removed.
- the step of forming openings in the insulating layer includes forming through holes extending from the first surface through the insulating layer to the second surface.
- the step of selectively electrolytically plating a conductive wiring pattern conductively interconnects wiring patterns exposed at the first surface with wiring patterns exposed at the second surface of the insulating layer.
- the etch stop layer includes a metal which is not attacked by an etchant which attacks a metal included in the metal layer overlying the etch stop layer.
- the etch stop layer consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer each consists essentially of copper.
- the patternable member is formed by forming the thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer.
- the carrier layer includes a metal.
- the roughness of the exposed surface of the carrier layer in contact with the etch stop layer is such that it has unevenness of between about 0.1 micron and about 10 microns.
- a solder mask is formed to overlie surfaces of the wiring circuit element in such manner that the solder mask exposes the electrolytically plated conductive wiring patterns.
- the wiring patterns are embedded in the insulating layer such that the rough major surface of the insulating layer is co-planar with exposed major surfaces of the wiring patterns.
- a method of manufacturing a multi-layer wiring circuit element is provided.
- a first patternable member and a second patternable member are provided in which each of the first and second patternable members includes a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer.
- corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surfaces of the carrier layer are rough.
- the metal layers of the first and second patternable members are etched selective to a material of the etch stop layer to form first wiring patterns overlying the etch stop layer of the first patternable member and form second wiring patterns overlying the etch stop layer of the second patternable member and expose the rough surfaces of the etch stop layers in areas exposed by the first or second wiring patterns.
- the first and second insulating layers are joined to the wiring patterns and exposed etch stop layers of the first and second patternable members, respectively.
- An interconnection element including at least a third insulating layer is subsequently joined to the first and second insulating layers, the interconnection element having a plurality of interconnect wiring patterns extending in one or more directions parallel to an exposed surface of the third insulating layer.
- the carrier layers and the etch stop layers are removed to expose the wiring patterns joined to the first and second insulating layers and rough major surfaces of the first and second insulating layers between the wiring patterns.
- Through holes are formed which extend through the first, second and third insulating layers, the through holes contacting at least some of the wiring patterns.
- a layer of metal is electrolessly plated onto the rough major surfaces of the first and second insulating layers and within the through holes.
- conductive wiring patterns are selectively electrolytically plated over the electrolessly plated layers and within the through holes. Portions of the electrolessly plated layers exposed between the electrolytically plated conductive wiring patterns are removed.
- blind openings are formed which extend through at least one of the first and second insulating layers to the interconnect wiring patterns.
- the step of selectively electrolytically plating conductive wiring patterns includes electrolytically plating the conductive wiring patterns in the blind openings to connect the interconnect wiring patterns with at least some of the first or second wiring patterns.
- the interconnect wiring patterns of the interconnection element are disposed in a plurality of wiring layers separated by respective insulating layers, and the interconnection element further includes plated through holes which conductively interconnect the plurality of wiring layers of the interconnection element.
- FIGS. 1(A) through 1(M) are cross sectional views illustrating a method of manufacturing a wiring board in accordance with a first embodiment of the invention.
- FIGS. 2(A) through 2(H) are cross sectional views illustrating a method of manufacturing a wiring board in accordance with a second embodiment of the invention.
- FIG. 3 is a cross sectional view illustrating a wiring board in accordance with the invention.
- FIGS. 4(A) through 4(G) are cross sectional views illustrating a method of manufacturing a wiring board according to the prior art.
- one of the major surfaces of a carrier layer which serves as a member for the manufacture of a circuit board is a rough surface.
- This rough surface is transferred to a metal etch stop layer and, in turn, to a metal wiring layer formed on that rough surface.
- the rough surface is then transferred to insulating material which forms a base of the board.
- the insulating material which forms the base of the wiring board preferably includes epoxy resin in which glass fibers are embedded.
- a preferred method of interconnecting wiring layers of the wiring board is to form through holes and then line the through holes by electroless plating of copper or other metal.
- a resist layer is then formed and copper or other metal is then selectively deposited by electrolytic plating.
- a dry resist layer is used as this resist layer.
- FIGS. 1(A) through 1(M) are cross sectional views showing the production steps in manufacturing a wiring board according to a first embodiment of this invention.
- a carrier layer 2 is prepared which preferably includes or consists essentially of copper and has a thickness of several microns to several hundred microns. At least one of the major surfaces of this carrier layer 2 has an average roughness of approximately 0.1 microns to about 10 microns measured by unevenness in the surface.
- Commercially available copper foil exists which has approximately this degree of roughness on at least one of its major surfaces. It is also acceptable to use a copper foil or other metal foil as the metal carrier layer 2 which has unevenness on both of its surfaces.
- an etch stop layer 6 including or consisting essentially of nickel, for example, and preferably having a thickness of under 1.0 microns is formed on the rough major surface 4 of the carrier layer 2 .
- the surface of the etch stop layer 6 is also rough. This is because the etch stop layer 6 is thin, preferably under 1.0 microns and follows the roughness of the uneven major surface 4 of the carrier layer 2 .
- a metal layer 8 preferably consisting essentially of copper and having a thickness of several microns to several hundred microns is formed on the surface of the etch stop layer 6 to complete a member 10 for use in manufacturing a wiring board.
- the metal layer 8 will be subsequently patterned into wiring patterns of the wiring board.
- wiring patterns 12 , 12 , . . . are formed by selectively etching the metal layer 8 .
- the rough surface of the etch stop layer 6 is exposed by this etching process in areas between the wiring patterns 12 , 12 .
- the member obtained after performing this step (D) is 10 a.
- the two members 10 a , 10 a are disposed opposite each other so that the surfaces on which wiring patterns 12 , 12 , . . . are formed face each other, with a layer of insulating material 14 disposed between them, the layer 14 preferably including glass fiber and epoxy resin.
- the members 10 a and insulating material 14 are joined by heat and pressure.
- the rough surfaces of the metal members 10 a are transferred to the surfaces 16 of the insulating material 14 to make them rough as well, except where the insulating material contacts the wiring patterns 12 , 12 . . . .
- the rough surfaces of the etch stop layers 6 are transferred to the major surfaces 16 of the insulating material 14 .
- wiring patterns 12 , 12 , . . . are formed on both major surfaces of the insulating material 14
- wiring patterns 12 , 12 , . . . can be provided at only one major surface of the insulating material 14 .
- through holes 18 are formed which cut through or adjoin the wiring patterns 12 on both sides of the insulating material.
- the through holes after further processing, facilitate interlayer connections between the wiring patterns 12 .
- a thin metal layer 20 preferably including or consisting essentially of copper, is formed by electroless plating over the entire surfaces of the wiring board including within through holes 18 and over major surfaces 16 of the insulating material and exposed surfaces 15 of the wiring patterns.
- the copper layer 20 preferably is thin, from about 0.02 microns up to several microns in thickness. Since the copper layer 20 is formed on the rough surface 16 of the insulating material 14 , it avoids problems of poor bonding and a tendency to peel that plague the electroless copper layer of the wiring bond formed according to the prior art method ( FIGS. 4(A) through 4(G) ).
- a resist layer 22 is selectively formed, e.g., either by selective deposition or subtractive patterning, as a mask for further processing of the metal layer 20 overlying through holes 18 .
- the selective formation of this resist mask 22 preferably is performed by applying a photoresist that is a dry film over the entire surface of the wiring board 10 a , exposing the resist to light and developing it. Since the resist layer 22 is formed on the rough-surfaced copper layer 20 , it bonds more strongly to the insulating material 14 and is better able to avoid the problems of the prior art of poor bonding and the tendency to peel.
- a metal layer e.g., copper layer 24 is formed by electrolytic plating in the through holes, with the resist layer 22 functioning as the mask.
- solder resist layer 26 is selectively formed.
- solder resist layer 26 is formed on the rough surface of the insulating material 14 . Therefore, the solder resist layer strongly adheres to the underlying insulating material 14 , avoiding the above-described problems of poor bonding and the tendency to peel.
- FIGS. 2(A) through (M) are cross sectional views showing production steps in a method of manufacturing a wiring board in accordance with a second embodiment of the invention.
- a member for the manufacture of a wiring board 10 is prepared in a manner as described above with reference to FIG. 1(C) , and wiring patterns 12 , 12 , . . . are formed by selectively etching the metal layer 8 , to form the wiring board member 10 a having a carrier layer 2 and etch stop layer 6 having an exposed rough-surface as shown in FIG. 2(A) .
- an insulating layer 40 consisting, for example of resin, is bonded to the rough surface of the member 10 a upon which the wiring patterns 12 , 12 , . . . are formed.
- a base is prepared that includes metal layers 44 , 44 on both sides of a layer of insulating material 42 .
- Layer 42 preferably includes or consists essentially of a resin, for example.
- the carrier layers 2 , 2 of the members 10 a , 10 a on both sides are removed, and the etch stop layers 6 , 6 are removed, leaving rough surfaces 15 of the wiring patterns and rough surfaces 41 of the insulating material 40 exposed.
- blind openings 46 , 46 serving as the interlayer connection means, and through holes 48 are formed, to provide the structure shown in FIG. 2(D) .
- a metal layer 50 of copper or the like is formed by electroless plating over the exposed surfaces. Subsequently, the through holes are selectively electrolytically plated with copper or other suitable metal at which time resist patterns 52 , 52 serve as the required plating mask.
- plated through holes 54 and plated blind openings 56 provide interlayer connections between the wiring patterns 12 on each side of the insulating material 40 .
- FIG. 2(E) shows the plated through holes 54 and plated blind openings 56 after they are formed.
- solder resist layer 58 is selectively formed to cover areas other than the plated through holes 54 and plated blind openings 56 .
- FIGS. 2(A) through 2(H) is configured to obtain a wiring board that is slightly different in structure from the embodiment shown in FIG. 1 .
- the member 10 shown in FIG. 1(C) the technological effect of the embodiment that is shown in FIGS. 1(A) through 1(M) can be obtained.
- FIG. 3 is a cross sectional view showing a wiring board according to a third embodiment of the invention in which a plated through hole 55 conductively interconnects internal wiring pattern layers 60 and 62 but does not conductively interconnect those layers to the outermost wiring patterns 12 .
- Internal wiring pattern layers 60 or 62 are conductively interconnected to another plated through hole 54 which provides conductive interconnection to outermost wiring patterns 12 .
- Plated blind vias 56 provide further interconnection between wiring patterns 12 and wiring pattern layers 60 .
- this embodiment of the invention facilitates manufacture of a more multi-layered structure, a greater diversity of through-hole shapes, and can facilitate the manufacture of wiring boards with a variety of structures.
- Layers including copper or the like used to plate the through holes are formed using electrolytic plating of copper or the like in this particular embodiment, but the invention is not limited to this, and can be formed using, for example, conductive fillers.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Methods are provided for manufacturing a wiring circuit element or wiring board in which a set of rough wiring patterns are formed by selectively etching a metal layer of a patternable member which includes a carrier layer having a rough surface and a thin rough-surfaced etch stop layer between the carrier layer and the metal layer. The etch stop layer and wiring patterns are joined to an insulating layer such that the wiring patterns adhere to the insulating layer and the insulating layer acquires a rough surface. Thereafter, the carrier layer and the etch stop layer are removed, after which openings are formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer, and then a conductive wiring pattern is selectively electroplated over the electrolessly plated layer to form plated openings that interconnect at least some of the wiring patterns.
Description
- This application is a continuation of U.S. patent application Ser. No. 11/585,064, filed Oct. 23, 2006, which is a continuation of U.S. patent application Ser. No. 11/356,672, filed Feb. 17, 2006, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2005-43784, filed Feb. 21, 2005, the disclosures of which are hereby incorporated by reference herein.
- Wiring boards typically have a wiring layer formed on the surface of an insulating substrate such that the thickness of the wiring layer protrudes above the surface of the insulating substrate. In boards which have high wiring pattern densities, such structures are prone to short-circuiting problems, particularly where contacts to the wiring layers are formed.
- Wiring boards are known in which the surfaces of wiring patterns themselves are embedded in the insulating material at the surface of the substrate so as to be coplanar (located at the same plane) with the surface of the insulating material. Examples of such wiring board structures are described in Japanese Examined Patent Application Publication H 6-21619.
-
FIGS. 4(A) through 4(G) show one example of the production steps in a method of manufacturing a wiring board having such structure. In a typical method, a transfer technique is used to make a wiring board in which exposed surfaces of the insulating material and the wiring layer embedded therein are coplanar. - (A) As shown in
FIG. 4(A) , a three-layer metal member is prepared by providing a nickel layer b as an etch stop layer overlying a copper carrier layer a, and a copper layer c overlying the surface of the nickel layer b as a layer from which wiring patterns will be formed. - (B) Next, as shown in
FIG. 4(B) , by selectively etching the copper layer c, wiring layers d, d, are formed to provide a wiring member “e”. In the etching process, the nickel layer b prevents the copper carrier layer a from being etched. - (C) Two wiring members e as shown in
FIG. 4(B) are prepared and disposed in opposition to each other such that the wiring layers d, d face each other. The wiring members e are pressed together with a glass fiber epoxy resin member f disposed between them to form a combined structure as shown inFIG. 4(C) . - (D) The copper carrier layer a and the nickel layer b are no longer needed and are then removed, as shown in
FIG. 4(D) . In so doing, a wiring board is completed in which the wiring layers d, d, . . . have exposed surfaces d1 which are coplanar with the exposed surfaces f1 of the insulating material f. - (E) Next, as shown in
FIG. 4(E) , through holes g are formed where needed to provide interlayer connections between the wiring patterns on the top and bottom surfaces of the insulating material. - (F) Next, as shown in
FIG. 4(F) , a thin metallic film h is formed by electrolessly plating the entire exposed surface of the wiring board, and subsequently a photoresist layer i is formed and patterned as a mask for forming the through holes. - Having done so, using this photoresist layer i as a mask for electroplating, copper layer j is deposited electrolytically onto exposed surfaces of the electrolessly formed film to form plated through
holes 24.FIG. 4(F) shows the condition after this copper layer j is formed. - (G) Next, this photoresist layer is removed and the thin layer h formed by electroless plating is removed to complete the wiring board (
FIG. 4(G) ) which includes a copper layer j covering through holes g to connect the wiring patterns exposed at opposite surfaces of the wiring board. Next, although not indicated in the drawings, the electrodes of electronic parts are connected by means of solder, etc. to the copper layer j, etc., in areas of the wiring board not covered by a selectively-formed solder resist. - However, the background technology shown in
FIGS. 4(A) through 4(G) has the following problems: - First, it is difficult to form the copper layer j by the additive process shown in
FIGS. 4( a) through 4(G) because of poor connection, poor bonding, and peeling of the copper layer j from the through holes due to the process of electrolytic plating used to form copper layer j and the electroless plating process which is assumed to be unavoidable for forming the copper underlayer h. - Second, a selective electrolytic etching process used to form the resist layer i interferes with the additive process of forming the copper layer j, making copper layer j prone to poor connection, poor bonding, and peeling.
- Third, upon completing the steps outlined in
FIG. 4(G) , it is necessary to selectively form a solder resist layer overlying wiring layers d. - These problems, in large part, are due to the exposed surfaces f1 of the glass fiber epoxy resin member f of the insulating material being smooth and failing to adequately grip the electroless and electrolytic metal layers disposed thereon.
- According to various embodiments of the invention described herein, methods are provided herein for manufacturing a wiring circuit element or wiring board. In a method in accordance with one embodiment of the invention, a patternable member is provided which includes a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer. As a result, corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surface of the carrier layer are rough. The metal layer is etched selectively to a material of the etch stop layer to form a plurality of wiring patterns and to expose the rough surface of the etch stop layer between the wiring patterns. An insulating layer is joined to the wiring patterns and to the exposed rough surface of the etch stop layer. Thereafter, the carrier layer and the etch stop layer are removed from the insulating layer to expose the wiring patterns and expose a rough major surface of the insulating layer between the wiring patterns. Openings are then formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer and within the openings in the insulating layer. Thereafter, a conductive wiring pattern is selectively electrolytically plated over the electrolessly plated layer and within the openings to form plated openings which conductively interconnect at least some of the wiring patterns. Portions of the electrolessly plated layer exposed by the conductive wiring pattern can then be removed.
- In accordance with a particular embodiment of the invention, at least two patternable members are used such that first and second exposed surfaces of the insulating layer are joined to the wiring patterns and exposed rough surfaces of the etch stop layers. In such embodiment, the step of forming openings in the insulating layer includes forming through holes extending from the first surface through the insulating layer to the second surface. In addition, the step of selectively electrolytically plating a conductive wiring pattern conductively interconnects wiring patterns exposed at the first surface with wiring patterns exposed at the second surface of the insulating layer.
- In accordance with one or more embodiments of the invention, the etch stop layer includes a metal which is not attacked by an etchant which attacks a metal included in the metal layer overlying the etch stop layer.
- Preferably, the etch stop layer consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer each consists essentially of copper.
- In a particular embodiment of the invention, the patternable member is formed by forming the thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer. Preferably, the carrier layer includes a metal.
- The roughness of the exposed surface of the carrier layer in contact with the etch stop layer is such that it has unevenness of between about 0.1 micron and about 10 microns.
- Preferably, a solder mask is formed to overlie surfaces of the wiring circuit element in such manner that the solder mask exposes the electrolytically plated conductive wiring patterns.
- In accordance with one or more preferred aspects of the invention, the wiring patterns are embedded in the insulating layer such that the rough major surface of the insulating layer is co-planar with exposed major surfaces of the wiring patterns.
- In accordance with another embodiment of the invention, a method of manufacturing a multi-layer wiring circuit element is provided. In such method, a first patternable member and a second patternable member are provided in which each of the first and second patternable members includes a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer. In this way, corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surfaces of the carrier layer are rough. The metal layers of the first and second patternable members are etched selective to a material of the etch stop layer to form first wiring patterns overlying the etch stop layer of the first patternable member and form second wiring patterns overlying the etch stop layer of the second patternable member and expose the rough surfaces of the etch stop layers in areas exposed by the first or second wiring patterns. Thereafter, the first and second insulating layers are joined to the wiring patterns and exposed etch stop layers of the first and second patternable members, respectively. An interconnection element including at least a third insulating layer is subsequently joined to the first and second insulating layers, the interconnection element having a plurality of interconnect wiring patterns extending in one or more directions parallel to an exposed surface of the third insulating layer. Thereafter, the carrier layers and the etch stop layers are removed to expose the wiring patterns joined to the first and second insulating layers and rough major surfaces of the first and second insulating layers between the wiring patterns. Through holes are formed which extend through the first, second and third insulating layers, the through holes contacting at least some of the wiring patterns. Subsequently, a layer of metal is electrolessly plated onto the rough major surfaces of the first and second insulating layers and within the through holes. Thereafter, conductive wiring patterns are selectively electrolytically plated over the electrolessly plated layers and within the through holes. Portions of the electrolessly plated layers exposed between the electrolytically plated conductive wiring patterns are removed.
- In a preferred embodiment of the invention, blind openings are formed which extend through at least one of the first and second insulating layers to the interconnect wiring patterns. In such case, the step of selectively electrolytically plating conductive wiring patterns includes electrolytically plating the conductive wiring patterns in the blind openings to connect the interconnect wiring patterns with at least some of the first or second wiring patterns.
- Preferably, the interconnect wiring patterns of the interconnection element are disposed in a plurality of wiring layers separated by respective insulating layers, and the interconnection element further includes plated through holes which conductively interconnect the plurality of wiring layers of the interconnection element.
-
FIGS. 1(A) through 1(M) are cross sectional views illustrating a method of manufacturing a wiring board in accordance with a first embodiment of the invention. -
FIGS. 2(A) through 2(H) are cross sectional views illustrating a method of manufacturing a wiring board in accordance with a second embodiment of the invention. -
FIG. 3 is a cross sectional view illustrating a wiring board in accordance with the invention. -
FIGS. 4(A) through 4(G) are cross sectional views illustrating a method of manufacturing a wiring board according to the prior art. - In the embodiments of the invention described below, one of the major surfaces of a carrier layer which serves as a member for the manufacture of a circuit board is a rough surface. This rough surface is transferred to a metal etch stop layer and, in turn, to a metal wiring layer formed on that rough surface. The rough surface is then transferred to insulating material which forms a base of the board. The insulating material which forms the base of the wiring board preferably includes epoxy resin in which glass fibers are embedded. After the metal wiring layer is patterned, the metal wiring layer and the insulating material retain the rough surface when the carrier layer is removed.
- A preferred method of interconnecting wiring layers of the wiring board is to form through holes and then line the through holes by electroless plating of copper or other metal. A resist layer is then formed and copper or other metal is then selectively deposited by electrolytic plating. Preferably a dry resist layer is used as this resist layer.
- The embodiments of the invention provided herein are described with reference to the drawings.
-
FIGS. 1(A) through 1(M) are cross sectional views showing the production steps in manufacturing a wiring board according to a first embodiment of this invention. - (A) As shown in
FIG. 1(A) , acarrier layer 2 is prepared which preferably includes or consists essentially of copper and has a thickness of several microns to several hundred microns. At least one of the major surfaces of thiscarrier layer 2 has an average roughness of approximately 0.1 microns to about 10 microns measured by unevenness in the surface. Commercially available copper foil exists which has approximately this degree of roughness on at least one of its major surfaces. It is also acceptable to use a copper foil or other metal foil as themetal carrier layer 2 which has unevenness on both of its surfaces. - (B) Next, as shown in
FIG. 1(A) , anetch stop layer 6 including or consisting essentially of nickel, for example, and preferably having a thickness of under 1.0 microns is formed on the rough major surface 4 of thecarrier layer 2. - Like the surface 4 of the carrier layer, the surface of the
etch stop layer 6 is also rough. This is because theetch stop layer 6 is thin, preferably under 1.0 microns and follows the roughness of the uneven major surface 4 of thecarrier layer 2. - (C) Next, as shown in
FIG. 1(C) , ametal layer 8, preferably consisting essentially of copper and having a thickness of several microns to several hundred microns is formed on the surface of theetch stop layer 6 to complete amember 10 for use in manufacturing a wiring board. Themetal layer 8 will be subsequently patterned into wiring patterns of the wiring board. - (D) Next, as shown in
FIG. 1(D) ,wiring patterns metal layer 8. The rough surface of theetch stop layer 6 is exposed by this etching process in areas between thewiring patterns - (E) Next, as shown in
FIG. 1 (E), the twomembers wiring patterns material 14 disposed between them, thelayer 14 preferably including glass fiber and epoxy resin. Themembers 10 a and insulatingmaterial 14 are joined by heat and pressure. - At this time, the rough surfaces of the
metal members 10 a are transferred to thesurfaces 16 of the insulatingmaterial 14 to make them rough as well, except where the insulating material contacts thewiring patterns etch stop layers 6 are transferred to themajor surfaces 16 of the insulatingmaterial 14. - Although in the embodiment illustrated in
FIGS. 1(A) through 1(E) wiring patterns material 14, in otherembodiments wiring patterns material 14. - (F) Next, as shown in FIG. (F), the
carrier layer 2 and theetch stop layer 6 are removed because they are no longer needed. In so doing, a wiring board is completed in which the exposed surfaces 15 of thewiring patterns major surfaces 16 of the insulatingmaterial 14 and both the exposed surfaces 15 of the wiring patterns and the exposed major surfaces of the insulating material are rough surfaces. - (G) Next, as shown in
FIG. 1(G) , throughholes 18 are formed which cut through or adjoin thewiring patterns 12 on both sides of the insulating material. The through holes, after further processing, facilitate interlayer connections between thewiring patterns 12. - (H) Next, as shown in
FIG. 1 (H), athin metal layer 20, preferably including or consisting essentially of copper, is formed by electroless plating over the entire surfaces of the wiring board including within throughholes 18 and overmajor surfaces 16 of the insulating material and exposedsurfaces 15 of the wiring patterns. Thecopper layer 20 preferably is thin, from about 0.02 microns up to several microns in thickness. Since thecopper layer 20 is formed on therough surface 16 of the insulatingmaterial 14, it avoids problems of poor bonding and a tendency to peel that plague the electroless copper layer of the wiring bond formed according to the prior art method (FIGS. 4(A) through 4(G) ). - (I) Next, as shown in
FIG. 1(I) , a resistlayer 22 is selectively formed, e.g., either by selective deposition or subtractive patterning, as a mask for further processing of themetal layer 20 overlying throughholes 18. The selective formation of this resistmask 22 preferably is performed by applying a photoresist that is a dry film over the entire surface of thewiring board 10 a, exposing the resist to light and developing it. Since the resistlayer 22 is formed on the rough-surfacedcopper layer 20, it bonds more strongly to the insulatingmaterial 14 and is better able to avoid the problems of the prior art of poor bonding and the tendency to peel. - (J) Next, as shown in
FIG. 1(J) , a metal layer, e.g.,copper layer 24 is formed by electrolytic plating in the through holes, with the resistlayer 22 functioning as the mask. - (K) Next, as shown in
FIG. 1(K) , the resistlayer 22 is removed. - (L) Next, as shown in
FIG. 1(L) , thecopper layer 20 is removed. - (M) Next, as shown in
FIG. 1(M) , a solder resistlayer 26 is selectively formed. - This solder resist
layer 26 is formed on the rough surface of the insulatingmaterial 14. Therefore, the solder resist layer strongly adheres to the underlying insulatingmaterial 14, avoiding the above-described problems of poor bonding and the tendency to peel. -
FIGS. 2(A) through (M) are cross sectional views showing production steps in a method of manufacturing a wiring board in accordance with a second embodiment of the invention. - (A) First, a member for the manufacture of a
wiring board 10 is prepared in a manner as described above with reference toFIG. 1(C) , andwiring patterns metal layer 8, to form thewiring board member 10 a having acarrier layer 2 and etchstop layer 6 having an exposed rough-surface as shown inFIG. 2(A) . - (B) Next, as shown in
FIG. 2(B) , an insulatinglayer 40 consisting, for example of resin, is bonded to the rough surface of themember 10 a upon which thewiring patterns - (C) As shown in
FIG. 2(C) , a base is prepared that includes metal layers 44, 44 on both sides of a layer of insulatingmaterial 42.Layer 42 preferably includes or consists essentially of a resin, for example. - (D) Next, referring to
FIG. 2(D) , twomembers - Next, the carrier layers 2,2 of the
members rough surfaces 15 of the wiring patterns andrough surfaces 41 of the insulatingmaterial 40 exposed. - After that,
blind openings holes 48 are formed, to provide the structure shown inFIG. 2(D) . - Next, referring to
FIG. 2(E) , ametal layer 50 of copper or the like is formed by electroless plating over the exposed surfaces. Subsequently, the through holes are selectively electrolytically plated with copper or other suitable metal at which time resistpatterns - In such manner, plated through
holes 54 and platedblind openings 56 provide interlayer connections between thewiring patterns 12 on each side of the insulatingmaterial 40.FIG. 2(E) shows the plated throughholes 54 and platedblind openings 56 after they are formed. - (F) Next, as shown in
FIG. 2(F) , the resistlayers - (G) Next, as shown in
FIG. 2(G) , themetal layer 50 that was formed by electroless plating is removed in exposed areas not covered by the electrolytically plated layer. - (H) Next, as shown in
FIG. 2(H) , a solder resistlayer 58 is selectively formed to cover areas other than the plated throughholes 54 and platedblind openings 56. - The embodiment shown in
FIGS. 2(A) through 2(H) is configured to obtain a wiring board that is slightly different in structure from the embodiment shown inFIG. 1 . However, by using themember 10 shown inFIG. 1(C) the technological effect of the embodiment that is shown inFIGS. 1(A) through 1(M) can be obtained. -
FIG. 3 is a cross sectional view showing a wiring board according to a third embodiment of the invention in which a plated throughhole 55 conductively interconnects internal wiring pattern layers 60 and 62 but does not conductively interconnect those layers to theoutermost wiring patterns 12. Internal wiring pattern layers 60 or 62 are conductively interconnected to another plated throughhole 54 which provides conductive interconnection tooutermost wiring patterns 12. Platedblind vias 56 provide further interconnection betweenwiring patterns 12 and wiring pattern layers 60. - Thus, this embodiment of the invention facilitates manufacture of a more multi-layered structure, a greater diversity of through-hole shapes, and can facilitate the manufacture of wiring boards with a variety of structures.
- Layers including copper or the like used to plate the through holes are formed using electrolytic plating of copper or the like in this particular embodiment, but the invention is not limited to this, and can be formed using, for example, conductive fillers.
- Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (17)
1. A method of manufacturing a wiring circuit element comprising the steps of:
providing a patternable member including a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer such that corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surface of the carrier layer are rough;
etching the metal layer selectively to a material of the etch stop layer to form a plurality of wiring patterns and to expose the rough surface of the etch stop layer between the wiring patterns;
joining an insulating layer to the wiring patterns and to the exposed rough surface of the etch stop layer;
thereafter removing the carrier layer and the etch stop layer from the insulating layer to expose the wiring patterns and expose a rough major surface of the insulating layer between the wiring patterns;
forming openings in the insulating layer in contact with at least some of the wiring patterns;
electrolessly plating a layer of metal onto the rough major surface of the insulating layer and within the openings in the insulating layer;
selectively electrolytically plating a conductive wiring pattern over the electrolessly plated layer and within the openings to form plated openings which conductively interconnect at least some of the wiring patterns; and
removing portions of the electrolessly plated layer exposed by the conductive wiring pattern.
2. The method as claimed in claim 1 , wherein exposed first and second opposite surfaces of the insulating layer are joined to the wiring patterns and exposed rough surfaces of the etch stop layers of at least two of the patternable members, the step of forming openings in the insulating layer includes forming through holes extending from the first surface through the insulating layer to the second surface, and the step of selectively electrolytically plating a conductive wiring pattern conductively interconnects wiring patterns exposed at the first surface with wiring patterns exposed at the second surface of the insulating layer.
3. The method as claimed in claim 1 , wherein the etch stop layer includes a metal which is not attacked by an etchant which attacks a metal included in the metal layer overlying the etch stop layer.
4. The method as claimed in claim 3 , wherein the etch stop layer consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer consist essentially of copper.
5. The method as claimed in claim 4 , wherein the patternable member is formed by forming the thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer.
6. The method as claimed in 3, wherein the carrier layer includes a metal.
7. The method as claimed in claim 1 , wherein the exposed surface of the carrier layer in contact with the etch stop layer has unevenness of between about 0.1 micron and about 10 microns.
8. The method as claimed in claim 5 , further comprising forming a solder mask overlying surfaces of the wiring circuit element, the solder mask exposing the electrolytically plated conductive wiring patterns.
9. The method as claimed in claim 1 , wherein the wiring patterns are embedded in the insulating layer such that the rough major surface of the insulating layer is co-planar with major surfaces of the wiring patterns.
10. A method of manufacturing a multi-layer wiring circuit element, comprising the steps of:
providing a first patternable member and a second patternable member, each of the first and second patternable members including a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer, such that corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surfaces of the carrier layer are rough;
etching the metal layers of the first and second patternable members selective to a material of the etch stop layer to form first wiring patterns overlying the etch stop layer of the first patternable member and to form second wiring patterns overlying the etch stop layer of the second patternable member and to expose the rough surfaces of the etch stop layers in areas exposed by the first or second wiring patterns;
joining first and second insulating layers to the wiring patterns and exposed etch stop layers of the first and second patternable members, respectively;
joining an interconnection element including at least a third insulating layer to the first and second insulating layers, the interconnection element including a plurality of interconnect wiring patterns extending in one or more directions parallel to an exposed surface of the third insulating layer;
thereafter removing the carrier layers and the etch stop layers to expose the wiring patterns joined to the first and second insulating layers and rough major surfaces of the first and second insulating layers between the wiring patterns;
forming through holes extending through the first, second and third insulating layers, the through holes contacting at least some of the wiring patterns;
electrolessly plating a layer of metal onto the rough major surfaces of the first and second insulating layers and within the through holes;
selectively electrolytically plating conductive wiring patterns over the electrolessly plated layers and within the through holes; and
removing portions of the electrolessly plated layers exposed between the electrolytically plated conductive wiring patterns.
11. The method as claimed in claim 10 , further comprising forming blind openings extending through at least one of the first and second insulating layers to the interconnect wiring patterns, wherein the step of selectively electrolytically plating conductive wiring patterns includes electrolytically plating the conductive wiring patterns in the blind openings to connect the interconnect wiring patterns with at least some of the first or second wiring patterns.
12. The method as claimed in claim 10 , wherein the interconnect wiring patterns of the interconnection element are disposed in a plurality of wiring layers separated by respective insulating layers, the interconnection element further including plated through holes conductively interconnecting the plurality of wiring layers of the interconnection element.
13. The method as claimed in claim 12 , further comprising forming a solder mask overlying surfaces of the multi-layer wiring element, the solder mask exposing the electrolytically plated conductive wiring patterns.
14. The method as claimed in claim 10 , wherein the etch stop layer of each patternable member consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer consist essentially of copper.
15. The method as claimed in claim 14 , wherein each of the first and second patternable members is formed by forming a thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer.
16. The method as claimed in 13, wherein the carrier layer of each patternable member includes a metal.
17. The method as claimed in claim 10 , wherein the carrier layer of each patternable member has unevenness of between about 0.1 micron and about 10 microns.
Priority Applications (1)
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US11/811,066 US20080128288A1 (en) | 2005-02-21 | 2007-06-08 | Method of manufacturing a multi-layer wiring board using a metal member having a rough surface |
Applications Claiming Priority (5)
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JP2005-43784 | 2005-02-21 | ||
JP2005043784A JP2006229115A (en) | 2005-02-21 | 2005-02-21 | Metal component used in manufacturing wiring substrate and method for manufacturing wiring substrate using it |
US35667206A | 2006-02-17 | 2006-02-17 | |
US58506406A | 2006-10-23 | 2006-10-23 | |
US11/811,066 US20080128288A1 (en) | 2005-02-21 | 2007-06-08 | Method of manufacturing a multi-layer wiring board using a metal member having a rough surface |
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US58506406A Continuation | 2005-02-21 | 2006-10-23 |
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US11/811,066 Abandoned US20080128288A1 (en) | 2005-02-21 | 2007-06-08 | Method of manufacturing a multi-layer wiring board using a metal member having a rough surface |
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US20110283535A1 (en) * | 2008-05-23 | 2011-11-24 | Shinko Electric Industries Co., Ltd. | Wiring board and method of manufacturing the same |
US20160242277A1 (en) * | 2015-02-12 | 2016-08-18 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and manufacturing method thereof |
US20160316558A1 (en) * | 2015-04-24 | 2016-10-27 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
ITUB20155408A1 (en) * | 2015-11-10 | 2017-05-10 | St Microelectronics Srl | PACKAGING SUBSTRATE FOR SEMICONDUCTOR, EQUIPMENT AND CORRESPONDENT PROCEDURES |
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US10257938B2 (en) | 2013-07-24 | 2019-04-09 | Jx Nippon Mining & Metals Corporation | Surface-treated copper foil, copper foil with carrier, substrate, resin substrate, printed wiring board, copper clad laminate and method for producing printed wiring board |
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