CN107105578A - It is a kind of to prepare two-sided and multilayer circuit plating stripping technology - Google Patents
It is a kind of to prepare two-sided and multilayer circuit plating stripping technology Download PDFInfo
- Publication number
- CN107105578A CN107105578A CN201710247628.5A CN201710247628A CN107105578A CN 107105578 A CN107105578 A CN 107105578A CN 201710247628 A CN201710247628 A CN 201710247628A CN 107105578 A CN107105578 A CN 107105578A
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- Prior art keywords
- circuit
- sided
- paper tinsel
- metal layer
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4658—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern characterized by laminating a prefabricated metal foil pattern, e.g. by transfer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0528—Patterning during transfer, i.e. without preformed pattern, e.g. by using a die, a programmed tool or a laser
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention prepares two-sided and multilayer circuit plating stripping technology to be a kind of.The idiographic flow of double-sided circuit can simply be summarized as on carrier metal paper tinsel line pattern on graphic plating, the adhesion of line pattern and base material and the stripping and drilling of carrier metal paper tinsel and the metallization step in hole.The idiographic flow of multilayer circuit is on the basis of double-sided circuit, can simply it be summarized as, carrier metal paper tinsel of the adhesion with circuitous pattern on the double-sided circuit of preparation, and peel off carrier metal paper tinsel formation third layer circuit, then the drilling and by hole metallization on third layer circuit, three layers of circuit are obtained, this process of repetition obtains more layers circuit.This technique is as a kind of additive process, and etching waste liquid is few, therefore pollution is few, and treatment cost of waste liquor is low, while avoiding circuit lateral erosion causes the problem of line width is limited, can prepare very fine circuitous pattern.
Description
Technical field
It is specially a kind of to prepare two-sided and multilayer circuit plating stripping technology the invention belongs to circuit manufacture field.
Background technology
Prepared by traditional circuit, including printed circuit board, flexible circuit board, electronic tag, IC support plates, sensor electricity
Prepared by the techniques that subtract into used based on metal etch such as road more, subtract into the specific steps of technique substantially：Covering Metal Substrate
The surface coating light sensitive layer of material pastes photosensitive dry film, and carries out selective exposure under the covering of photomask board, develops, cruelly
Expose metal foil logicalnot circuit figure position, then the metal of exposure portion is removed by way of etching, finally by circuit pack
Light sensitive layer or dry film remove, obtain required circuit.But this traditional subtractive process technique is the problem of have many.Carve
Erosion metal produces a large amount of waste liquids containing heavy metal, arbitrarily discharge meeting severe contamination environment, and the processing cost of waste liquid is also with ring
The lifting of guaranteed request and more and more higher.There are problems that lateral erosion in the etching process of metal foil, cause the line width of circuit to be restricted,
The preparation difficulty of less than 50 microns circuits is very big.
The additive process of printed circuit is supplemented as a kind of of technique is subtracted into, has been obtained for development for many years.Conventional
Several additive process, including semi-additive process, have printed the methods such as electrocondution slurry, printing electrically conductive ink, selective chemical plating
Through being applied.Semi-additive process is graphic plating technique, reduces the generation of etching waste liquid, while alleviating asking for lateral erosion
Topic, has been used among the preparation of high-precision circuit now.But semi-additive process has circuit poor adhesion, current density is difficult to
Uniformly, the problems such as part side etching phenomenon still has, causes yield relatively low.The method of printing electrocondution slurry and ink is avoided completely
The etching of metal foil, it is the most environmentally friendly, but printing electrocondution slurry and ink prepare circuit and there is poor electrical performance, printing precision is low
The problems such as, it is impossible to substitute simple metal circuit.Selective chemical plating, some people are also referred to as fully-additive process, it is to avoid quarter of metal foil
Erosion, in the absence of lateral erosion problem, but there is poor adhesion in electroless-deposited metal wire, and sedimentation rate is low, at plating wastewater
Can not be to subtracting into technique formation challenge from the point of view of the problems such as reason is difficult, short time.
There is the circuitous pattern between more than one layer of circuitous pattern, different layers to pass through metallization for double-sided circuit and multilayer circuit
Through hole, blind hole and buried via hole turned on, and its application exceeds well over single sided circuits.Prepare two-sided and multilayer circuit traditional work
Skill is divided into the preparation of conductive pattern and the metallization in hole, the preparation of conductive pattern and prepare single sided circuits subtract into technique substantially phase
Together, and the metallization in hole then it is mostly be based on roughening, sensitization, activation palladium chtalyst technique, and apply follow-up electroplating work procedure so that plating
Layer reaches required thickness.Among several additive process, semi-additive process can directly prepare two-sided and multilayer circuit, based on catalysis
The selective chemical plating method of property base material can also directly prepare two-sided and multilayer circuit, and other additive process based on printing are then
Two-sided and multilayer circuit can not directly be prepared.
In this application, it is proposed that a kind of to prepare two-sided and multilayer circuit plating stripping technology, graphic plating is used
Method prepares conductive pattern, and conductive pattern is transferred into substrate surface by peeling off, and uses traditional hole metallization technique
So that interlayer circuit turn-on.This technique need not use the method for etching to obtain circuit, therefore the problem of in the absence of circuit lateral erosion,
Very fine circuit can be prepared；The amount of metal of required etching is minimum, reduces waste liquid generation, reduces the cost of liquid waste processing,
It is suitable for the manufacture of high-precision two-sided and multilayer circuit.
The content of the invention
Two-sided and multilayer circuit additive process is prepared it is an object of the invention to provide a kind of, work is peeled off in referred to as plating
Skill.The obstructed over etching of this technique prepares circuit, the problem of without circuit lateral erosion, is wasted with low, low stain, bottom line is wide, circuit
The characteristics of electrical property and good adhesion.
Two-sided and multilayer circuit plating stripping technology is prepared the invention provides a kind of, is comprised the following steps that：
（1）The thin metal layer of below 10 microns of last layer is deposited on carrier metal paper tinsel surface by way of plating；
（2）Anti-plate mask is prepared using usual manner on thin metal layer surface, conductive circuit pattern position is exposed；
（3）By way of plating, the metallic conduction circuit on the conductive circuit pattern site deposition that thin metal layer surface exposes；
（4）Remove anti-plate mask on thin metal layer；
（5）By step（4）It is two-sided that there is the carrier metal paper tinsel of metallic conduction circuit to be bonded in circuit substrate on two pieces of obtained surfaces；
（6）Carrier metal paper tinsel is peeled off from circuit substrate, thin metal layer and on metallic conduction circuit can adhere to circuit
Base material is two-sided；
（7）The holes drilled through on circuit substrate, and turn on through hole by conventional hole metallization technique, connect two-sided conductor wire
Road；
（8）Thin metal layer is etched, retains the through hole of metal conducting wire and metallization, obtains double-sided circuit；
（9）On the basis of double-sided circuit, using the double-sided circuit of preparation as internal layer circuit, with step（4）Obtained surface tool
It is two-sided that the carrier metal paper tinsel for having metallic conduction circuit is bonded in second layer circuit substrate；
（10）Carrier metal paper tinsel is peeled off, thin metal layer and on metallic conduction circuit can adhere to second layer circuit substrate table
Face；
（11）Holes drilled through or blind hole on second layer circuit substrate, and lead through hole, blind hole by conventional hole metallization technique
It is logical；
（12）Thin metal layer is etched, retains the through hole or buried via hole of metal conducting wire and metallization, obtains three layers of circuit；
（13）Repeat step（9）-（12）, obtain more layers circuit.
In the present invention, step（1）In used carrier metal paper tinsel be in nickel, copper, titanium, chromium, stainless steel or filtter gold one
Kind.
In the present invention, step（1）The thin metal layer of middle electroplating deposition is one kind in copper, nickel, zinc, tin, chromium, iron or cobalt.
In the present invention, step（3）In the metallic conduction circuit that is deposited on thin metal layer surface be single metal or be multiple
Metal layer.
In the present invention, step（5）Described in circuit substrate be conventional use of hard or flexible base in circuit production
Material.
The beneficial effects of the present invention are：
1. a technique is compared to tradition " subtractive process " technique of circuit, it is not necessary to circuit is obtained by way of etching, it is to avoid
The problem of line width that circuit lateral erosion is brought is limited；
2. fine circuitry prepared by a technique can be buried among base material, the adhesion of circuit and base material is added, so as to solve
The adhesion problem of half additive process generally existing.
Brief description of the drawings
Fig. 1 is described prepares two-sided and multilayer circuit idiographic flow using plating stripping technology.In carrier metal paper tinsel 1
Surface prepares thin metal layer 2. by way of plating, and carrier metal paper tinsel typically can carry out insulation processing in another side here, mainly
Mode can be bonding last layer insulation film, coated using coatings.Carrier metal paper tinsel thickness preferably 20 to 100 is micro-
It is too thin electroplating current density to be caused uneven between rice, it is too thick, difficulty can be caused to follow-up stripping process.In thin gold
Category layer 2 surface prepares anti-plate mask 3, retains circuit graphics field, preferably most traditional to paste photosensitive dry film, and passes through light
The mode that mask plate is exposed is carried out.Then by way of plating, species and thickness needed in the deposition of the surface of thin metal layer 2
The conductive pattern coating 4 of degree, and anti-plate mask 3 is removed.The carrier of line pattern needed for double-sided circuit two sides is prepared
After paper tinsel, thin metal layer 2 and conductive pattern coating 4 are bonded in one with circuit substrate 5 used by two carrier metal paper tinsels 1 and thereon
Rise, here the main mode using hot pressing, in conventional circuit substrate, such as itself there is the epoxy prepreg of bond properties
Or itself do not possess bond properties, but can be by coating traditional binders on surface obtaining the base of bond properties
Carrier foils on material, such as polyimides, the both-sided adhesive of polyethylene terephthalate etc..By carrier metal paper tinsel 1 from circuit
The sur-face peeling of base material 5, here, due to the special nature on the surface of carrier metal paper tinsel used so that carrier metal paper tinsel 1 and thin gold
The adhesion belonged between layer 2 is very low, more easily can peel off carrier metal paper tinsel 1.The carrier metal paper tinsel 1 peeled off can be weighed
Telegram in reply plating is used.And peel off after carrier metal paper tinsel 1, thin metal layer 2 will expose outside, play a part of monolithic conductive.Institute
Need position to carry out machinery or laser drill, obtain through hole 6, then deposit the inwall in hole using conventional hole metallization mode
Layer of metal, is turned on through hole.Hole metallization mode used herein can be most-often used palladium activating chemical copper facing
Bottoming, the mode of coordination galvanization copper or more novel direct colloid palladium plating, " black holes " electroplating technique.Obtaining
After the through hole that must be metallized, thin metal layer 2 is etched away using the mode of etching, so that conductive pattern coating 4 be exposed
Come.It is therefore preferable that different thin metal layers 2 and the material of conductive pattern coating 4 so that specific etching liquid can etch away Bao Jin
Belong to layer 2, but not or seldom etching conductive figure coating 4. here can also thin metal layer 2 and conductive pattern coating 4 it
Between deposition last layer thin corrosion resistant metal layer, so, can also be etched even if the metal used in conductive pattern coating 4 by specific etching liquid
Fall, due to the presence of this layer thin corrosion resistant metal layer so that it can obtain complete guarantor after thin metal layer 2 is etched completely
Deposit.So, required double-sided circuit has just been obtained.
And multilayer circuit is then based on double-sided circuit, by internal layer double-sided circuit, second layer circuit substrate and with
The carrier metal paper tinsel of three layers of conductive pattern coating is bonded together, and carrier metal paper tinsel is peeled off.The position needed for circuit substrate
Holes drilled through or blind hole, and the coat of metal is deposited on through hole or blind pore wall by traditional hole metallization mode, so that
Turn on the circuit of third layer circuit and internal layer.Third layer thin metal layer is etched, three layers of circuit have just been obtained.And the electricity of more layers
Road can repeat the acquisition of this process.
Embodiment
Example below is that the present invention is further illustrated, rather than limitation the scope of the present invention.
Embodiment 1：
(1) 50 microns of nickel purchased in market is thin as carrier metal paper tinsel, in the 50 microns thick PET film of nickel foil one side bonding, by nickel foil one side
Exposure is outside；
(2) 2g/L sodium dodecyl sulfate solution is prepared, pH is adjusted to 9-10 with sodium hydroxide, obtains degreasing fluid.By carrier
Metal foil immersion degreasing fluid in 50 degree it is ultrasonically treated 5 minutes, cleaned after taking-up with clear water, and drying；
(3) cleaned and dried with clear water after plating as thin metal layer in the microns thickness bright copper of nickel foil electroplating surface 3, light
Bright copper electrolyte composition is as shown in table 1；
The bright copper solution composition of table 1
| Cupric pyrophosphate | 80 g/L |
| Potassium pyrophosphate | 300 g/L |
| Ammoniacal liquor | 5 ml/L |
| Brightener | 2 ml/L |
| Temperature | 50 degree |
| Current density | 2 A/dm2 |
(4) anti-plate photosensitive dry film is pasted on thin metal layer surface, and using conventional exposure imaging flow, obtains anti-plate and covers
Film；
(5) carrier metal paper tinsel is immersed in nickel plating solution, 1 micron thickness or so in plating under the covering of anti-plate mask
Nickel, is then immersed in copper electroplating solution, and the layers of copper of thickness, obtains circuitous pattern, electronickelling and electro-coppering institute needed for continuing plating
With solution composition as shown in table 2 and table 3；
The electronickelling solution composition of table 2
| Nickel sulfamic acid | 500 g/L |
| Lauryl sodium sulfate | 1 g/L |
| Temperature | 50 degree |
| Current density | 10 A/dm2 |
The electro-coppering solution composition of table 3
| Copper sulphate | 100 g/L |
| Sulfuric acid | 75 g/L |
| Chlorion | 150 ppm |
| Temperature | 45 degree |
| Current density | 10 A/dm2 |
(6) the anti-plate mask on the carrier metal paper tinsel surface after plating circuit figure is removed；
(7) another piece of carrier metal paper tinsel is passed through（1）-（6）Flow handled, obtain the circuitous pattern on dual platen two sides,
By the carrier metal paper tinsel hot pressing with two sides circuitous pattern on FR-4 prepreg base materials two sides, heating makes prepreg completely solid
Change；
(8) carrier metal paper tinsel is peeled off from the FR-4 substrate surfaces after solidification, then by way of machine drilling, in base material
Bore 300 micron diameter vias in position needed for surface；
(9) using conventional palladium activation method, then the 1 microns layers of copper in chemical plating on through hole hole wall uses plating side
Formula, makes layers of copper thicken to 10 microns, such as institute of table 4 of chemical bronze plating liquid composition used in electroless copper with copper electrolyte is electroplated in table 3
Show；
The chemical bronze plating liquid composition of table 4
| Copper sulphate | 15 g/L |
| EDETATE SODIUM | 20 g/L |
| Sodium hydroxide | 18 g/L |
| Formaldehyde | 15 ml/L |
| Temperature | 45 degree |
(10) base material after hole metallization is immersed in copper etching liquid, thin metal layer is etched away, underlying conductive circuit is exposed,
Copper etching liquid composition used in double-sided circuit needed for obtaining is as shown in table 5；
The bronze medal etching liquid composition of table 5
| Copper chloride | 120 g/L |
| Ammonium chloride | 100 g/L |
| Ammoniacal liquor | 700 ml/L |
| Temperature | 50 degree |
Embodiment 2：
Double-sided circuit prepared by embodiment 1 as multilayer circuit internal layer circuit, by double-sided circuit with according to the step of embodiment 1
（1）-（6）The carrier metal paper tinsel that there is third layer circuitous pattern on the surface of preparation is bonded to second layer FR-4 bases by way of hot pressing
On material, then carrier metal paper tinsel is peeled off, 300 micron diameter vias are bored at required position using machine drilling（Blind hole then can be with
By way of laser drill）, and use the step of embodiment 1（9）Mode make hole metallization, connect different layers circuit, then make
With the step of embodiment 1（10）Mode thin metal layer is etched away so that three layers of circuit needed for obtaining.
Claims (5)
1. a kind of prepare two-sided and multilayer circuit plating stripping technology, it is characterised in that comprises the following steps that：
（1）The thin metal layer of below 10 microns of last layer is deposited on carrier metal paper tinsel surface by way of plating；
（2）Anti-plate mask is prepared using usual manner on thin metal layer surface, conductive circuit pattern position is exposed；
（3）By way of plating, the metallic conduction circuit on the conductive circuit pattern site deposition that thin metal layer surface exposes；
（4）Remove anti-plate mask on thin metal layer；
（5）By step（4）It is two-sided that there is the carrier metal paper tinsel of metallic conduction circuit to be bonded in circuit substrate on two pieces of obtained surfaces；
（6）Carrier metal paper tinsel is peeled off from circuit substrate, thin metal layer and on metallic conduction circuit can adhere to circuit
Base material is two-sided；
（7）The holes drilled through on circuit substrate, and turn on through hole by conventional hole metallization technique, connect two-sided conductor wire
Road；
（8）Thin metal layer is etched, retains the through hole of metal conducting wire and metallization, obtains double-sided circuit；
（9）On the basis of double-sided circuit, using the double-sided circuit of preparation as internal layer circuit, with step（4）Obtained surface tool
It is two-sided that the carrier metal paper tinsel for having metallic conduction circuit is bonded in second layer circuit substrate；
（10）Carrier metal paper tinsel is peeled off, thin metal layer and on metallic conduction circuit can adhere to second layer circuit substrate table
Face；
（11）Holes drilled through or blind hole on second layer circuit substrate, and lead through hole, blind hole by conventional hole metallization technique
It is logical；
（12）Thin metal layer is etched, retains the through hole or buried via hole of metal conducting wire and metallization, obtains three layers of circuit；
（13）Repeat step（9）-（12）, obtain more layers circuit.
A kind of two-sided and multilayer circuit plating stripping technology is prepared 2. according to claim 1, it is characterised in that step
（1）In used carrier metal paper tinsel be one kind in nickel, copper, titanium, chromium, stainless steel or filtter gold.
A kind of two-sided and multilayer circuit plating stripping technology is prepared 3. according to claim 1, it is characterised in that step
（1）The thin metal layer of middle electroplating deposition is one kind in copper, nickel, zinc, tin, chromium, iron or cobalt.
A kind of two-sided and multilayer circuit plating stripping technology is prepared 4. according to claim 1, it is characterised in that step
（3）In the metallic conduction circuit that is deposited on thin metal layer surface be single metal or be complex metal layer.
A kind of two-sided and multilayer circuit plating stripping technology is prepared 5. according to claim 1, it is characterised in that step
（5）Described in circuit substrate be circuit production in conventional use of hard or flexible parent metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710247628.5A CN107105578A (en) | 2017-04-17 | 2017-04-17 | It is a kind of to prepare two-sided and multilayer circuit plating stripping technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710247628.5A CN107105578A (en) | 2017-04-17 | 2017-04-17 | It is a kind of to prepare two-sided and multilayer circuit plating stripping technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107105578A true CN107105578A (en) | 2017-08-29 |
Family
ID=59676162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710247628.5A Pending CN107105578A (en) | 2017-04-17 | 2017-04-17 | It is a kind of to prepare two-sided and multilayer circuit plating stripping technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107105578A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111328206A (en) * | 2020-03-06 | 2020-06-23 | 柏承科技(昆山)股份有限公司 | Method for manufacturing printed circuit board with low cost and high processing capacity |
| WO2021184231A1 (en) * | 2020-03-18 | 2021-09-23 | 柏承科技(昆山)股份有限公司 | Low-cost and high-process-capability printed circuit board manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0545328A2 (en) * | 1991-11-29 | 1993-06-09 | Hitachi Chemical Co., Ltd. | Printed circuit board manufacturing process |
| CN1333649A (en) * | 2000-02-09 | 2002-01-30 | 松下电器产业株式会社 | Duplicated material and making method thereof, and distribution substrate made of same |
| WO2006042029A2 (en) * | 2004-10-06 | 2006-04-20 | Tessera Interconnect Materials, Inc. | Structure and method of making interconnect element having metal traces embedded in surface of dielectric |
| CN1842254A (en) * | 2005-03-29 | 2006-10-04 | 日立电线株式会社 | Double-sided wiring board fabrication method, double-sided wiring board, and base material therefor |
| US20080128288A1 (en) * | 2005-02-21 | 2008-06-05 | Tessera Interconnect Materials, Inc. | Method of manufacturing a multi-layer wiring board using a metal member having a rough surface |
-
2017
- 2017-04-17 CN CN201710247628.5A patent/CN107105578A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0545328A2 (en) * | 1991-11-29 | 1993-06-09 | Hitachi Chemical Co., Ltd. | Printed circuit board manufacturing process |
| CN1333649A (en) * | 2000-02-09 | 2002-01-30 | 松下电器产业株式会社 | Duplicated material and making method thereof, and distribution substrate made of same |
| WO2006042029A2 (en) * | 2004-10-06 | 2006-04-20 | Tessera Interconnect Materials, Inc. | Structure and method of making interconnect element having metal traces embedded in surface of dielectric |
| US20080128288A1 (en) * | 2005-02-21 | 2008-06-05 | Tessera Interconnect Materials, Inc. | Method of manufacturing a multi-layer wiring board using a metal member having a rough surface |
| CN1842254A (en) * | 2005-03-29 | 2006-10-04 | 日立电线株式会社 | Double-sided wiring board fabrication method, double-sided wiring board, and base material therefor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111328206A (en) * | 2020-03-06 | 2020-06-23 | 柏承科技(昆山)股份有限公司 | Method for manufacturing printed circuit board with low cost and high processing capacity |
| CN111328206B (en) * | 2020-03-06 | 2022-08-09 | 柏承科技(昆山)股份有限公司 | Method for manufacturing printed circuit board |
| WO2021184231A1 (en) * | 2020-03-18 | 2021-09-23 | 柏承科技(昆山)股份有限公司 | Low-cost and high-process-capability printed circuit board manufacturing method |
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Application publication date: 20170829 |