CN104703401A - Circuit board electroplating method - Google Patents
Circuit board electroplating method Download PDFInfo
- Publication number
- CN104703401A CN104703401A CN201310672062.2A CN201310672062A CN104703401A CN 104703401 A CN104703401 A CN 104703401A CN 201310672062 A CN201310672062 A CN 201310672062A CN 104703401 A CN104703401 A CN 104703401A
- Authority
- CN
- China
- Prior art keywords
- plating
- line layer
- circuit board
- dielectric
- coating region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a circuit board electroplating method, aiming to overcome the defects of an existing graphic pre-gold-plating technology and an existing local gold-plating technology by a thin-copper method. The circuit board electroplating method is used for processing circuit boards with requirements on high-density circuits and high-precision size. The circuit board electroplating method includes the steps of processing a surface metal layer on a circuit board to a circuit layer; etching and thinning a non-electroplating area of the circuit layer; arranging insulating media in the etched and thinned non-electroplating area; electroplating an electroplating area of the circuit layer.
Description
Technical field
The present invention relates to circuit board technology field, be specifically related to a kind of electro-plating method of circuit board.
Background technology
In circuit board processing technology, there is a kind of technique of circuit board top layer pad (PAD) or circuit being carried out to gold-plated process, to play the wear-resistant effect with beating gold thread.Before this craft of gilding adopts figure usually, craft of gilding or thin copper method partially plating gold technique realize.
Before figure, craft of gilding is before making surface lines figure, with large copper face as glodclad wire, covers other region with dry film, carries out gold-plated to needs plating area.But craft of gilding has following defect before figure, more and more higher gold-plated requirement can not be met.
A, gold-plated plating and etching are unclean.In the electroless coating region that dry film covers, because the adhesion of dry film and copper face is large not, time gold-plated, around plating area, dry film easily comes off or under liquid medicine easily infiltrates dry film, cause and occur plating gold with the large copper face be connected around plating area, it is clean that the copper face that these ooze plating area when subsequent etch is difficult to etching.
B, plating area subside.Because be connected with large copper face around plating area, when subsequent etch finished surface line pattern, the layers of copper below plating area is easily snapped eating away, occurs that plating area subsides.
C, plating short circuit.Plating short circuit is easily there is when circuit board surface circuit is closeer.
Therefore, before figure, craft of gilding does not process high-density line, can not production high accuracy size circuit plate.
Thin copper method partially plating gold technique first on the surface metal-layer of circuit board, produces surface lines figure, again heavy copper is carried out to whole surface metal-layer, then, utilize heavy layers of copper as glodclad wire, cover other region with dry film, carry out gold-plated to needs plating area; Gold-plated complete, remove heavy layers of copper.But thin copper method partially plating gold technique has following defect:
A, produce surface lines figure surface metal-layer on rough and uneven in surface, easily cause dry film fold even damaged when covering dry film, make the region that should not be plated gold-plated;
The base material that b, heavy process for copper can expose at trace clearance adheres to layer of metal palladium, and this layer of Metal Palladium is difficult to be efficiently removed, follow-uply likely causes top layer line pattern short circuit.
Summary of the invention
The embodiment of the present invention provides a kind of electro-plating method of circuit board, to solve the above-mentioned defect that craft of gilding and thin copper method partially plating gold technique exist before existing figure, has the circuit board of high-density line and high accuracy dimensional requirement for processing.
The electro-plating method of circuit board provided by the invention, comprising: the surface metal-layer of circuit board is processed as line layer; The etching of the electroless coating region of described line layer is subtracted thick; Subtract thick described electroless coating region dielectric is set etching; The plating area of described line layer is electroplated.
Therefore, after the embodiment of the present invention adopts and processes top layer line layer, the etching of the electroless coating region of line layer is subtracted thick and arranges dielectric protection, then, to the technical scheme that the plating area of line layer is electroplated, achieves following technique effect:
Relative to electroplating technology before existing figure, after plating step is placed on line pattern step, and the surrounding of plating area is not large copper face but dielectric, the only circuit top surface that plating area is exposed, therefore, gold-plated infiltration can be avoided and etching is clean and plating area subsides and the problem such as plating short circuit.
Relative to thin copper method partially plating gold technique, because electroless coating region has been set up dielectric, be no longer scraggly circuit, therefore, the plating resist film covered can not fold or breakage, and heavy layers of copper and line layer are kept apart by dielectric, can not cause line pattern short circuit because heavy layers of copper is residual.
Visible, the above-mentioned defect that before technical solution of the present invention solves figure, electroplating technology and thin copper method partially plating gold technique exist, can process and have more highdensity line pattern, can produce the circuit board with high accuracy size.
Accompanying drawing explanation
In order to be illustrated more clearly in embodiment of the present invention technical scheme, be briefly described to the accompanying drawing used required in embodiment and description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of the electro-plating method of the circuit board that one embodiment of the invention provides;
Fig. 2 is the schematic diagram of the electro-plating method of the circuit board that another embodiment of the present invention provides;
Fig. 3 a-3i is the schematic diagram of circuit board in each step of embodiment of the present invention method.
Embodiment
The embodiment of the present invention provides a kind of electro-plating method of circuit board, to solve the above-mentioned defect that craft of gilding and thin copper method partially plating gold technique exist before existing figure, has the circuit board of high-density line and high accuracy dimensional requirement for processing.
The present invention program is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the embodiment of a part of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, should belong to the scope of protection of the invention.
Below by specific embodiment, be described in detail respectively.
Please refer to Fig. 1, the embodiment of the present invention provides a kind of electro-plating method of circuit board, can comprise:
110, the surface metal-layer of circuit board is processed as line layer.
In the present embodiment, said circuit board can be single-side coated copper plate, or double face copper, also can based on the multi-layer sheet of single or double copper-clad plate lamination, and for the concrete structure and preparation method thereof of this circuit board, the embodiment of the present invention will not limit.General, this circuit board comprises at least one layer insulating and at least one deck metal level.Embodiment of the present invention method for electroplating on the surface metal-layer of this circuit board.
In the present embodiment, first the surface metal-layer of circuit board one or both sides is processed as line layer.Wherein, technique surface metal-layer being processed as line layer can adopt conventional process technology, and the embodiment of the present invention will not limit this.On the line layer that surface metal-layer processes, need the region of carrying out electroplating, be called plating area, specifically can comprise some pad or circuits etc.; Other does not need the region of carrying out electroplating, be then called electroless coating region.
120, the etching of the electroless coating region of described line layer is subtracted thick.
In this step, the electroless coating region etching on the line layer of circuit board top layer is subtracted thick, makes plating area higher than electroless coating region.General, the etching of the copper thickness in electroless coating region can be reduced to close to or only slight beyond the half of original thickness.Wherein, etching subtracts thick step and can comprise:
Etchant resist is covered in the plating area of line layer; Carrying out etching to the electroless coating region of the not capped etchant resist of line layer subtracts thick; Remove etchant resist.
Wherein, said etchant resist can be specifically dry film against corrosion or wet film against corrosion.The said plating area at line layer covers etchant resist and can comprise: after the full surface coverage etchant resist of line layer, is removed by the etchant resist in electroless coating region, only retain the etchant resist of plating area by exposure and development operation.The electroless coating region of the said not capped etchant resist to line layer is carried out etching and is subtracted thick comprising: the circuit board covering etchant resist is placed in electroplating bath, takes out, detect whether reach requirement after energising plating setting-up time.Said removal etchant resist can comprise: remove etchant resist by methods such as alkali etchings.
In a kind of execution mode, the thickness of the surface metal-layer of circuit board can be 3-5 ounce (OZ, 1OZ approximate 35 microns), such as 4OZ, accordingly, the etching of the electroless coating region of described line layer is subtracted thick comprising: subtract thick in 1-2 ounce by the etching of the electroless coating region of described line layer.
130, subtract thick described electroless coating region dielectric is set etching.
In this step, subtracting thick electroless coating region dielectric be set etching at circuit board top layer line layer, but expose plating area, and set dielectric is concordant with the line layer surface of plating area.In the embodiment of the present invention, the step arranging dielectric can comprise:
Lamination dielectric on line layer; Remove the top layer of dielectric, make dielectric concordant with the surface, plating area of line layer, to expose plating area.
Wherein, can slot, so that lamination in the position corresponding to plating area of dielectric in advance.Said dielectric can be specifically prepreg, that is, the PP sheet often said, and PP sheet is one of main material during multi-layer sheet is produced, and form primarily of resin and reinforcing material, reinforcing material is divided into again the several types such as glass-fiber-fabric, paper substrate, composite material.The top layer of said removal dielectric, can being removed by the dark miller skill of control, by controlling the degree of depth of the dark milling of control, the part exceeding plating area of dielectric being removed.
In some embodiments of the invention, in order to ensure lamination, in concrete lamination process, dielectric can be set above line layer, one deck false central layer be then set above dielectric, then carry out lamination.Said false central layer is also one deck insulating material, but its hardness is greater than prepreg.This false central layer, only for auxiliary lamination, can't really be pressed on circuit board, or, even if this press on circuit board, is also removed by techniques such as the dark millings of control.
140, the plating area of described line layer is electroplated.
Through above-mentioned dielectric step is set after, circuit board surface comprises two regions, and one is plating area, expose in this region need plating line layer; Another is non-plating area, and this region is covered by insulating resin, and the line pattern in this region is all positioned at below insulating resin, and does not come out.
In this step, electroplate the plating area of the line layer come out, said plating can be electrogilding, nickel gold or NiPdAu etc.This plating step can comprise:
Heavy layers of copper is generated at circuit board surface; At the electroless coating region overlay plating resist film of circuit board surface; The plating area not covering plating resist film is electroplated; Remove the heavy layers of copper in plating resist film and electroless coating region.
Wherein, adopt heavy process for copper in the electroless coating region on the heavy layers of copper covering board surface that circuit board surface generates and plating area, the heavy layers of copper of generation will be used in following electroplating process as electroplate lead wire.Usually heavy layers of copper is very thin one deck, in order to improve reliability, after the heavy layers of copper of generation, can also increase plating step, so as in heavy layers of copper regeneration electrodeposited coating (can be described as heavy copper electrodeposited coating).The gross thickness of this heavy layers of copper and electrodeposited coating can between 5-10 micron, to ensure to play good conductive effect.
The electroless coating region overlay plating resist film of said circuit board surface can comprise: after circuit board full surface coverage plating resist film, the plating resist film of plating area is removed by exposure and development operation, only retain the plating resist film in electroless coating region, that is, the plating resist film on set dielectric is only retained.
The said plating area to not covering plating resist film is electroplated and specifically be can be: with heavy layers of copper or heavy copper electrodeposited coating for electroplate lead wire, to plating area electrogilding, nickel gold or NiPdAu etc.
Electroplate complete, remove the heavy layers of copper in plating resist film and electroless coating region by alkali etching technique.
Above; embodiments provide a kind of electro-plating method of circuit board; after the method adopts and processes top layer line layer; the etching of the electroless coating region of line layer is subtracted thick and arranges dielectric protection; then; to the technical scheme that the plating area of line layer is electroplated, achieve following technique effect:
Relative to electroplating technology before existing figure, after plating step is placed on line pattern step, and the surrounding of plating area is not large copper face but dielectric, the only circuit top surface that plating area is exposed, therefore, gold-plated infiltration can be avoided and etching is clean and plating area subsides and the problem such as plating short circuit.
Relative to thin copper method partially plating gold technique, because electroless coating region has been set up dielectric, be no longer scraggly circuit, therefore, the plating resist film covered can not fold or breakage, and heavy layers of copper and line layer are kept apart by dielectric, can not cause line pattern short circuit because heavy layers of copper is residual.
Visible, the above-mentioned defect that before technical solution of the present invention solves figure, electroplating technology and thin copper method partially plating gold technique exist, can process and have more highdensity line pattern, can produce the circuit board with high accuracy size.
For ease of better understanding the technical scheme that the embodiment of the present invention provides, be that example is introduced below by the execution mode under a concrete scene.
Please refer to Fig. 2, the electro-plating method of the another kind of circuit board of the embodiment of the present invention, can comprise:
201, as best shown in figures 3 a and 3b, the surface metal-layer of circuit board 300 produces line layer 310.This line layer 310 comprises the gold-plated plating area of needs 301 and does not need gold-plated electroless coating region 302.The thickness of this line layer is assumed to 4OZ.Before making line layer 310, if the thickness of surface metal-layer is less than 4OZ, by electroplating surface mode, surface metal-layer plating can be thickeied to 4OZ.
202, as shown in Figure 3 c, the plating area of line layer 310 dry film 401 against corrosion is covered, but exposes electroless coating region.
203, as shown in Figure 3 d, adopt etch process the etching of electroless coating region to be subtracted and thickly after 1-2OZ, remove dry film 401 against corrosion.
204, as shown in Figure 3 e, pressing dielectric 320 on line layer 310, the position corresponding to plating area of this dielectric 320 has fluting.
205, as illustrated in figure 3f, adopt the dark miller skill of whole plate control, ream the top layer resin of dielectric 320, until expose the plating area of line layer 310, electroless coating region is not then exposed by dielectric 320 covering protection.
206, as shown in figure 3g, adopt heavy copper-electroplating technology, sink copper and plating at the whole plate of circuit board surface, form the metal level 330 that comprises heavy layers of copper and electrodeposited coating, the copper of this metal level is thick can be 5-10um.
207, as illustrated in figure 3h, adopt plating resist dry film 402 to cover electroless coating region, expose plating area, then, with metal level 330 for electroplate lead wire, normal electrogilding, nickel gold or NiPdAu are carried out to plating area, forms electrodeposited coating 340.
208, as shown in figure 3i, electroplated rear removal plating resist dry film 402, it is the metal level of 5-10um that alkali etching technique of going further removes electroless coating area thickness, namely obtains required circuit board.
Therefore, in feasible execution modes more of the present invention, after processing top layer line layer, the etching of the electroless coating region of line layer is subtracted thick and arranges dielectric protection, then, the plating area of line layer is electroplated, because the surrounding of plating area is not large copper face but dielectric, therefore, gold-plated infiltration can be avoided and etching is clean and plating area subsides and the problem such as plating short circuit; Because electroless coating region has been set up dielectric, be no longer scraggly circuit, therefore, the plating resist film of covering can not fold or breakage, and heavy layers of copper and line layer are kept apart by dielectric, can not cause line pattern short circuit because heavy layers of copper is residual.Visible, the above-mentioned defect that before technical solution of the present invention solves figure, electroplating technology and thin copper method partially plating gold technique exist, can process and have more highdensity line pattern, can produce the circuit board with high accuracy size.
In the above-described embodiments, the description of each embodiment is all emphasized particularly on different fields, in certain embodiment, there is no the part described in detail, can see the associated description of other embodiment.
It should be noted that, for aforesaid each embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not by the restriction of described sequence of movement, because according to the present invention, some step can adopt other order or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in specification all belongs to preferred embodiment, and involved action and module might not be that the present invention is necessary.
Above the electro-plating method of the circuit board that the embodiment of the present invention provides is described in detail, but the explanation of above embodiment just understands method of the present invention and core concept thereof for helping, and should not be construed as limitation of the present invention.Those skilled in the art, according to thought of the present invention, in the technical scope that the present invention discloses, the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.
Claims (10)
1. an electro-plating method for circuit board, is characterized in that, comprising:
The surface metal-layer of circuit board is processed as line layer;
The etching of the electroless coating region of described line layer is subtracted thick;
Subtract thick described electroless coating region dielectric is set etching;
The plating area of described line layer is electroplated.
2. method according to claim 1, is characterized in that, described etching in the electroless coating region of described line layer subtracts thick comprising:
Etchant resist is covered in the plating area of described line layer;
Carrying out etching to the electroless coating region of the not capped etchant resist of described line layer subtracts thick;
Remove described etchant resist.
3. method according to claim 1 and 2, is characterized in that, the thickness of described surface metal-layer is 3-5 ounce, and accordingly, described etching in the electroless coating region of described line layer subtracts thick comprising:
The etching of the electroless coating region of described line layer is subtracted thick in 1-2 ounce.
4. method according to claim 1, is characterized in that, describedly subtracts thick described electroless coating region and arranges dielectric and comprise etching:
Lamination dielectric on described line layer;
Remove the top layer of described dielectric, make described dielectric concordant with the surface, plating area of described line layer, to expose described plating area.
5. method according to claim 4, is characterized in that, describedly also comprises before lamination dielectric on described line layer:
Slot in the position corresponding to described plating area of described dielectric.
6. method according to claim 4, is characterized in that, described dielectric comprises prepreg.
7. method according to claim 4, is characterized in that, adopts the dark miller skill of control to remove the top layer of described dielectric.
8. method according to claim 1, is characterized in that, the described plating area to described line layer is carried out plating and comprised:
Heavy layers of copper is generated at described circuit board surface;
At the electroless coating region overlay plating resist film of described circuit board surface;
The plating area not covering plating resist film is electroplated;
Remove the heavy layers of copper in described plating resist film and described electroless coating region.
9. method according to claim 8, is characterized in that, the described plating area to not covering plating resist film is carried out plating and comprised:
Electrogilding, nickel gold or NiPdAu are carried out to the plating area not covering plating resist film.
10. method according to claim 8, is characterized in that, adopts alkali etching technique to remove the heavy layers of copper in described electroless coating region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310672062.2A CN104703401B (en) | 2013-12-10 | 2013-12-10 | A kind of electro-plating method of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310672062.2A CN104703401B (en) | 2013-12-10 | 2013-12-10 | A kind of electro-plating method of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104703401A true CN104703401A (en) | 2015-06-10 |
| CN104703401B CN104703401B (en) | 2018-08-03 |
Family
ID=53350052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310672062.2A Active CN104703401B (en) | 2013-12-10 | 2013-12-10 | A kind of electro-plating method of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104703401B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106191935A (en) * | 2016-08-11 | 2016-12-07 | 强半导体（苏州）有限公司 | Electrogilding technique for chip testing connecting plate |
| CN107920427A (en) * | 2016-10-09 | 2018-04-17 | 北大方正集团有限公司 | The preparation method and printed circuit board (PCB) of the metal connecting structure of circuit board |
| CN109994660A (en) * | 2019-03-15 | 2019-07-09 | 福建南平南孚电池有限公司 | A kind of rechargeable battery with improved circuit unit |
| CN110602889A (en) * | 2019-10-21 | 2019-12-20 | 深圳市中基自动化有限公司 | Contact circuit board process for lithium battery formation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200304351A (en) * | 2003-04-29 | 2003-09-16 | Mutual Tek Ind Co Ltd | Manufacturing method of thin integrated circuit with multi-layered circuit |
| US20050124096A1 (en) * | 1997-11-12 | 2005-06-09 | International Business Machines Corporation | Manufacturing methods for printed circuit boards |
| CN102373492A (en) * | 2010-08-13 | 2012-03-14 | 北大方正集团有限公司 | Method for carrying out selective electroplating on surface of circuit board, and circuit board |
-
2013
- 2013-12-10 CN CN201310672062.2A patent/CN104703401B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050124096A1 (en) * | 1997-11-12 | 2005-06-09 | International Business Machines Corporation | Manufacturing methods for printed circuit boards |
| TW200304351A (en) * | 2003-04-29 | 2003-09-16 | Mutual Tek Ind Co Ltd | Manufacturing method of thin integrated circuit with multi-layered circuit |
| CN102373492A (en) * | 2010-08-13 | 2012-03-14 | 北大方正集团有限公司 | Method for carrying out selective electroplating on surface of circuit board, and circuit board |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106191935A (en) * | 2016-08-11 | 2016-12-07 | 强半导体（苏州）有限公司 | Electrogilding technique for chip testing connecting plate |
| CN107920427A (en) * | 2016-10-09 | 2018-04-17 | 北大方正集团有限公司 | The preparation method and printed circuit board (PCB) of the metal connecting structure of circuit board |
| CN107920427B (en) * | 2016-10-09 | 2020-07-14 | 北大方正集团有限公司 | Preparation method of metal connection structure of circuit board and printed circuit board |
| CN109994660A (en) * | 2019-03-15 | 2019-07-09 | 福建南平南孚电池有限公司 | A kind of rechargeable battery with improved circuit unit |
| CN109994660B (en) * | 2019-03-15 | 2023-12-05 | 福建南平南孚电池有限公司 | Rechargeable battery with improved circuit unit |
| CN110602889A (en) * | 2019-10-21 | 2019-12-20 | 深圳市中基自动化有限公司 | Contact circuit board process for lithium battery formation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104703401B (en) | 2018-08-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103619125B (en) | A kind of PCB electro-plating method for improving electroplating evenness | |
| CN108617104B (en) | Method for manufacturing printed circuit board with thickened copper local pattern | |
| KR100632577B1 (en) | Electrolytic gold plating method of printed circuit board | |
| CN102316677B (en) | Electroplating method for double-side and multilayer flexible printed circuit board | |
| CN104918421A (en) | Manufacturing method for PCB golden finger | |
| CN105704948B (en) | The production method of ultra-thin printed circuit board and ultra-thin printed circuit board | |
| CN102569171A (en) | Wiring structure for improving crown-like defect and fabrication method thereof | |
| TWI492690B (en) | Method for manufacturing circuit board | |
| CN112788857A (en) | Circuit board fine circuit processing method | |
| CN104703401A (en) | Circuit board electroplating method | |
| CN112312662A (en) | Manufacturing method of fine circuit printed circuit board | |
| CN113056116A (en) | Method for plating hole copper and processing method of circuit board | |
| KR20140101260A (en) | Multi-layer flexible circuit board and process for producing the same | |
| KR101287761B1 (en) | Printed circuit board and method for manufacturing the same | |
| CN111787708A (en) | Manufacturing method of high-low copper PAD circuit board | |
| CN101442885A (en) | Method for preparing circuit board guide hole | |
| CN104684265A (en) | Method for electroplating surface of circuit board | |
| US8074352B2 (en) | Method of manufacturing printed circuit board | |
| CN104105354A (en) | Method of manufacturing high-aperture ratio fine printed circuit board | |
| JP2008004862A (en) | Printed circuit board and method for manufacturing it | |
| CN110545634A (en) | Manufacturing method of multilayer fine circuit board with circuit being firstly made and then plated with hole copper | |
| KR100990575B1 (en) | Printed circuit board having fine pattern and manufacturing method of the same | |
| JP4137279B2 (en) | Printed wiring board and manufacturing method thereof | |
| CN102131346A (en) | Circuit board and manufacturing process thereof | |
| CN103354702B (en) | The circuit board that microwave circuit board manufacturing method and the method make |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518053 No. 99 East Qiaocheng Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN SHENNAN CIRCUIT CO., LTD. Address before: 518053 No. 99 East Qiaocheng Road, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Shennan Circuits Co., Ltd. |
|
| CP01 | Change in the name or title of a patent holder |