JPH05183259A - Manufacture of high density printed wiring board - Google Patents

Manufacture of high density printed wiring board

Info

Publication number
JPH05183259A
JPH05183259A JP36014591A JP36014591A JPH05183259A JP H05183259 A JPH05183259 A JP H05183259A JP 36014591 A JP36014591 A JP 36014591A JP 36014591 A JP36014591 A JP 36014591A JP H05183259 A JPH05183259 A JP H05183259A
Authority
JP
Japan
Prior art keywords
plating
conductor circuit
circuit pattern
resist
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP36014591A
Other languages
Japanese (ja)
Inventor
Nobuhito Hayashi
信人 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP36014591A priority Critical patent/JPH05183259A/en
Publication of JPH05183259A publication Critical patent/JPH05183259A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a manufacturing method of a high density printed wiring board excellent in reliability wherein plating omission, plating spread, and undercut of solder resist are not generated. CONSTITUTION:In a manufacturing method of a fine printed wiring board of high density wherein resist 1 formed on an insulative board 9 is subjected to chemical plating, the height of a conductor circuit pattern 2 between patterns of the conductor circuit pattern 2 is made a nearly identical surface. After that, the part except the conductor circuit pattern 2 to be subjected to chemical plating is coated with solder resist, and subjected to chemical plating like an Ni-plated film 22 and an Au-plated film 23.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,高密度でファインな導
体回路パターンを有する,高密度プリント配線板の製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a high density printed wiring board having a high density and fine conductor circuit pattern.

【0002】[0002]

【従来技術】近年,電子機器の小型化に伴い,これを実
装するためのプリント配線板に対しても,ファインで高
密度化への要求が強くなっている。従来,上記プリント
配線板は,特に産業用のものに対しては高い信頼性が要
求されることから,主としてサブトラクティブ法により
製造されている。これは,導体回路パターンが絶縁基板
に対して密着強度が高いことによる。上記サブトラクテ
ィブ法は,図7〜図11に示すごとく,銅箔91を有す
る銅張り積層板9を出発材料として,導体回路パターン
として不必要な銅箔91を部分的にエッチングにより溶
解除去する方法である。
2. Description of the Related Art In recent years, with the miniaturization of electronic equipment, there is an increasing demand for finer and higher density printed wiring boards for mounting the electronic equipment. Conventionally, the above-mentioned printed wiring board is mainly manufactured by the subtractive method because high reliability is required particularly for industrial use. This is because the conductor circuit pattern has high adhesion strength to the insulating substrate. As shown in FIGS. 7 to 11, the subtractive method is a method in which a copper clad laminate 9 having a copper foil 91 is used as a starting material and a copper foil 91 unnecessary as a conductor circuit pattern is partially removed by etching. Is.

【0003】即ち,図7に示すごとく,まず上記銅張り
積層板9に,スルーホール形成用,位置合せ用などの穴
90を多数,所定の個所に明ける。次に,図8に示すご
とく,エッチングレジスト92を,銅張り積層板9にお
ける,導体回路パターンを形成する部分以外の表面に被
覆する。次いで,図9に示すごとく,塩化銅溶液を用い
た無電解メッキによりCuメッキ膜93を形成し,導体
回路パターン900のベースを形成する。
That is, as shown in FIG. 7, first, a large number of holes 90 for forming through holes and for positioning are formed in the copper-clad laminate 9 at predetermined locations. Next, as shown in FIG. 8, an etching resist 92 is coated on the surface of the copper-clad laminate 9 other than the portion where the conductor circuit pattern is formed. Next, as shown in FIG. 9, a Cu plating film 93 is formed by electroless plating using a copper chloride solution to form a base of the conductor circuit pattern 900.

【0004】以上のごとく,上記サブトラクティブ法
は,図7〜図9に示す工程により導体回路パターン90
0を形成する方法である。その後,図10に示すごと
く,上記Cuメッキ膜93の表面において,化学メッキ
を施さない部分には,写真現像型のソルダーレジスト9
4を被覆する。そして,図11に示すごとく,上記Cu
メッキ膜93の表面に,化学メッキによりNiメッキ膜
95を施す。また,該Niメッキ膜95の表面には,化
学置換法及び化学還元法により,Auメッキ膜96を施
す。
As described above, in the subtractive method, the conductor circuit pattern 90 is formed by the steps shown in FIGS.
This is a method of forming 0. Then, as shown in FIG. 10, on the surface of the Cu plating film 93, the photo-developing solder resist 9 is applied to a portion where chemical plating is not applied.
Coat 4. Then, as shown in FIG.
A Ni plating film 95 is applied to the surface of the plating film 93 by chemical plating. Further, an Au plating film 96 is applied to the surface of the Ni plating film 95 by the chemical substitution method and the chemical reduction method.

【0005】[0005]

【解決しようとする課題】しかしながら,上記従来技術
には,次の問題点がある。即ち,上記Cuメッキ膜9
3,Niメッキ膜95,Auメッキ膜96により形成さ
れた導体回路パターン900は,その線間距離が100
μm以下の高密度でファインな場合においては,図12
に示すごとく,メッキ落ち97を生ずる。
However, the above-mentioned conventional technique has the following problems. That is, the Cu plating film 9
3, the conductor circuit pattern 900 formed of the Ni plating film 95 and the Au plating film 96 has a line spacing of 100.
In the case of high density and fine of less than μm, FIG.
As shown in FIG.

【0006】また,図13に示すごとく,メッキ拡がり
98と称する,隣接するパターン相互間のショート部分
を生ずる。上記メッキ落ち部分97及びメッキ拡がり9
8は,いずれも線間距離が100μm以下と極めて小さ
いピッチであるために,メッキ液が線間において流れに
くくなるために生ずる現象と考えられる。一方,上記サ
ブトラクティブ法においては,上記ソルダーレジスト9
4が,導体回路パターン900の上の部分である上方部
分940において,その厚みが薄くなり易い。
Further, as shown in FIG. 13, a short-circuit portion between adjacent patterns, which is called a plating spread 98, occurs. The plated-off portion 97 and the plated spread 9
No. 8 is considered to be a phenomenon that occurs because it is difficult for the plating solution to flow between the lines because the distance between the lines is 100 μm or less and the pitch is extremely small. On the other hand, in the subtractive method, the solder resist 9
In the upper portion 940, which is the upper portion of the conductor circuit pattern 900, the thickness of the portion 4 is likely to be thin.

【0007】ところが,ソルダーレジスト94を硬化す
るための現像処理は,一般に該ソルダーレジスト94の
厚みが大きい部分941,即ち導体回路パターン以外の
上方部分に合わせて行われる。そのため,上記導体回路
パターン900上の上方部分940においては,現像が
過剰となり,ソルダーレジスト94が硬化し過ぎる場合
を生ずる。その結果,図14に示すごとく,ソルダーレ
ジスト94の境界端部において,下方が欠損したアンダ
ーカット99を生じ易い。
However, the developing process for hardening the solder resist 94 is generally performed in conformity with the portion 941 having a large thickness of the solder resist 94, that is, the upper portion other than the conductor circuit pattern. Therefore, in the upper portion 940 on the conductor circuit pattern 900, excessive development may occur and the solder resist 94 may be excessively hardened. As a result, as shown in FIG. 14, an undercut 99 lacking in the lower portion is likely to occur at the boundary end of the solder resist 94.

【0008】また,上記Niメッキ膜95及びAuメッ
キ膜96を施す際の液温が80℃〜90℃と比較的高温
の厳しい条件下では,上記ソルダーレジスト94のアン
ダーカット99にメッキ液が浸み込むことがある。その
結果,ソルダーレジスト94が楔を打ち込まれたよう
に,順次剥離していく場合がある。本発明は,かかる従
来の問題点に鑑みてなされたもので,メッキ落ち,メッ
キ拡がり,アンダーカットを生ずることがなく,高密度
で信頼性に優れた,高密度プリント配線板の製造方法を
提供しようとするものである。
In addition, under the severe conditions that the liquid temperature for applying the Ni plating film 95 and the Au plating film 96 is relatively high at 80 ° C. to 90 ° C., the undercut 99 of the solder resist 94 is immersed in the plating liquid. There is something that can be seen. As a result, the solder resist 94 may be peeled off one after another as if a wedge was driven in. The present invention has been made in view of the above conventional problems, and provides a method for manufacturing a high-density printed wiring board which is free from plating drop, plating spread, and undercut, and has high density and excellent reliability. Is what you are trying to do.

【0009】[0009]

【課題の解決手段】本発明は,絶縁基板に形成された導
体回路パターンに対して,該導体回路パターンの表面に
化学メッキを施すに際して,上記導体回路パターンの表
面を覆うようにめっきレジストを被覆し,その後化学メ
ッキを施すべき導体回路パターンの付近のめっきレジス
トを除去して導体回路パターンを露出させ,かつ露出部
分における導体回路パターンとめっきレジストの高さを
ほぼ同一面となし,その後化学メッキを施すことを特徴
とする高密度プリント配線板の製造方法にある。
According to the present invention, when a conductor circuit pattern formed on an insulating substrate is chemically plated on the surface of the conductor circuit pattern, a plating resist is coated so as to cover the surface of the conductor circuit pattern. Then, the plating resist in the vicinity of the conductor circuit pattern to be chemically plated is removed to expose the conductor circuit pattern, and the height of the conductor circuit pattern and the plating resist in the exposed portion is made to be substantially on the same plane, and then the chemical plating is performed. The method for manufacturing a high-density printed wiring board is characterized in that

【0010】本発明において最も注目すべきことは,上
記導体回路パターンの表面をめっきレジストにより被覆
し,その後化学メッキを施すべき部分のめっきレジスト
を除去して導体回路パターンを露出させ,該導体回路パ
ターンとめっきレジストの高さをほぼ同一面とし,その
後化学メッキを施すことにある。上記めっきレジストと
しては,例えばドライフィルムを用いる。また,該めっ
きレジストを除去する方法としては,例えばサンドペー
パーを用いる研磨加工法がある。
What is most noticeable in the present invention is that the surface of the conductor circuit pattern is covered with a plating resist, and then the plating resist in the portion to be chemically plated is removed to expose the conductor circuit pattern. The heights of the pattern and the plating resist are almost on the same plane, and then chemical plating is performed. As the plating resist, for example, a dry film is used. As a method for removing the plating resist, there is a polishing method using sandpaper, for example.

【0011】上記導体回路パターンは,例えば化学メッ
キによるCuメッキ膜,半田剥離法による半田を用いた
パターンメッキ膜により形成する。また,上記絶縁基板
としては,例えばガラス繊維により強化したガラスエポ
キシ基板,銅箔積層基板を用いる。また,上記導体回路
パターン形成のために,化学メッキによるCuメッキ膜
を,ガラスエポキシ基板の表面に形成するに当たって
は,例えばアディティブ法を用いる。このアディティブ
法は,例えばガラスエポキシ基板等の絶縁基板の表面
に,耐熱性及び電気絶縁性に優れたエポキシ樹脂接着剤
を塗布することにより行う。その後,アンカーを形成す
るために,上記エポキシ樹脂接着剤の粗化を行う。そし
て,粗化後は,触媒をその表面に付与する。その後,上
記のごとく,めっきレジストを上記のごとく施し,導体
回路パターンの上面に,Cuメッキ膜,Niメッキ膜,
Auメッキ膜などの化学メッキを形成する。
The conductor circuit pattern is formed of, for example, a Cu plating film by chemical plating or a pattern plating film using solder by a solder peeling method. Further, as the insulating substrate, for example, a glass epoxy substrate reinforced with glass fiber or a copper foil laminated substrate is used. Further, in forming the Cu plating film by chemical plating on the surface of the glass epoxy substrate for forming the conductor circuit pattern, for example, an additive method is used. This additive method is performed by applying an epoxy resin adhesive having excellent heat resistance and electrical insulation to the surface of an insulating substrate such as a glass epoxy substrate. After that, the epoxy resin adhesive is roughened to form an anchor. After roughening, the catalyst is applied to the surface. After that, the plating resist is applied as described above, and the Cu plating film, Ni plating film,
Chemical plating such as Au plating film is formed.

【0012】[0012]

【作用及び効果】本発明においては,隣接する導体回路
パターン間には,導体回路パターンと高さがほぼ同一面
のめっきレジストが被覆してある(図3参照)。そのた
め,導体回路上に化学メッキを施した際に,隣接する導
体回路パターン間に,メッキ落ち,メッキ拡がりを生ず
ることがなく,またアンダーカットを生ずることがない
(図6参照)。上記メッキ落ち及びメッキ拡がりを生じ
ない理由は,導体回路パターンの間に,該導体回路パタ
ーンとほぼ同一面までめっきレジストが形成してあるた
め,化学メッキが横方向に拡がらないからである。
In the present invention, between the adjacent conductor circuit patterns, a plating resist having the same height as that of the conductor circuit patterns is coated (see FIG. 3). Therefore, when chemical plating is performed on the conductor circuit, neither plating drop nor plating spread occurs between adjacent conductor circuit patterns, and no undercut occurs (see FIG. 6). The reason why the plating drop and the plating spread do not occur is that the chemical plating does not spread in the lateral direction because the plating resist is formed between the conductor circuit patterns to almost the same surface as the conductor circuit patterns.

【0013】また,アンダーカットを生じない理由は,
導体回路パターン間にこれと同一面上までめっきレジス
トが形成してあるため,化学メッキを施さない部分に被
覆するソルダーレジストの厚みを均一にすることができ
ることによる(図4,5参照)。また,これらにより,
高密度で信頼性に優れた導体回路パターンを形成するこ
とができる。以上のごとく,本発明によれば,メッキ落
ち,メッキ拡がり,アンダーカットを生ずることがな
く,高密度で信頼性に優れた,高密度プリント配線板の
製造方法を提供することができる。
The reason why the undercut does not occur is as follows.
Since the plating resist is formed between the conductor circuit patterns on the same surface as the conductor circuit patterns, it is possible to make the thickness of the solder resist covering the portions not subjected to chemical plating uniform (see FIGS. 4 and 5). Also, with these,
It is possible to form a conductor circuit pattern having high density and excellent reliability. As described above, according to the present invention, it is possible to provide a method for manufacturing a high-density printed wiring board that is free from plating drop, plating spread, and undercut, and has high density and excellent reliability.

【0014】[0014]

【実施例】本発明の実施例にかかる高密度プリント配線
板の製造方法につき,図1〜図6を用いて説明する。本
例は,まず図1に示すごとく,絶縁基板9に形成された
導体回路パターン2に対して,該導体回路パターン2の
表面に化学メッキを施すことにより,高密度でファイン
な,プリント配線板を製造するものである。まず,その
概要を説明すれば,図2に示すごとく,絶縁基板9上
に,めっきレジスト1を被覆する。これに,Cuメッキ
膜21を形成して,図4に示すごとく,導体回路パター
ン2とめっきレジスト1の高さをほぼ同一面となすプリ
ント配線板を従来と同様アディティブ法で作成する。
EXAMPLE A method for manufacturing a high-density printed wiring board according to an example of the present invention will be described with reference to FIGS. In this example, first, as shown in FIG. 1, a conductor circuit pattern 2 formed on an insulating substrate 9 is subjected to chemical plating on the surface of the conductor circuit pattern 2 to obtain a high density and fine printed wiring board. Is manufactured. First, the outline thereof will be described. As shown in FIG. 2, the insulating substrate 9 is coated with the plating resist 1. A Cu plating film 21 is formed on this, and as shown in FIG. 4, a printed wiring board in which the height of the conductor circuit pattern 2 and the plating resist 1 are substantially on the same plane is formed by the additive method as in the conventional case.

【0015】そして,図4,図5に示すごとく,化学メ
ッキを施すべき導体回路パターン2以外の部分をソルダ
ーレジスト3により被覆し,その後Niメッキ膜22,
Auメッキ膜23の化学メッキを施す。このようにし
て,上記図1に示した高密度プリント配線板を得る。こ
こで,まず注目すべきことは,導体回路パターン2の線
間距離は,約50〜60μmで,高密度でファインなこ
とである。
Then, as shown in FIGS. 4 and 5, a portion other than the conductor circuit pattern 2 to be chemically plated is covered with the solder resist 3, and then the Ni plating film 22,
The Au plating film 23 is chemically plated. In this way, the high-density printed wiring board shown in FIG. 1 is obtained. Here, it should be noted that the distance between lines of the conductor circuit pattern 2 is about 50 to 60 μm, which is dense and fine.

【0016】上記導体回路パターン2は,図1に示すご
とく化学メッキにより形成した,Cuメッキ膜21と,
Niメッキ膜22と,Auメッキ膜23とよりなる。上
記Cuメッキ膜21は,膜厚みが約30μmである。ま
た,上記Niメッキ膜22は,膜厚みが約5μmであ
る。また,上記Auメッキ膜23は,膜厚みが約0.5
μmである。
The conductor circuit pattern 2 has a Cu plating film 21 formed by chemical plating as shown in FIG.
It is composed of a Ni plating film 22 and an Au plating film 23. The Cu plating film 21 has a film thickness of about 30 μm. The Ni plating film 22 has a film thickness of about 5 μm. The Au plating film 23 has a film thickness of about 0.5.
μm.

【0017】次に,上記高密度プリント配線板の製造方
法につき,図1〜図6を用いて具体的に説明する。先
ず,絶縁基板9上に,図2に示すごとく,アディティブ
法により,上記Cuメッキ膜21を形成する。即ち,上
記アディティブ法は,銅箔を表面に有しない,ガラスエ
ポキシ基板からなる絶縁基板9を用いる。そして,上記
絶縁基板9の表面には,先ず耐熱性及び電気絶縁性に優
れたエポキシ樹脂接着剤(図示略)を塗布する。そし
て,これを加熱し,硬化させる。
Next, a method for manufacturing the above-mentioned high-density printed wiring board will be specifically described with reference to FIGS. First, the Cu plating film 21 is formed on the insulating substrate 9 by an additive method as shown in FIG. That is, the additive method uses the insulating substrate 9 made of a glass epoxy substrate having no copper foil on the surface. Then, an epoxy resin adhesive (not shown) having excellent heat resistance and electrical insulation is first applied to the surface of the insulating substrate 9. Then, this is heated and cured.

【0018】次に,上記エポキシ樹脂接着剤をアンカー
形成のために粗化する。次いで,粗化した該エポキシ樹
脂接着剤の表面に,塩酸系パラジウム溶液を用いて活性
化処理(図示略)を行う。その後,図2に示すごとく,
絶縁基板9上に,化学メッキにより導体回路パターン2
の基礎となる上記Cuメッキ膜21を形成する。次に,
上記Cuメッキ膜21を含めて回路パターン2の表面を
覆うように,めっきレジスト1を被覆する。
Next, the epoxy resin adhesive is roughened to form an anchor. Next, an activation treatment (not shown) is performed on the surface of the roughened epoxy resin adhesive using a hydrochloric acid palladium solution. After that, as shown in Figure 2,
Conductor circuit pattern 2 is formed on the insulating substrate 9 by chemical plating.
The Cu plating film 21 serving as the basis of is formed. next,
The plating resist 1 is coated so as to cover the surface of the circuit pattern 2 including the Cu plating film 21.

【0019】上記めっきレジスト1は,永久レジスト型
のドライフィルムを用いる。該めっきレジスト1は,厚
みが約40μmで,柔軟性を有する。次いで,図4に示
すごとく,化学メッキを施すべき導体回路パターン2の
付近のめっきレジスト1を除去して導体回路パターン2
の表面を露出させる。そして,該露出部分における該導
体回路パターン2とめっきレジスト1の高さを,ほぼ同
一面となす。
As the plating resist 1, a permanent resist type dry film is used. The plating resist 1 has a thickness of about 40 μm and is flexible. Next, as shown in FIG. 4, the plating resist 1 near the conductor circuit pattern 2 to be chemically plated is removed to remove the conductor circuit pattern 2
Expose the surface of. The heights of the conductor circuit pattern 2 and the plating resist 1 in the exposed portion are substantially flush with each other.

【0020】上記導体回路パターン1を露出させる手段
としては,まずサンドペーパーを用いた研磨加工を用い
る。次いで,導体回路パターン2とめっきレジスト1と
の高さを,ほぼ同一面となす手段としては,ポリッシャ
加工を用いる。次に,図4に示すごとく,化学メッキを
施すべき導体回路パターン2以外の部分を,ソルダーレ
ジスト3により被覆する。該ソルダーレジスト3は,写
真現像型の光硬化性樹脂よりなる。そのため,該ソルダ
ーレジスト3は,露光現像して硬化させる。
As a means for exposing the conductor circuit pattern 1, first, a polishing process using sandpaper is used. Next, as a means for making the heights of the conductor circuit pattern 2 and the plating resist 1 substantially flush with each other, polisher processing is used. Next, as shown in FIG. 4, portions other than the conductor circuit pattern 2 to be subjected to chemical plating are covered with a solder resist 3. The solder resist 3 is made of a photo-developing photocurable resin. Therefore, the solder resist 3 is exposed and developed and cured.

【0021】その後,図5に示すごとく,化学メッキを
施す部分の上記Cuメッキ膜21の表面に,まず化学メ
ッキによりNiメッキ膜22を施す。Niメッキ膜22
を施すに当たっては,メッキ液の液温を80℃に調整
し,またpHを4に調整する。次いで,上記Niメッキ
膜22上には,Auメッキ膜23を化学メッキにより施
す。該Auメッキ膜23は,化学置換法及び化学還元法
により形成する。化学置換法は,メッキ液の液温を90
℃に調整し,またpHを4に調整して行う。また,化学
還元法は,液温を75℃に調整し,またpHを13に調
整して行う。
Thereafter, as shown in FIG. 5, a Ni plating film 22 is first applied by chemical plating on the surface of the Cu plating film 21 in the portion to be chemically plated. Ni plating film 22
In applying, the temperature of the plating solution is adjusted to 80 ° C. and the pH is adjusted to 4. Then, an Au plating film 23 is chemically plated on the Ni plating film 22. The Au plating film 23 is formed by a chemical substitution method and a chemical reduction method. The chemical replacement method is performed by adjusting the temperature of the plating solution to 90
The temperature is adjusted to ℃ and the pH is adjusted to 4. The chemical reduction method is performed by adjusting the liquid temperature to 75 ° C and the pH to 13.

【0022】次に,作用効果につき説明する。本例にお
いては,隣接する導体回路パターン2の間には,図4に
示すごとく,導体回路パターン2と高さがほぼ同一面の
めっきレジスト1が被覆してある。そのため,従来のご
とく,隣接する導体回路パターン2間に,メッキ落ち,
メッキ拡がり,アンダーカット(図6)を生ずることが
ない。ここで,図6は,導体回路パターン2において,
化学メッキを施さない部分の表面に,ソルダーレジスト
3を被覆した状態を示すものであるが,従来のごとく,
ソルダーレジスト3にアンダーカットを生じていない。
上記メッキ落ち及びメッキ拡がりを生じない理由は,ア
ディティブ法により形成したCuメッキ膜21からなる
導体回路パターン2間に,該導体回路パターン2とほぼ
同一面までめっきレジスト1が形成してある(図3)た
め,化学メッキを形成してもこれらが横方向に広がらな
いからである。
Next, the function and effect will be described. In this example, as shown in FIG. 4, a space between the adjacent conductor circuit patterns 2 is covered with a plating resist 1 whose height is substantially the same as that of the conductor circuit patterns 2. Therefore, as in the conventional case, plating is dropped between the adjacent conductor circuit patterns 2,
There is no plating spread and undercut (Fig. 6). Here, in FIG. 6, in the conductor circuit pattern 2,
It shows a state in which the surface of the portion not subjected to chemical plating is covered with the solder resist 3.
Undercut does not occur in the solder resist 3.
The reason why the above-mentioned plating drop and plating spread does not occur is that the plating resist 1 is formed between the conductor circuit patterns 2 made of the Cu-plated film 21 formed by the additive method up to almost the same surface as the conductor circuit patterns 2 (FIG. 3) Therefore, even if chemical plating is formed, these do not spread in the lateral direction.

【0023】また,上記アンダーカットを生じない理由
は,図4に示すごとく,導体回路パターン2間にこれと
同一面上までめっきレジスト1が形成してある。そのた
め,導体回路パターン2において化学メッキを施さない
部分に被覆するソルダーレジスト3の厚みを均一にする
ことができるからである。また,これらにより,高密度
で信頼性に優れた導体回路パターンを形成することがで
きる。また,上記Cuメッキ膜21を形成するに当た
り,耐熱性,電気絶縁性に優れたエポキシ樹脂接着剤を
用いている。そのため,導体回路パターン2間の電気絶
縁性に優れ,高い信頼性が得られる。また,Cuメッキ
膜21の密着強度が高温下でも安定し,耐熱性に優れ
る。
The reason why the undercut does not occur is that the plating resist 1 is formed between the conductor circuit patterns 2 on the same surface as the conductor circuit patterns 2 as shown in FIG. Therefore, the thickness of the solder resist 3 covering the portion of the conductor circuit pattern 2 that is not subjected to chemical plating can be made uniform. Further, by these, it is possible to form a high-density and highly reliable conductor circuit pattern. In forming the Cu plating film 21, an epoxy resin adhesive having excellent heat resistance and electrical insulation is used. Therefore, the electrical insulation between the conductor circuit patterns 2 is excellent, and high reliability is obtained. Further, the adhesion strength of the Cu plating film 21 is stable even at high temperature, and the heat resistance is excellent.

【0024】また,図3に示すごとく,めっきレジスト
1と導体回路パターン2の高さをほぼ同一面にしてある
ため,該導体回路パターン2が平坦性に優れ,高密度表
面実装に最適である。以上のごとく,本例によれば,図
1に示すごとく,高密度でファインな信頼性に優れた,
高密度プリント配線板を得ることができる。なお,上記
アディティブ法により形成したCuメッキ膜21に代え
て,半田剥離法による半田を用いたパターンメッキ膜と
することもできる。
Further, as shown in FIG. 3, since the plating resist 1 and the conductor circuit pattern 2 have substantially the same height, the conductor circuit pattern 2 has excellent flatness and is most suitable for high-density surface mounting. .. As described above, according to this example, as shown in FIG. 1, high density and fine reliability are excellent.
A high-density printed wiring board can be obtained. The Cu plating film 21 formed by the additive method may be replaced by a pattern plating film using solder by a solder peeling method.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例にかかる高密度プリント配線板の断面を
示す,図5のA−A線矢視断面図。
FIG. 1 is a cross-sectional view taken along the line AA of FIG. 5, showing a cross section of a high density printed wiring board according to an example.

【図2】実施例における,絶縁基板に形成した導体回路
パターンを示す斜視図。
FIG. 2 is a perspective view showing a conductor circuit pattern formed on an insulating substrate in the example.

【図3】実施例における,めっきレジストと導体回路パ
ターンの高さをほぼ同一面となした状態を示す斜視図。
FIG. 3 is a perspective view showing a state in which the plating resist and the conductor circuit pattern have substantially the same height in the embodiment.

【図4】実施例における,化学メッキしない導体回路パ
ターンの表面にソルダーレジストを被覆した状態を示す
斜視図。
FIG. 4 is a perspective view showing a state in which a solder resist is coated on the surface of a conductor circuit pattern that is not subjected to chemical plating in the example.

【図5】実施例における,導体回路パターンの表面に化
学メッキ膜を施した状態を示す斜視図。
FIG. 5 is a perspective view showing a state in which a chemical plating film is applied to the surface of the conductor circuit pattern in the example.

【図6】実施例における,導体回路パターンの表面にソ
ルダーレジストを被覆した状態を示す斜視図。
FIG. 6 is a perspective view showing a state in which the surface of the conductor circuit pattern is covered with a solder resist in the example.

【図7】従来例における,絶縁基板に穴明けをした状態
を示す斜視図。
FIG. 7 is a perspective view showing a state in which a hole is formed in an insulating substrate in a conventional example.

【図8】従来例における,絶縁基板にエッチングレジス
トを被覆した状態を示す斜視図。
FIG. 8 is a perspective view showing a state in which an insulating substrate is covered with an etching resist in a conventional example.

【図9】従来例における,絶縁基板上に導体回路パター
ンを形成した状態を示す斜視図。
FIG. 9 is a perspective view showing a state in which a conductor circuit pattern is formed on an insulating substrate in a conventional example.

【図10】従来例における,導体回路パターン上にソル
ダーレジストを被覆した状態を示す斜視図。
FIG. 10 is a perspective view showing a state in which a conductor resist pattern is coated on a conductor circuit pattern in a conventional example.

【図11】従来例における,導体回路パターンの表面に
化学メッキ膜を形成した状態を示す斜視図。
FIG. 11 is a perspective view showing a state in which a chemical plating film is formed on the surface of a conductor circuit pattern in a conventional example.

【図12】図12のB−B線矢視断面図。12 is a cross-sectional view taken along the line BB of FIG.

【図13】図12のC−C線矢視断面図。13 is a cross-sectional view taken along the line CC of FIG.

【図14】図10のD−D線矢視断面図。14 is a cross-sectional view taken along the line DD of FIG.

【符号の説明】[Explanation of symbols]

1...めっきレジスト, 2...導体回路パターン, 20...露出部分, 21...Cuメッキ膜, 22...Niメッキ膜, 23...Auメッキ膜, 3...ソルダーレジスト, 9...絶縁基板, 1. . . Plating resist, 2. . . Conductor circuit pattern, 20. . . Exposed part, 21. . . Cu plating film, 22. . . Ni plating film, 23. . . Au plating film, 3. . . Solder resist, 9. . . Insulating substrate,

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板に形成された導体回路パターン
に対して,該導体回路パターンの表面に化学メッキを施
すに際して, 上記導体回路パターンの表面を覆うようにめっきレジス
トを被覆し,その後化学メッキを施すべき導体回路パタ
ーンの付近のめっきレジストを除去して導体回路パター
ンを露出させ,かつ露出部分における導体回路パターン
とめっきレジストの高さをほぼ同一面となし,その後化
学メッキを施すことを特徴とする高密度プリント配線板
の製造方法。
1. When a conductor circuit pattern formed on an insulating substrate is chemically plated on the surface of the conductor circuit pattern, a plating resist is coated so as to cover the surface of the conductor circuit pattern, and then chemical plating is performed. Characterized by removing the plating resist in the vicinity of the conductor circuit pattern to be exposed to expose the conductor circuit pattern, and making the height of the conductor circuit pattern and the plating resist in the exposed portion almost the same surface, and then performing chemical plating And a method for manufacturing a high-density printed wiring board.
JP36014591A 1991-12-27 1991-12-27 Manufacture of high density printed wiring board Pending JPH05183259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36014591A JPH05183259A (en) 1991-12-27 1991-12-27 Manufacture of high density printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36014591A JPH05183259A (en) 1991-12-27 1991-12-27 Manufacture of high density printed wiring board

Publications (1)

Publication Number Publication Date
JPH05183259A true JPH05183259A (en) 1993-07-23

Family

ID=18468101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP36014591A Pending JPH05183259A (en) 1991-12-27 1991-12-27 Manufacture of high density printed wiring board

Country Status (1)

Country Link
JP (1) JPH05183259A (en)

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JP2002198630A (en) * 2000-12-26 2002-07-12 Kyocera Corp Electronic component mounting substrate
JP2006344920A (en) * 2005-05-10 2006-12-21 Hitachi Chem Co Ltd Printed circuit board, manufacturing method therefor, semiconductor chip mounting substrate, manufacturing method therefor, and semiconductor package
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US7257891B2 (en) 2001-11-13 2007-08-21 Lg Electronics Inc. Method for forming bonding pads
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JP2002198630A (en) * 2000-12-26 2002-07-12 Kyocera Corp Electronic component mounting substrate
US7304249B2 (en) * 2001-11-13 2007-12-04 Lg Electronics Inc. Bonding pads for a printed circuit board
US7257891B2 (en) 2001-11-13 2007-08-21 Lg Electronics Inc. Method for forming bonding pads
JP2006344920A (en) * 2005-05-10 2006-12-21 Hitachi Chem Co Ltd Printed circuit board, manufacturing method therefor, semiconductor chip mounting substrate, manufacturing method therefor, and semiconductor package
JP2007096007A (en) * 2005-09-29 2007-04-12 Cmk Corp Printed circuit board and its manufacturing method
JP2007103648A (en) * 2005-10-04 2007-04-19 Hitachi Chem Co Ltd Printed circuit board, manufacturing metehod thereof, semiconductor chip mounting substrate, manufacturing method thereof and semiconductor package
WO2007040204A1 (en) * 2005-10-04 2007-04-12 Hitachi Chemical Company, Ltd. Photosensitive resin composition, photosensitive element, and method for manufacturing printed wiring board
JP4747770B2 (en) * 2005-10-04 2011-08-17 日立化成工業株式会社 Method for manufacturing printed wiring board and method for manufacturing semiconductor chip mounting substrate
WO2007119947A1 (en) * 2006-04-13 2007-10-25 Kolon Industries, Inc Method of manufacturing metal electrode
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JPWO2014103541A1 (en) * 2012-12-27 2017-01-12 日本碍子株式会社 Electronic component and manufacturing method thereof
JP2015148966A (en) * 2014-02-06 2015-08-20 日本写真印刷株式会社 Transparent conductive support body, touch sensor, and method for manufacturing the same
WO2019187558A1 (en) * 2018-03-30 2019-10-03 住友大阪セメント株式会社 Optical waveguide element
JP2019179122A (en) * 2018-03-30 2019-10-17 住友大阪セメント株式会社 Optical waveguide element
US11327347B2 (en) 2018-03-30 2022-05-10 Sumitomo Osaka Cement Co., Ltd. Optical waveguide element
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