JPH05335722A - Manufacture of printed circuit board - Google Patents

Manufacture of printed circuit board

Info

Publication number
JPH05335722A
JPH05335722A JP13638792A JP13638792A JPH05335722A JP H05335722 A JPH05335722 A JP H05335722A JP 13638792 A JP13638792 A JP 13638792A JP 13638792 A JP13638792 A JP 13638792A JP H05335722 A JPH05335722 A JP H05335722A
Authority
JP
Japan
Prior art keywords
solder
layer
circuit pattern
electrolytic
solder plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP13638792A
Other languages
Japanese (ja)
Inventor
Kenji Goto
謙二 後藤
Noriaki Sekine
典昭 関根
Naoto Kamegawa
直人 亀川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13638792A priority Critical patent/JPH05335722A/en
Publication of JPH05335722A publication Critical patent/JPH05335722A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE:To acquire a manufacturing method of a printed circuit board which does not lower wiring density and does not require application of solder paste, etc. CONSTITUTION:A required circuit pattern including a surface mounting pad is patterned in a conductor layer surface 1a which is integrally formed in at least one main surface of an insulating substrate. An electrolytic solder plating layer 5 is applied and formed in the circuit patterning surface, and a required circuit pattern including a surface mounting pad is formed by selectively etching an exposed conductor layer using the applied and formed electrolytic solder plating layer as an etching resist. Then, a specified circuit pattern part is masked and the electrolytic solder plating layer excepting the masked region is removed. After the mask is removed, a solder flow-out preventing dam 7 is formed in a conductor layer pattern surface of the remaining and applied electrolytic solder plating layer. Thereafter, the remaining and applied electrolytic solder plating is made into eutectic solder by heating treatment and a solder resist layer is applied and formed in a specified circuit pattern formation surface including a surface mounting pad.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプリント配線板の製造方
法に係り、特に表面実装用パッドを有するプリント配線
板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board having surface mounting pads.

【0002】[0002]

【従来の技術】電子機器類の軽量化ないしコンパクト化
を目的として、回路機構の小形化なども図られている。
すなわち、プリント配線板の主面に、所要の電子部品を
実装して成る実装回路装置(実装回路ユニット)が、各
種の電子機器類で広く実用に供されつつあり、またこの
ために、高密度プリント配線板の開発も進められてい
る。 ところで、前記表面実装用の高密度プリント配線
板の製造方法としては、次のような手段が知られてい
る。
2. Description of the Related Art For the purpose of reducing the weight and size of electronic devices, the circuit mechanism has been downsized.
That is, a mounting circuit device (mounting circuit unit) in which required electronic components are mounted on the main surface of a printed wiring board is being widely put to practical use in various electronic devices. Development of printed wiring boards is also in progress. By the way, the following means are known as a method for manufacturing the high-density printed wiring board for surface mounting.

【0003】(a) エッチングレジストとして、電解半田
めっき層を用いて選択エッチングを行い、表面実装用パ
ッドを含む導体回路全体を、銅(下地層)およびめっき
された半田(上層)の2層構造に形成する半田めっきプ
リント配線板の製造方法。
(A) As an etching resist, selective etching is performed by using an electrolytic solder plating layer, and the entire conductor circuit including the surface mounting pads is formed into a two-layer structure of copper (underlayer) and plated solder (upper layer). A method for manufacturing a solder-plated printed wiring board to be formed on.

【0004】(b) 表面実装用パッド領域以外の導体回路
パターン上に、ソルダーレジストをコーティングし、そ
の後ホットエアーレベリングによって、露出している表
面実装用パッド領域面上に、選択的に半田層を形成する
ホットエアーレベリングプリント配線板の製造方法(HAL
法)。
(B) A solder resist is coated on the conductor circuit pattern other than the surface mounting pad region, and then hot air leveling is performed to selectively form a solder layer on the exposed surface mounting pad region surface. Forming method of hot air leveling printed wiring board (HAL
Law).

【0005】(c) 前記(b) の HAL法に比べて電解半田め
っき層の厚さを 2〜 3倍程度にし、下地銅の選択的なエ
ッチングにより回路パターン形成後、前記電解半田めっ
きを共晶化させて、共晶はんだで表面が被覆された回路
パターンを形成するプリント配線板の製造方法(半田ス
ルホールめっき法)。
(C) Compared with the HAL method of (b) above, the thickness of the electrolytic solder plating layer is about 2 to 3 times, and after the circuit pattern is formed by selective etching of the underlying copper, the electrolytic solder plating is applied together. A method for manufacturing a printed wiring board, which is crystallized to form a circuit pattern whose surface is coated with eutectic solder (solder through-hole plating method).

【0006】(d) 表面実装用パッドを含む導体回路パタ
ーンの形成を、エッチングレジストパターンの被着、選
択エッチングおよびエッチングレジストパターンの剥離
によって、前記導体回路パターンを銅の1層構造とし、
ソルダーレジスト非被覆面にプリフラックスをコーティ
ングするプリフラックスプリント配線板の製造方法。 (e) 選択エッチングによって表面実装用パッドを含む導
体回路パターン形成し、さらにソルダーレジストをコー
ティングした後、所要の表面実装用パッドから給電用め
っきリードを引き出し、前記所要の表面実装用パッド面
上にのみ、選択的に電解半田層を析出させる部分電解半
田めっきプリント配線板の製造方法。
(D) The formation of the conductor circuit pattern including the surface mounting pad is performed by applying an etching resist pattern, selectively etching and peeling the etching resist pattern to form the conductor circuit pattern into a one-layer structure of copper.
A method for manufacturing a pre-flux printed wiring board, wherein a pre-flux is coated on the surface not covered with the solder resist. (e) After forming a conductor circuit pattern including the surface mounting pad by selective etching and further coating the solder resist, pull out the power supply plating lead from the required surface mounting pad and place it on the required surface mounting pad surface. A method for manufacturing a partially electrolytic solder-plated printed wiring board, which selectively deposits an electrolytic solder layer.

【0007】[0007]

【発明が解決しようとする課題】しかし、上記表面実装
用プリント配線板の製造方法には、実用上次のような問
題がある。
However, the above-mentioned method for manufacturing a surface-mounted printed wiring board has the following problems in practical use.

【0008】先ず、(a) の半田めっきプリント配線板の
製造方法で得られるプリント配線板の場合は、導体回路
の細密化(配線の高密度化)に伴い、実装部品を半田付
けする際、ソルダーレジストで覆われた導体回路(パタ
ーン)部分において、半田ブリッジを起こし易いという
不都合がある。
First, in the case of a printed wiring board obtained by the method of manufacturing a solder-plated printed wiring board of (a), when the mounting components are soldered together with the miniaturization of the conductor circuit (density of wiring), There is an inconvenience that a solder bridge is likely to occur in the conductor circuit (pattern) portion covered with the solder resist.

【0009】(b) のホットエアーレベリングプリント配
線板の製造方法で得られるプリント配線板の場合は、被
半田付け部以外がソルダーレジストで被覆されているた
め、半田ブリッジの起生は回避されるが、ホットエアー
レベリングされた半田(上層)の厚さが均一でないため
(均一な厚さに被着するのは事実上至難)、実装部品の
半田付け不良が起こり易いという不都合がある。
In the case of the printed wiring board obtained by the method for manufacturing a hot air leveling printed wiring board of (b), the occurrence of solder bridges is avoided because the portions other than the soldered portion are covered with solder resist. However, since the thickness of the hot air leveled solder (upper layer) is not uniform (it is virtually impossible to adhere to a uniform thickness), there is a disadvantage that defective soldering of mounted components easily occurs.

【0010】(c) の半田スルホールめっき法の場合は、
回路パターン幅が 150μm 以下と微細化すると、隣接す
る回路パターン間でショートなどを発生し易く、ソルダ
ーレジスト層の下側に半田層が残っているため、電子部
品の搭載・実装に対する信頼性の低下を招来するという
問題がある。
In the case of the solder through-hole plating method (c),
When the circuit pattern width is reduced to 150 μm or less, short circuits easily occur between adjacent circuit patterns, and the solder layer remains under the solder resist layer, which reduces the reliability of electronic component mounting and mounting. There is a problem of inviting.

【0011】(d) のプリフラックスプリント配線板の製
造方法で得られるプリント配線板の場合も、被半田付け
部以外がソルダーレジスト3で被覆されているため、半
田ブリッジの起生は回避されるが、所要の電子部品を実
装するに先立って、表面実装用パッド面に印刷法などに
よって、半田ペーストを被着する必要があり、表面実装
用パッドが 500μm 程度以下に狭ピッチ化してくると、
印刷による半田ペーストの被着が困難となって量産に不
適となる。
Also in the case of the printed wiring board obtained by the method for producing a pre-flux printed wiring board of (d), since the solder resist 3 covers the portions other than the soldered portion, the occurrence of solder bridges is avoided. However, before mounting the required electronic components, it is necessary to apply solder paste to the surface mounting pad surface by a printing method, etc., and if the surface mounting pads become narrower than about 500 μm,
It becomes difficult to apply the solder paste by printing, which is not suitable for mass production.

【0012】(e) の部分電解半田めっきプリント配線板
の製造方法の場合は、電解半田めっき層を被覆する表面
実装用パッドごとに、給電用めっきリードを引き出す必
要があるため、回路パターンの配線密度が必然的に低下
するという問題がある。
In the case of the method for manufacturing the partially electrolytic solder-plated printed wiring board of (e), it is necessary to pull out the power supply plating lead for each surface mounting pad covering the electrolytic solder plating layer, and therefore the wiring of the circuit pattern is required. There is a problem that the density inevitably decreases.

【0013】本発明は上記事情に対処してなされたもの
で、配線密度を低下させることなく、電子部品の実装に
当たって印刷による半田ペーストの被着なども不要で、
信頼性の高い表面実装が可能なプリント配線板の製造に
適するプリント配線板の製造方法の提供を目的とする。
The present invention has been made in view of the above circumstances, and does not reduce wiring density and does not require solder paste deposition by printing when mounting electronic components.
An object of the present invention is to provide a method for manufacturing a printed wiring board suitable for manufacturing a printed wiring board capable of highly reliable surface mounting.

【0014】[0014]

【課題を解決するための手段】本発明に係るプリント配
線板の製造方法は、絶縁性基板の少なくとも一主面に一
体的に形成された導体層面に表面実装用パッドを含む所
要の回路パターンをパターンニングする工程と、前記回
路パターンニングした面に電解半田めっき層を被着形成
する工程と、前記被着形成した電解半田めっき層をエッ
チングレジストとして露出している導体層を選択エッチ
ングして表面実装用パッドを含む所要の回路パターンを
形成する工程と、前記形成した少なくとも表面実装用パ
ッドを含む所定の回路パターン部にマスキングする工程
と、前記マスキングした領域以外の露出する電解半田め
っき層を除去する工程と、前記電解半田めっき層の除去
に用いたマスクを除去後、残存・被着している電解半田
めっき層の導体層パターン面上端部領域に半田流出防止
機能の付与もしくは配置・形成する工程と、前記半田流
出防止ダムを配置・形成した後、加熱処理を施して残存
・被着している電解半田めっきを共晶半田化する工程
と、前記加熱処理を施し共晶半田化した後、表面実装用
パッドを含む所定の回路パターン形成面にソルダーレジ
スト層を被着・形成する工程とを具備して成ることを特
徴とする。
A method of manufacturing a printed wiring board according to the present invention provides a required circuit pattern including a surface mounting pad on a conductor layer surface integrally formed on at least one main surface of an insulating substrate. A step of patterning, a step of depositing an electrolytic solder plating layer on the circuit-patterned surface, and a step of selectively etching the exposed conductor layer using the deposited electrolytic solder plating layer as an etching surface A step of forming a required circuit pattern including a mounting pad, a step of masking the formed circuit pattern portion including at least the surface mounting pad, and an exposed electrolytic solder plating layer other than the masked area are removed. And the conductor layer of the electrolytic solder plating layer remaining / adhered after removing the mask used for removing the electrolytic solder plating layer Eutectic process of applying or arranging / forming the solder outflow prevention function on the upper end area of the turn surface, and electrolytic solder plating remaining / deposited by heat treatment after arranging / forming the solder outflow prevention dam And a step of depositing and forming a solder resist layer on a predetermined circuit pattern forming surface including a surface mounting pad after performing the eutectic solder by performing the heat treatment. And

【0015】[0015]

【作用】本発明に係るプリント配線板の製造方法におい
ては、少なくとも表面実装用パッドを含む所要の回路パ
ターンを形成する段階に先立って、この回路パターン用
の導体層を共通の給電用リードとして利用し、回路パタ
ーンの全面に選択的に電解半田めっき層を被着形成した
後、回路パターン形成に用いたレジストを剥離・除去す
る。その後、電解半田めっき層で被覆されていない導体
層を選択的にエッチングしてから、少なくとも表面実装
用パッド面(領域)をマスキングして、不要な部分(領
域)の半田めっき層を選択除去する。つまり、将来電子
部品を搭載・実装するため露出させておくパッド面やス
ルホールに対応する給電用リードを各別に取り出す必要
もなく、所要の電解半田めっき層を選択的に被着形成し
得る。 また、実装電子部品の半田付けに寄与する電解
半田めっき層も、いわゆるヒュージング処理において、
連接する回路パターン面への流失が防止された状態で共
晶化(緻密化)が行われる一方、この共晶化(緻密化)
後、ソルダーレジスト層を被着・形成するので信頼性の
高い実装が可能になる。つまり、配線密度を低下させる
ことなく、また表面実装用パッドが 300μm 程度の狭ピ
ッチの場合でも、所要の半田層が設けられ、信頼性の高
い実装回路装置の構成が可能なプリント配線板を容易に
得ることができる。
In the method for manufacturing a printed wiring board according to the present invention, prior to the step of forming a required circuit pattern including at least surface mounting pads, the conductor layer for this circuit pattern is used as a common power supply lead. Then, after selectively forming an electrolytic solder plating layer on the entire surface of the circuit pattern, the resist used for forming the circuit pattern is peeled and removed. After that, the conductor layer not covered with the electrolytic solder plating layer is selectively etched, and then at least the surface mounting pad surface (region) is masked to selectively remove the unnecessary portion (region) of the solder plating layer. .. In other words, it is not necessary to separately take out the power supply leads corresponding to the pad surface and the through holes that are exposed for mounting and mounting electronic parts in the future, and the required electrolytic solder plating layer can be selectively deposited. Also, the electrolytic solder plating layer that contributes to the soldering of mounted electronic components is
While eutecticization (densification) is performed in a state where the flow to the circuit pattern surface that is connected is prevented, this eutecticization (densification)
After that, a solder resist layer is deposited and formed, so that highly reliable mounting becomes possible. In other words, a printed wiring board that can be configured with a highly reliable mounting circuit device is provided without reducing the wiring density, and even when the surface mounting pads have a narrow pitch of about 300 μm, the required solder layer is provided. Can be obtained.

【0016】[0016]

【実施例】以下図1〜図8(a) 〜(c) を参照して本発明
の実施例を説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 8 (a) to 8 (c).

【0017】実施例1 図1〜図7は本発明に係るプリント配線板の製造方法の
実施態様例を模式的に示したもので、図1〜図6は断面
的に、また図7は平面的にそれぞれ示している。先ず、
両主面に厚さ約18μm の銅箔層1aが一体的に配設(形
成)されたプリント配線板用の積層板2を用意し、所要
の箇所(位置)に孔明け加工を施して電気的な接続用の
孔3を形設する(図1)。次いで、前記孔明け加工した
積層板2の銅箔層1a面上に、要すれば厚付けもしくは薄
付けの化学銅めっき処理、および電気銅めっき処理を施
してパネル銅めっき層1bを形成した後、ドライフィルム
をラミネートして露光、現像を行うことによりパターン
マスキング4し、パターン銅めっき処理を施して接続用
の孔3の内壁面を含む露出面に厚さ25μmm程度の銅めっ
き層1cを被着・形成する(図2)。
Embodiment 1 FIGS. 1 to 7 schematically show an embodiment of a method for manufacturing a printed wiring board according to the present invention. FIGS. 1 to 6 are sectional views, and FIG. 7 is a plan view. It shows respectively. First,
Prepare a laminated board 2 for a printed wiring board in which copper foil layers 1a with a thickness of approximately 18 μm are integrally arranged (formed) on both main surfaces, and perform punching at the required locations (positions) to produce electricity. A hole 3 for making a special connection is formed (FIG. 1). Then, after forming a panel copper plating layer 1b on the surface of the copper foil layer 1a of the perforated laminated plate 2, if necessary, chemical copper plating treatment of thickening or thinning and electrolytic copper plating treatment are performed. , A dry film is laminated, exposed and developed to perform pattern masking 4, and a pattern copper plating process is performed to form a copper plating layer 1c having a thickness of about 25 μm on the exposed surface including the inner wall surface of the hole 3 for connection. Wear and form (Fig. 2).

【0018】その後、前記銅めっき層1cを被着・形成し
た積層板2を、たとえばホウフッ酸系半田めっき浴に浸
漬し、前記積層板2の銅箔層1aなどを給電用リードとし
て、電解半田めっき処理を行い露出している面に厚さ10
μmm程度以上の電解半田めっき層5を被着形成した(図
3)。次いで、前記パターンマスク4を剥離、除去し
(図4)、常套の手段によって所要の回路パターンを形
成した。つまり、前記電解半田めっき層5をエッチング
レジストとして、パターンマスク4の除去によって露出
した銅層1a,1b,1cを選択的にエッチング除去して、電
解半田めっき層5で表面が被覆された表面実装用パッド
など含む回路パターンを形成する。
After that, the laminated plate 2 on which the copper plating layer 1c has been deposited and formed is immersed in, for example, a borofluoric acid-based solder plating bath, and the copper foil layer 1a of the laminated plate 2 is used as a power-feeding lead for electrolytic soldering. The exposed surface is plated to a thickness of 10
An electrolytic solder plating layer 5 having a thickness of about μmm or more was deposited and formed (FIG. 3). Then, the pattern mask 4 was peeled and removed (FIG. 4), and a desired circuit pattern was formed by a conventional means. That is, using the electrolytic solder plating layer 5 as an etching resist, the copper layers 1a, 1b, 1c exposed by the removal of the pattern mask 4 are selectively etched away, and the surface mounting is covered with the electrolytic solder plating layer 5. A circuit pattern including pads for forming is formed.

【0019】上記により表面実装用パッドなど含む回路
パターンを形成した後、たとえばドライフィルムのよう
な感光性材料を真空ラミネータなどを用いてラミネート
し、前記電解半田めっき層5の被着形成されている回路
パターン中、電解半田めっき層5を残しておきたい領
域、すなわち表面実装用パッド面上やスルホール(接続
用の孔)3領域周面上を、感光性材料層でマスキング6
するように露光−現像し(図5)、露出している部分
(領域)の電解半田めっき層5を選択的に除去する。次
いで、前記感光性のマスク6を剥離・除去してから、ヒ
ュージング処理を行なう(図6)。
After forming the circuit pattern including the surface mounting pads and the like as described above, a photosensitive material such as a dry film is laminated by using a vacuum laminator or the like, and the electrolytic solder plating layer 5 is adhered and formed. In the circuit pattern, the area where the electrolytic solder plating layer 5 is to be left, that is, the surface mounting pad surface and the through hole (connection hole) 3 area peripheral surface are masked with a photosensitive material layer 6
Exposure-development is performed as shown in FIG. 5 to selectively remove the electrolytic solder plating layer 5 in the exposed portion (region). Then, the photosensitive mask 6 is peeled and removed, and then a fusing treatment is performed (FIG. 6).

【0020】本実施例においては、前記ヒュージング処
理に当たって、電解半田めっき層5の流出を防止するた
め、図7に平面的に示すごとく、残存・被着している電
解半田めっき層5の端縁部、換言すると電解半田めっき
層5が被覆されている表面実装用パッド領域に接続する
回路パターンとの境界領域に、たとえば印刷法などによ
って半田流れ防止用のダム7を予め形成する。このよう
に、半田流れ防止用のダム7を印刷・被着により形成し
た後、いわゆるヒュージング処理を行い、前記残存・被
着している電解半田めっき層5を流動化ないし軟化させ
て共晶・一様化する。このヒュージング処理において、
前記電解半田めっき層5をエッチングレジストとした銅
層1a,1b,1cの選択的なエッチングによる表面実装用パ
ッドなど含む回路パターンの形成で、銅層1a,1b,1cは
サイドエッチングを受け易いため、回路パターン化した
状態では銅層1a,1b,1cに対し、側面が突出した形を成
していた電解半田めっき層5が、形成された回路パター
ン面に沿って流動して、一様に被覆する形態を採ってい
た。
In this embodiment, in order to prevent the electrolytic solder plating layer 5 from flowing out during the fusing treatment, as shown in a plan view in FIG. 7, the end of the remaining electrolytic solder plating layer 5 is adhered. A dam 7 for preventing solder flow is previously formed by, for example, a printing method in an edge portion, in other words, in a boundary area with a circuit pattern connected to the surface mounting pad area covered with the electrolytic solder plating layer 5. In this way, after forming the solder flow preventing dam 7 by printing / deposition, a so-called fusing treatment is performed to fluidize or soften the remaining / deposited electrolytic solder plating layer 5 to thereby form a eutectic crystal.・ Be uniform. In this fusing process,
In the formation of a circuit pattern including a surface mounting pad by selectively etching the copper layers 1a, 1b, 1c using the electrolytic solder plating layer 5 as an etching resist, the copper layers 1a, 1b, 1c are susceptible to side etching. The electrolytic solder plating layer 5 having a side surface protruding with respect to the copper layers 1a, 1b, and 1c in the circuit-patterned state flows along the formed circuit pattern surface and is uniformly distributed. It was in the form of coating.

【0021】前記ヒュージング処理後、電解半田めっき
層5を残存・被着させた領域を除いた所要の領域面に、
いわゆるソルダーレジストをコーティングする。次い
で、所要の外形加工,電気検査を行い、たとえば、 300
μm , 250μm ピッチの表面実装用パッド面上に、厚さ
10μm 以上の半田層が一様に形成された表面実装用に適
するプリント配線板が得られた。
After the fusing treatment, on the surface of the required area except for the area where the electrolytic solder plating layer 5 remains and is adhered,
A so-called solder resist is coated. Then, the required external processing and electrical inspection are performed, and, for example, 300
Thickness on the surface mount pad surface of μm and 250μm pitch
A printed wiring board having a uniform solder layer of 10 μm or more and suitable for surface mounting was obtained.

【0022】実施例2 前記図1〜図7で模式的に図示した実施態様例におい
て、孔明け加工した積層板2(図1参照)の銅箔層1面
上に、要すれば厚付けもしくは薄付けの化学銅めっき処
理、および電気銅めっき処理を施してパネル銅めっき層
1bを形成した後、ドライフィルムをラミネートして露
光、現像を行うことによりパターンマスキング4する段
階で、表面実装用パッド領域に連接する回路パターンを
成す領域を、たとえば図8(a) 〜(c) に平面的に示すご
とく、非直線状を成すようにパターンニングした。その
後の銅めっき処理による接続用孔3の内壁面を含む露出
面への厚さ25μmm程度の銅めっき層1cの被着・形成(図
2参照)、前記銅めっき層1cを被着・形成した積層板2
に対する電解半田めっき処理、露出面にへの厚さ10μmm
程度以上の電解半田めっき層5の被着形成を実施例1の
場合に準じて行った(図3参照)。
Example 2 In the example of the embodiment schematically illustrated in FIGS. 1 to 7, the copper foil layer 1 surface of the punched laminated plate 2 (see FIG. 1) is thickened or if necessary. Panel copper plating layer after thin chemical copper plating and electrolytic copper plating
After forming 1b, a dry film is laminated, exposed and developed to perform pattern masking 4, and a region forming a circuit pattern connected to the surface mounting pad region is formed, for example, as shown in FIGS. ) Is patterned so as to form a non-linear shape. The copper plating layer 1c having a thickness of about 25 μmm is deposited / formed on the exposed surface including the inner wall surface of the connection hole 3 by the subsequent copper plating treatment (see FIG. 2), and the copper plating layer 1c is deposited / formed. Laminated board 2
Electrolytic solder plating treatment, thickness to exposed surface 10μmm
The electrolytic solder plating layer 5 was formed to a certain degree or more in accordance with the case of Example 1 (see FIG. 3).

【0023】次いで、前記パターンマスク4を剥離、除
去し、前記電解半田めっき層5をエッチングレジストと
して(図4参照)、露出している銅層1a,1b,1cを選択
的にエッチング除去し、電解半田めっき層5で表面が被
覆された表面実装用パッドなど含む回路パターンを形成
する。こうして、表面実装用パッドなど含む回路パター
ンを形成した後、たとえばドライフィルムのような感光
性材料を真空ラミネータなどを用いてラミネートし、前
記電解半田めっき層5の被着形成されている回路パター
ン中、電解半田めっき層5を残しておきたい領域、すな
わち表面実装用パッド面上やスルホール(接続用の孔)
3領域周面上などを、感光性材料層でマスキング6する
ように露光−現像し、露出している部分(領域)の電解
半田めっき層5を選択的に除去する(図5参照)。次い
で、前記感光性のマスク6を剥離・除去してから、所要
のヒュージング処理を行なう(図6参照)。
Next, the pattern mask 4 is peeled and removed, and the exposed copper layers 1a, 1b, 1c are selectively removed by etching using the electrolytic solder plating layer 5 as an etching resist (see FIG. 4), A circuit pattern including a surface mounting pad whose surface is covered with the electrolytic solder plating layer 5 is formed. In this way, after forming a circuit pattern including pads for surface mounting, a photosensitive material such as a dry film is laminated using a vacuum laminator or the like, and the circuit pattern in which the electrolytic solder plating layer 5 is formed is formed. , The area where the electrolytic solder plating layer 5 is to be left, that is, on the surface mounting pad surface or through hole (connection hole)
The peripheral surface of the three regions is exposed and developed so as to be masked 6 with the photosensitive material layer, and the electrolytic solder plating layer 5 in the exposed portion (region) is selectively removed (see FIG. 5). Next, the photosensitive mask 6 is peeled and removed, and then a required fusing treatment is performed (see FIG. 6).

【0024】本実施例においては、前記ヒュージング処
理に当たって、図8(a) 〜(c) に平面的に示すごとく、
残存・被着している電解半田めっき層5の端縁部、換言
すると電解半田めっき層5が被覆されている表面実装用
パッド領域に接続する回路パターンとの境界領域が、折
り曲げもしくは膨大部の形成などによって非直線化さ
れ、半田の流れ性の抑制ないし低減を図った構成を採っ
ている。このため、前記ヒュージング処理過程での電解
半田めっき層5の流動化ないし軟化による共晶・一様化
工程においても、電解半田めっきの被着を所望しない回
路パターン面に、電解半田めっきが流出・被着するのが
効果的に防止される。つまり、この実施例の場合では、
回路パターンの折り曲げもしくは膨大部などの非直線化
領域が半田流れ防止用のダムとして機能する。
In this embodiment, in the fusing process, as shown in plan view in FIGS. 8 (a) to 8 (c),
The edge area of the remaining / adhered electrolytic solder plating layer 5, in other words, the boundary area with the circuit pattern connected to the surface mounting pad area covered with the electrolytic solder plating layer 5 is bent or enlarged. It is made non-linear by formation and the like, and adopts a configuration for suppressing or reducing the flowability of solder. Therefore, even in the eutectic / uniformizing process by fluidizing or softening the electrolytic solder plating layer 5 in the fusing process, the electrolytic solder plating flows out to the circuit pattern surface to which electrolytic solder plating is not desired to be deposited. -Effectively prevented from wearing. That is, in the case of this embodiment,
Non-linear areas such as bent or swelled portions of the circuit pattern function as dams for preventing solder flow.

【0025】なお、このヒュージング処理において、前
記電解半田めっき層5をエッチングレジストとした表面
実装用パッドなど含む回路パターンの形成で、サイドエ
ッチングで凹面化した側面から突出した形を成していた
電解半田めっき層5が、回路パターン面(側面を含む)
に沿って流動して、一様に被覆する形態を採っていた。
前記ヒュージング処理後、電解半田めっき層5を残存
・被着させた領域を除いた所要の領域面に、いわゆるソ
ルダーレジストをコーティングする。次いで、外形加
工、電気検査を行い、たとえば、 300μm , 250μm ピ
ッチの表面実装用パッド面上に、厚さ10μm 以上の半田
層が一様に形成された表面実装用に適するプリント配線
板が得られた。
In this fusing process, a circuit pattern including a surface mounting pad using the electrolytic solder plating layer 5 as an etching resist was formed so as to project from the side surface concaved by side etching. The electrolytic solder plating layer 5 has a circuit pattern surface (including a side surface)
It had a form in which it uniformly flowed along with.
After the fusing treatment, a so-called solder resist is coated on a required area surface excluding the area where the electrolytic solder plating layer 5 remains and is adhered. Next, external processing and electrical inspection are performed to obtain a printed wiring board suitable for surface mounting, for example, where a solder layer with a thickness of 10 μm or more is uniformly formed on the surface mounting pad surface with a pitch of 300 μm and 250 μm. It was

【0026】なお、上記においては回路パターンを銅箔
層の選択的なエッチングによって形成したが、他の導電
性金属層の選択的なエッチングによって形成してもよ
く、さらに片面型もしくは多層配線型であっても勿論よ
い。
Although the circuit pattern is formed by selective etching of the copper foil layer in the above description, it may be formed by selective etching of another conductive metal layer. Of course it does.

【0027】また、上記実施例では表面実装用パッド面
上およびスルホール(接続用の孔)領域に、選択的に電
解半田めっき層5を設けた構成を例示したが、たとえば
接続用の孔を電子部品のリード端子接続に利用しない場
合など、接続用の孔領域には電解半田めっき層5を設け
ない構成としてもよく、あるいは表面実装用パッドを含
む回路パターン中、表面実装用パッド部とともに表面実
装用パッド以外の領域に電解半田めっき層6を設けた構
成としてもよい。
In the above embodiment, the electrolytic solder plating layer 5 is selectively provided on the surface mounting pad surface and through hole (connection hole) area. The electrolytic solder plating layer 5 may not be provided in the connection hole area when it is not used for connecting a lead terminal of a component, or in the circuit pattern including the surface mounting pad, the surface mounting pad portion is used together with the surface mounting pad portion. The electrolytic solder plating layer 6 may be provided in a region other than the pad for use.

【0028】[0028]

【発明の効果】上記したように本発明に係るプリント配
線板の製造方法によれば、繁雑な操作を要せずに高密度
の実装が可能で、かつ配線密度も高いプリント配線板を
容易に得ることができる。すなわち、先ず第1に、選択
エッチングによる回路パターン形成に先立って、被選択
エッチング導電金属層を給電用リードとし、少なくとも
表面実装用パッド面に、電解半田めっき層を形成する方
式を採っているため、給電用リードを別設する必要もな
くなり操作が簡略化する。そして、この給電用リードを
不要とすることは、その分、配線密度の低下の回避に寄
与する。第2には、電解半田めっき層は、いわゆるヒュ
ージング処理による共晶化・緻密化する過程で、不所望
な回路パターン領域に流失する恐れも容易、かつ確実に
回避されるので、信頼性の高い表面実装面(表面実装用
パッド面)を備えた、あるいは隣接する回路パターン間
でのショート発生もなく、すぐれた機能を保持・発揮す
る。さらに、第3には、表面実装用パッドをたとえば 3
00μm 以下の狭ピッチに設定することが可能で、またそ
の場合でも厚さ10μm 以上で、かつ厚さもほぼ一様な電
解半田めっき層が被着形成されるため、実装に当たって
の半田付け機能を十分に保持・発揮する。
As described above, according to the method for manufacturing a printed wiring board according to the present invention, it is possible to easily realize a printed wiring board which can be mounted at high density without complicated operations and has a high wiring density. Obtainable. That is, first of all, prior to the formation of the circuit pattern by the selective etching, the selective etching conductive metal layer is used as a power supply lead, and the electrolytic solder plating layer is formed on at least the surface mounting pad surface. The operation is simplified because there is no need to install a power supply lead separately. The elimination of the power supply lead contributes to the reduction of the wiring density. Secondly, the electrolytic solder plating layer can be easily and surely prevented from flowing into an undesired circuit pattern region in the process of eutecticization and densification by so-called fusing treatment, so that reliability can be improved. It has a high surface mounting surface (surface mounting pad surface) or does not cause short circuit between adjacent circuit patterns, and retains and exhibits excellent functions. Thirdly, a surface mounting pad, for example, 3
It is possible to set a narrow pitch of 00 μm or less, and even in that case, an electrolytic solder plating layer with a thickness of 10 μm or more and a substantially uniform thickness is deposited, so the soldering function for mounting is sufficient. Holds and demonstrates.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るプリント配線板の製造方法の実施
態様例において、銅箔張積層板面に接続用孔を穿設した
状態を示す断面図。
FIG. 1 is a cross-sectional view showing a state in which a connection hole is formed in a surface of a copper foil-clad laminate in an embodiment of a method for manufacturing a printed wiring board according to the present invention.

【図2】本発明に係るプリント配線板の製造方法の実施
態様例において、選択的に電気銅めっき層を設けた状態
を示す断面図。
FIG. 2 is a cross-sectional view showing a state in which an electrolytic copper plating layer is selectively provided in the embodiment example of the method for manufacturing a printed wiring board according to the present invention.

【図3】本発明に係るプリント配線板の製造方法の実施
態様例において、選択的に設けた銅めっき層上に電解半
田層を設けた状態を示す断面図。
FIG. 3 is a cross-sectional view showing a state in which an electrolytic solder layer is provided on a copper plating layer that is selectively provided in an embodiment of the method for manufacturing a printed wiring board according to the present invention.

【図4】本発明に係るプリント配線板の製造方法の実施
態様例において、電気銅めっき層および電解半田層を選
択的に設ける際用いたパターンマスクを剥離・除去した
状態を示す断面図。
FIG. 4 is a cross-sectional view showing a state in which a pattern mask used when selectively providing an electrolytic copper plating layer and an electrolytic solder layer is peeled and removed in an embodiment example of a method for manufacturing a printed wiring board according to the present invention.

【図5】本発明に係るプリント配線板の製造方法の実施
態様例において、選択エッチングして形成した表面実装
用パッドを含む回路パターン面の電解半田層をマスキン
グし、電解半田層を選択的に除去した状態を示す断面
図。
FIG. 5 is a view showing an embodiment of a method for manufacturing a printed wiring board according to the present invention, in which an electrolytic solder layer on a circuit pattern surface including a surface mounting pad formed by selective etching is masked to selectively remove the electrolytic solder layer. Sectional drawing which shows the removed state.

【図6】本発明に係るプリント配線板の製造方法の実施
態様例において、被着残存している電解半田層を流動・
共晶一様化した状態を示す断面図。
FIG. 6 shows a flow chart of flowing electrolytic solder layer remaining on an adherend in an example of an embodiment of a method for manufacturing a printed wiring board according to the present invention.
Sectional drawing which shows the state which the eutectic became uniform.

【図7】本発明に係るプリント配線板の製造方法の実施
態様例において、被着残存している電解半田層を流動・
共晶一様化(ヒュージング処理)に当たり電解半田層の
流出を防止するためのダムを設けた状態を示す断面図。
FIG. 7 is a flow chart showing the flow of the remaining electrolytic solder layer deposited in the embodiment of the method for manufacturing a printed wiring board according to the present invention.
Sectional drawing which shows the state which provided the dam for preventing outflow of an electrolytic solder layer at the time of eutectic uniformization (fusing process).

【図8】(a) 〜(c) は本発明に係るプリント配線板の製
造方法の他の実施態様を模式的に示すもので、最終段階
で被着残存する電解半田層の流動・共晶一様化(ヒュー
ジング処理)時における電解半田層の流出防止機能を、
連接する回路パターン部に付与させた互いに異なる回路
パターン例を示す平面図。
8 (a) to 8 (c) are schematic views showing another embodiment of the method for manufacturing a printed wiring board according to the present invention. Prevents the outflow of the electrolytic solder layer during uniformization (fusing treatment)
The top view which shows the circuit pattern example different from each other given to the circuit pattern part connected.

【符号の説明】[Explanation of symbols]

1a…銅箔層 1b…パネル銅めっき層 1c…電解銅め
っき層 2…積層板 3…接続用の孔 4…パターンマスク 5…電解半
田めっき層 6…マスキング(感光性マスク)
1a ... Copper foil layer 1b ... Panel copper plating layer 1c ... Electrolytic copper plating layer 2 ... Laminated plate 3 ... Connection hole 4 ... Pattern mask 5 ... Electrolytic solder plating layer 6 ... Masking (photosensitive mask)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板の少なくとも一主面に一体的
に形成された導体層面に表面実装用パッドを含む所要の
回路パターンをパターンニングする工程と、 前記回路パターンニングした面に電解半田めっき層を被
着形成する工程と、 前記被着形成した電解半田めっき層をエッチングレジス
トとして露出している導体層を選択エッチングして表面
実装用パッドを含む所要の回路パターンを形成する工程
と、 前記形成した少なくとも表面実装用パッドを含む所定の
回路パターン部にマスキングする工程と、 前記マスキングした領域以外の露出する電解半田めっき
層を除去する工程と、 前記電解半田めっき層の除去に用いたマスクを除去後、
残存・被着している電解半田めっき層の導体層パターン
面上端部に半田流出防止ダムを配置・形成する工程と、 前記半田流出防止ダムを配置・形成した後、加熱処理を
施して残存・被着している電解半田めっきを共晶半田化
する工程と、 前記加熱処理を施し共晶半田化した後、表面実装用パッ
ドを含む所定の回路パターン形成面にソルダーレジスト
層を被着・形成する工程とを具備して成ることを特徴と
するプリント配線板の製造方法。
1. A step of patterning a desired circuit pattern including a surface mounting pad on a conductor layer surface integrally formed on at least one main surface of an insulating substrate, and electrolytic solder plating on the circuit patterned surface. A step of depositing a layer, a step of selectively etching the exposed conductor layer using the deposited electrolytic solder plating layer as an etching resist to form a required circuit pattern including a surface mounting pad, A step of masking the formed circuit pattern portion including at least the surface mounting pad, a step of removing the exposed electrolytic solder plating layer other than the masked area, and a mask used for removing the electrolytic solder plating layer. After removal
A step of disposing / forming a solder outflow prevention dam on the upper end of the conductor layer pattern surface of the remaining / adhered electrolytic solder plating layer, and a step of disposing / forming the solder outflow prevention dam and then applying heat treatment to leave / remain. A step of converting the deposited electrolytic solder plating to eutectic solder, and after applying the heat treatment to form eutectic solder, deposit and form a solder resist layer on a predetermined circuit pattern forming surface including a surface mounting pad A method of manufacturing a printed wiring board, comprising:
【請求項2】 絶縁性基板の少なくとも一主面に一体的
に形成された導体層面に表面実装用パッドを含む所要の
回路パターンをパターンニングする工程と、 前記回路パターンニングした面に電解半田めっき層を被
着形成する工程と、 前記被着形成した電解半田めっき層をエッチングレジス
トとして露出している導体層を選択エッチングして表面
実装用パッドを含む所要の回路パターンを形成する工程
と、 前記形成した少なくとも表面実装用パッドを含む所定の
回路パターン部にマスキングする工程と、 前記マスキングした領域以外の露出する電解半田めっき
層を除去する工程と、 前記半田流出防止ダムを配置・形成した後、加熱処理を
施して残存・被着している電解半田めっきを共晶半田化
する工程と、 前記加熱処理を施し共晶半田化した後、表面実装用パッ
ドを含む所定の回路パターン形成面にソルダーレジスト
層を被着・形成する工程とを具備し、 前記導体層を選択エッチングして表面実装用パッドを含
む所要の回路パターンを形成する工程で、電解半田めっ
き層を残存・被着させる導体層パターンの連接領域部を
非直線に形成し、加熱処理による共晶半田化工程での半
田流出を防止するようにしたことを特徴とするプリント
配線板の製造方法。
2. A step of patterning a required circuit pattern including a surface-mounting pad on a conductor layer surface integrally formed on at least one main surface of an insulating substrate, and electrolytic solder plating on the circuit-patterned surface. A step of depositing a layer, a step of selectively etching the exposed conductor layer using the deposited electrolytic solder plating layer as an etching resist to form a required circuit pattern including a surface mounting pad, A step of masking the formed circuit pattern portion including at least the surface mounting pad, a step of removing the exposed electrolytic solder plating layer other than the masked area, and a step of arranging and forming the solder outflow prevention dam, A step of applying eutectic solder to the electrolytic solder plating remaining or adhered by heat treatment, and applying eutectic solder to the heat treatment And a step of depositing and forming a solder resist layer on a predetermined circuit pattern forming surface including the surface mounting pad, the conductor layer being selectively etched to form a required circuit pattern including the surface mounting pad. In the step of forming, the connecting area portion of the conductor layer pattern for leaving and depositing the electrolytic solder plating layer is formed to be non-linear to prevent the solder outflow in the eutectic soldering step due to the heat treatment. Printed wiring board manufacturing method.
JP13638792A 1992-05-28 1992-05-28 Manufacture of printed circuit board Withdrawn JPH05335722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13638792A JPH05335722A (en) 1992-05-28 1992-05-28 Manufacture of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13638792A JPH05335722A (en) 1992-05-28 1992-05-28 Manufacture of printed circuit board

Publications (1)

Publication Number Publication Date
JPH05335722A true JPH05335722A (en) 1993-12-17

Family

ID=15173969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13638792A Withdrawn JPH05335722A (en) 1992-05-28 1992-05-28 Manufacture of printed circuit board

Country Status (1)

Country Link
JP (1) JPH05335722A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011003928A (en) * 2010-09-17 2011-01-06 Rohm Co Ltd Light-emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011003928A (en) * 2010-09-17 2011-01-06 Rohm Co Ltd Light-emitting device

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A300 Withdrawal of application because of no request for examination

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Effective date: 19990803