JP2004072027A - Method of manufacturing wiring board with bump electrode - Google Patents

Method of manufacturing wiring board with bump electrode Download PDF

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Publication number
JP2004072027A
JP2004072027A JP2002232716A JP2002232716A JP2004072027A JP 2004072027 A JP2004072027 A JP 2004072027A JP 2002232716 A JP2002232716 A JP 2002232716A JP 2002232716 A JP2002232716 A JP 2002232716A JP 2004072027 A JP2004072027 A JP 2004072027A
Authority
JP
Japan
Prior art keywords
wiring board
forming
metal layer
circuit
photosensitive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002232716A
Other languages
Japanese (ja)
Inventor
Yutaka Yoshino
吉野 裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon CMK Corp
CMK Corp
Original Assignee
Nippon CMK Corp
CMK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon CMK Corp, CMK Corp filed Critical Nippon CMK Corp
Priority to JP2002232716A priority Critical patent/JP2004072027A/en
Publication of JP2004072027A publication Critical patent/JP2004072027A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board equipped with bump electrodes, which is capable of easily forming the fine bump electrodes flat. <P>SOLUTION: The method of manufacturing the wiring board equipped with bump electrodes comprises a first process of forming a conductor circuit by electroplating on a metal layer equipped with a mold-release support, a second process of fixing an insulating board to the conductor circuit by thermocompression bonding to form a flat circuit on the insulating board, a third process of separating the mold-release support to expose the metal layer after the flat circuit is formed, and a fourth process of forming the bump electrodes on the exposed metal layer by electroplating. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は突起電極付き配線基板の製造方法に関する。
【0002】
【従来の技術】
従来、突起電極付き配線基板は図2に示される工程により製造されていた。
すなわち、まず銅張りした基材11を用意し(図2(1))、銅箔上に感光性エッチングレジスト12を形成する(図2(2))。次いで、回路非形成部の感光性エッチングレジスト12を露光・現像し、開口部を設ける(図2(3))。次いで、露出した銅をエッチングする(図2(4))。次いで、感光性エッチングレジスト12を剥離する(図2(5))。次いで、全面に無電解銅めっき13を施す(図2(6))。次いで、感光性めっきレジスト14を形成する(図2(7))。次いで、ランド15対応部の感光性めっきレジスト14を露光・現像し、開口部を設ける(図2(8))。次いで、感光性めっきレジスト14の当該開口部に電解銅めっきによる突起電極16を形成する(図2(9))。次いで、感光性めっきレジスト14を剥離する(図2(10))。次いで、無電解銅めっきのみをエッチングして(図2(11))、突起電極付き配線基板を製造していた。
【0003】
しかしながら、突起電極は微細なため、微細化に限界があるサブトラクティブ法による回路形成では、そもそも形成が難しいと言う問題があった。
さらに、突起電極を形成するランドに絶縁層とランドとの間に数十ミクロンメートルの凹凸ができ、突起電極を形成するランドが微細なため、感光性めっきレジストを露光・現像する際にも位置合わせによるズレが生じ易く、感光性エッチングレジストの開口部がランド15からズレた場合には、段差により図3に示すように突起電極16を平担に形成できず、後工程での部品実装時に支障が生じる問題も発生していた。
さらにまた、感光性めっきレジストを剥離後、余分な無電解銅めっきをエッチングする際に、突起電極の下のランドまでエッチングされてしまうという問題も看過し得なかった。
【0004】
【発明が解決しようとする課題】
本発明は上記の如き従来の問題に鑑みてなされたものであり、微細な突起電極を容易に、しかもランド上に突起電極を形成する際のめっきレジストに露光ズレが発生しても平坦な突起電極を形成することができる突起電極付き配線基板の製造方法を提供することを目的とする。
【0005】
【課題を解決するための手段】
本発明は、離型性支持体を備えた金属層に、電解めっきにて導体回路を形成する工程と、当該導体回路側に絶縁基板を熱圧着して該絶縁層に平坦な回路を形成する工程と、当該回路形成後、離型性支持体を剥離して金属層を露出せしめる工程と、当該露出した金属層に電解めっきにて突起電極を形成する工程とを有することを特徴とする突起電極付き配線基板の製造方法により上記の目的を達成したものである。
【0006】
【発明の実施の形態】
以下本発明の実施の形態を図1と共に説明する。
【0007】
まず、金属層たる銅箔1a(3〜5μm)に離型性支持体であるキャリア銅箔1b(35μm)を備えた銅キャリア付銅箔1を用意する(図1(1))。ここでは、離型性支持体として銅キャリアを用いたが、銅キャリアにこだわることはなく、離型性支持体であれば、フィルムタイプのものあるいはステンレス等の金属板を使用しても構わない。
【0008】
次いで、銅箔1a側に感光性めっきレジスト2を形成する(図1(2))。次いで、導体回路形成部の感光性めっきレジスト2を露光・現像し、開口部を設ける(図1(3))。次いで、感光性めっきレジスト2の当該開口部に金属めっきを電気的に析出させ、それを導体回路3とする(図1(4))。
【0009】
尚、ここに金属めっきの金属としては、Cu、Ni、Au、Cr、Ag、Sn等が挙げられ、またはんだ等の合金でも構わない。また、キャリアの銅箔と異なる金属を析出させ、回路形成時に選択エッチングができるようにしても構わない。
【0010】
次いで、析出させた金属めっきを粗化4する(図1(5))。次いで、感光性めっきレジスト2を剥離する(図1(6))。次いで、導体回路3側に絶縁基板5を熱圧着することによって、導体回路3を当該絶縁基板5に埋め込む(図1(7))。尚、ここに絶縁基板5の材料は、熱硬化性樹脂、熱可塑性樹脂あるいは液晶ポリマー等の如何を問わない。
【0011】
次いで、キャリア銅箔1bを剥離する(図1(8))。次いで、突起電極5の厚みに応じて、感光性めっきレジスト2を10〜60μmの厚みで形成する(図1(9))。次いで、突起電極形成部の感光性めっきレジスト2を露光・現像し、開口部を設ける(図1(10))。次いで、感光性めっきレジスト2の当該開口部に突起電極6を電解めっきにて形成する(図1(11))。次いで、感光性めっきレジスト2を剥離する(図1(12))。次いで、露出した銅箔1aをエッチングして(図1(13))、突起電極付き配線基板を得る。
【0012】
【発明の効果】
本発明方法は、離型性支持体を備えた金属層を利用して、微細な導体回路を形成すると共に、転写により絶縁基板に導体回路を埋め込んでいるため、微細なランドを平滑に形成でき、かつその同一の金属層を利用して突起電極を電解めっきにて形成しているため、従来の如き無電解銅めっき工程が省け、微細な突起電極を容易に形成することができる。しかも微細なランド上に突起電極を形成する際のめっきレジストに露光ズレが発生しても、本発明方法によれば、前記の如く微細ランドが絶縁基板に埋め込まれているので、平坦な金属層に突起電極が形成される結果、突起電極も平坦に形成される。
【図面の簡単な説明】
【図1】本発明方法による製造例を示す断面工程説明図。
【図2】従来方法による製造例を示す断面工程説明図。
【図3】従来方法において露光ズレが発生した場合の突起電極の形状を示す断面説明図。
【符号の説明】
1:キャリア付き銅箔
1a:銅箔
1b:キャリア銅箔
2,14:感光性めっきレジスト
3:導体回路
4:粗化
5:絶縁基板
6,16:突起電極
11:銅張りした基材
12:感光性エッチングレジスト
13:無電解銅めっき
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board with bump electrodes.
[0002]
[Prior art]
Conventionally, a wiring board with a protruding electrode has been manufactured by the process shown in FIG.
That is, first, a copper-clad base material 11 is prepared (FIG. 2 (1)), and a photosensitive etching resist 12 is formed on a copper foil (FIG. 2 (2)). Next, the photosensitive etching resist 12 in the portion where the circuit is not formed is exposed and developed to provide an opening (FIG. 2 (3)). Next, the exposed copper is etched (FIG. 2D). Next, the photosensitive etching resist 12 is peeled off (FIG. 2 (5)). Next, electroless copper plating 13 is applied to the entire surface (FIG. 2 (6)). Next, a photosensitive plating resist 14 is formed (FIG. 2 (7)). Next, the photosensitive plating resist 14 corresponding to the land 15 is exposed and developed to provide an opening (FIG. 2 (8)). Next, a protruding electrode 16 is formed in the opening of the photosensitive plating resist 14 by electrolytic copper plating (FIG. 2 (9)). Next, the photosensitive plating resist 14 is peeled off (FIG. 2 (10)). Next, only the electroless copper plating was etched (FIG. 2 (11)) to produce a wiring board with bump electrodes.
[0003]
However, since the projection electrode is fine, there is a problem that formation is difficult in the first place by circuit formation by a subtractive method, which has a limit in miniaturization.
Furthermore, unevenness of several tens of micrometers is formed between the insulating layer and the land on the land on which the bump electrode is formed, and the land on which the bump electrode is formed is fine. When the opening of the photosensitive etching resist is displaced from the land 15 due to misalignment, the bump electrode 16 cannot be formed flat as shown in FIG. There was also a problem that caused trouble.
Furthermore, it was not possible to overlook the problem that, when the photosensitive electroless copper resist was peeled off and the unnecessary electroless copper plating was etched, the lands below the protruding electrodes were etched.
[0004]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and enables fine projection electrodes to be easily formed, and even when exposure deviation occurs in a plating resist when a projection electrode is formed on a land, flat projections are formed. An object of the present invention is to provide a method for manufacturing a wiring board with a protruding electrode on which an electrode can be formed.
[0005]
[Means for Solving the Problems]
The present invention provides a step of forming a conductive circuit by electrolytic plating on a metal layer provided with a releasable support, and forming a flat circuit on the insulating layer by thermocompression bonding an insulating substrate to the conductive circuit side. And a step of, after forming the circuit, peeling the releasable support to expose the metal layer, and forming a projecting electrode on the exposed metal layer by electrolytic plating. The above object has been achieved by a method of manufacturing a wiring board with electrodes.
[0006]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
[0007]
First, a copper foil 1 with a copper carrier having a copper foil 1a (3 to 5 μm) as a metal layer and a carrier copper foil 1b (35 μm) as a releasable support is prepared (FIG. 1 (1)). Here, a copper carrier was used as the releasable support, but the present invention is not limited to the copper carrier, and a releasable support may be a film type or a metal plate such as stainless steel. .
[0008]
Next, a photosensitive plating resist 2 is formed on the copper foil 1a side (FIG. 1 (2)). Next, the photosensitive plating resist 2 in the conductor circuit forming portion is exposed and developed to provide an opening (FIG. 1 (3)). Next, metal plating is electrically deposited on the opening of the photosensitive plating resist 2 to form a conductive circuit 3 (FIG. 1 (4)).
[0009]
Here, as the metal for the metal plating, Cu, Ni, Au, Cr, Ag, Sn and the like may be mentioned, or an alloy such as solder may be used. Alternatively, a metal different from the copper foil of the carrier may be deposited so that selective etching can be performed at the time of circuit formation.
[0010]
Next, the deposited metal plating is roughened 4 (FIG. 1 (5)). Next, the photosensitive plating resist 2 is peeled off (FIG. 1 (6)). Next, the conductive circuit 3 is embedded in the insulating substrate 5 by thermocompression bonding of the insulating substrate 5 to the conductive circuit 3 side (FIG. 1 (7)). Here, the material of the insulating substrate 5 is not limited to a thermosetting resin, a thermoplastic resin, a liquid crystal polymer or the like.
[0011]
Next, the carrier copper foil 1b is peeled off (FIG. 1 (8)). Next, the photosensitive plating resist 2 is formed in a thickness of 10 to 60 μm according to the thickness of the bump electrode 5 (FIG. 1 (9)). Next, the photosensitive plating resist 2 in the protruding electrode forming portion is exposed and developed to provide an opening (FIG. 1 (10)). Next, a protruding electrode 6 is formed in the opening of the photosensitive plating resist 2 by electrolytic plating (FIG. 1 (11)). Next, the photosensitive plating resist 2 is peeled off (FIG. 1 (12)). Next, the exposed copper foil 1a is etched (FIG. 1 (13)) to obtain a wiring board with bump electrodes.
[0012]
【The invention's effect】
The method of the present invention utilizes a metal layer provided with a releasable support, forms a fine conductor circuit, and embeds the conductor circuit in an insulating substrate by transfer, so that a fine land can be formed smoothly. In addition, since the protruding electrode is formed by electrolytic plating using the same metal layer, a conventional electroless copper plating step can be omitted, and a fine protruding electrode can be easily formed. In addition, even if exposure deviation occurs in the plating resist when forming the protruding electrode on the fine land, according to the method of the present invention, since the fine land is embedded in the insulating substrate as described above, a flat metal layer is formed. As a result, the protruding electrodes are formed flat.
[Brief description of the drawings]
FIG. 1 is a sectional process explanatory view showing a production example according to the method of the present invention.
FIG. 2 is a sectional process explanatory view showing a production example according to a conventional method.
FIG. 3 is an explanatory sectional view showing a shape of a protruding electrode when an exposure shift occurs in a conventional method.
[Explanation of symbols]
1: Copper foil with carrier 1a: Copper foil 1b: Copper foil 2, 14: Photosensitive plating resist 3: Conductive circuit 4: Roughening 5: Insulating substrates 6, 16: Projecting electrode 11: Copper-clad base material 12: Photosensitive etching resist 13: electroless copper plating

Claims (1)

離型性支持体を備えた金属層に、電解めっきにて導体回路を形成する工程と、当該導体回路側に絶縁基板を熱圧着して該絶縁層に平坦な回路を形成する工程と、当該回路形成後、離型性支持体を剥離して金属層を露出せしめる工程と、当該露出した金属層に電解めっきにて突起電極を形成する工程とを有することを特徴とする突起電極付き配線基板の製造方法。A step of forming a conductor circuit by electrolytic plating on a metal layer provided with a releasable support, and a step of forming a flat circuit on the insulation layer by thermocompression bonding an insulating substrate to the conductor circuit side; A wiring board with a protruding electrode, comprising: a step of exposing the metal layer by peeling the releasable support after forming the circuit; and a step of forming a protruding electrode on the exposed metal layer by electrolytic plating. Manufacturing method.
JP2002232716A 2002-08-09 2002-08-09 Method of manufacturing wiring board with bump electrode Pending JP2004072027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002232716A JP2004072027A (en) 2002-08-09 2002-08-09 Method of manufacturing wiring board with bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002232716A JP2004072027A (en) 2002-08-09 2002-08-09 Method of manufacturing wiring board with bump electrode

Publications (1)

Publication Number Publication Date
JP2004072027A true JP2004072027A (en) 2004-03-04

Family

ID=32018032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002232716A Pending JP2004072027A (en) 2002-08-09 2002-08-09 Method of manufacturing wiring board with bump electrode

Country Status (1)

Country Link
JP (1) JP2004072027A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006134220A1 (en) * 2005-06-16 2006-12-21 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
KR100757910B1 (en) 2006-07-06 2007-09-11 삼성전기주식회사 Buried pattern substrate and manufacturing method thereof
WO2011078031A1 (en) * 2009-12-22 2011-06-30 株式会社メイコー Process for production of printed circuit board, and printed circuit board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006134220A1 (en) * 2005-06-16 2006-12-21 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
GB2441265A (en) * 2005-06-16 2008-02-27 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
GB2441265B (en) * 2005-06-16 2012-01-11 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
US8225499B2 (en) 2005-06-16 2012-07-24 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
KR100757910B1 (en) 2006-07-06 2007-09-11 삼성전기주식회사 Buried pattern substrate and manufacturing method thereof
WO2011078031A1 (en) * 2009-12-22 2011-06-30 株式会社メイコー Process for production of printed circuit board, and printed circuit board
JP2011134758A (en) * 2009-12-22 2011-07-07 Meiko:Kk Manufacturing method for printed board and printed board

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