JP2001053189A - Wiring board and manufacturing method thereof - Google Patents
Wiring board and manufacturing method thereofInfo
- Publication number
- JP2001053189A JP2001053189A JP22914099A JP22914099A JP2001053189A JP 2001053189 A JP2001053189 A JP 2001053189A JP 22914099 A JP22914099 A JP 22914099A JP 22914099 A JP22914099 A JP 22914099A JP 2001053189 A JP2001053189 A JP 2001053189A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- solder
- wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線基板とその製
造方法に関する。The present invention relates to a wiring board and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】配線基板として、ＬＳＩチップを搭載
し、プリント配線等に接続される、半導体実装用インタ
ーポーザー等と称されるものがある。2. Description of the Related Art As a wiring board, there is a so-called interposer for mounting a semiconductor on which an LSI chip is mounted and which is connected to a printed wiring or the like.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上述した配
線基板において要求されることの一つは、実装密度を高
めることである。この実装密度は、例えば配線基板の両
側の主面にＬＳＩチップを搭載できるようにしたり、Ｌ
ＳＩチップを搭載した複数の配線基板同士を積層できる
ようにすれば、顕著に高めることが出来るが、従来にお
いてはそれは容易には為し難かった。One of the requirements of the above-mentioned wiring board is to increase the mounting density. The mounting density is, for example, such that an LSI chip can be mounted on the main surfaces on both sides of the wiring board,
If a plurality of wiring boards on which an SI chip is mounted can be stacked, the number of wiring boards can be significantly increased, but conventionally, this has been difficult.
【０００４】本発明はこのような問題点を解決すべく為
されたものであり、両側の主面にＬＳＩチップを搭載で
きるようにしたり、ＬＳＩチップを搭載した複数の配線
基板同士を積層できるようにすることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and it has been made possible to mount an LSI chip on the main surfaces on both sides or to stack a plurality of wiring boards on which the LSI chip is mounted. The purpose is to.
【０００５】[0005]
【課題を解決するための手段】請求項１の配線基板は、
上下間導通用開口を有する絶縁性樹脂膜の一方の側に配
線膜が、他方の側に上記開口を通じて上記配線膜に接続
された互いに二通りの異なる高さを有する金属突起がそ
れぞれ形成されたことを特徴とする。According to a first aspect of the present invention, there is provided a wiring board comprising:
A wiring film was formed on one side of an insulating resin film having an opening for vertical conduction, and a metal projection having two different heights connected to the wiring film through the opening was formed on the other side. It is characterized by the following.
【０００６】請求項２の配線基板は、請求項１記載の配
線基板において、低い金属突起がフリップチップボンデ
ィング用突起とされ、上記低い金属突起にＬＳＩチップ
がボンディングされたことを特徴とする。According to a second aspect of the present invention, there is provided the wiring board according to the first aspect, wherein the low metal projection is a flip chip bonding projection, and an LSI chip is bonded to the low metal projection.
【０００７】請求項３の配線基板は、請求項１又は２記
載の配線基板において、上下間導通用開口を有する絶縁
性樹脂膜の配線膜が形成された側にＬＳＩチップが設置
されたことを特徴とする。According to a third aspect of the present invention, there is provided the wiring board according to the first or second aspect, wherein the LSI chip is provided on the side of the insulating resin film having an opening for vertical conduction on which the wiring film is formed. Features.
【０００８】請求項４の配線基板の製造方法は、ベース
メタルの一方の主面に第１の半田膜を選択的に形成し、
更に該主面上に上記半田膜上も含め金属膜を形成し、該
金属膜上に、後で形成される金属突起と対応する位置に
上下間導通用開口のある絶縁膜を形成し、該絶縁膜上に
配線膜を形成し、上記ベースメタルの他方の主面の高い
金属突起を形成すべき位置に第２の半田膜を形成し、そ
の後、上記第２の半田膜をマスクとして上記ベースメタ
ルをエッチングすると共に、上記第２の半田膜及び上記
第１の半田膜をマスクとして上記金属膜をエッチングし
て上記金属膜とベースメタルからなる高い金属突起と、
上記金属膜からなる低い金属突起を形成することを特徴
とする。According to a fourth aspect of the present invention, a first solder film is selectively formed on one main surface of a base metal,
Further, a metal film including the solder film is formed on the main surface, and an insulating film having an opening for vertical conduction is formed on the metal film at a position corresponding to a metal projection to be formed later. Forming a wiring film on the insulating film, forming a second solder film on the other main surface of the base metal at a position where a high metal projection is to be formed, and then using the second solder film as a mask, Etching a metal, etching the metal film using the second solder film and the first solder film as a mask, and forming a high metal projection composed of the metal film and a base metal;
A low metal projection made of the above metal film is formed.
【０００９】請求項５の配線基板の製造方法は、請求項
４の配線基板の製造方法において、高い金属突起と低い
金属突起を形成した後、半田のリフロー処理により第１
の半田膜で低い金属突起表面を覆い、第２の半田膜で高
い金属突起表面を覆う状態にすることを特徴とする。According to a fifth aspect of the present invention, in the method for manufacturing a wiring board according to the fourth aspect, after forming the high metal projection and the low metal projection, the first method is performed by reflow soldering.
The second solder film covers the lower metal projection surface and the second solder film covers the higher metal projection surface.
【００１０】[0010]
【発明の実施の形態】以下、本発明を図示実施例に従っ
て詳細に説明する。図１（Ａ）〜（Ｄ）及び図２（Ｅ）
〜（Ｈ）は本発明配線基板の製造方法の一つの実施例を
工程順（Ａ）〜（Ｈ）に示す断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. 1 (A) to 1 (D) and FIG. 2 (E)
(H) to (H) are sectional views showing one embodiment of the method for manufacturing a wiring board of the present invention in the order of steps (A) to (H).
【００１１】（Ａ）例えば銅或いは銅合金からなるベー
スメタル１を用意し、該ベースメタル１の一方の側（表
側）の表面に第１の半田膜２を選択的に形成する。該半
田膜２の形成は、例えば、フォトレジスト膜を露光、現
像することによりパターニングし、該フォトレジスト膜
をマスクとして電解メッキすることにより行う。該半田
膜２の形成位置は、後述する高さが二通りある金属突起
のうちの高さが低い方の金属突起を形成すべき位置と対
応したところである。図１（Ａ）は半田膜２形成後の状
態を示す。(A) A base metal 1 made of, for example, copper or a copper alloy is prepared, and a first solder film 2 is selectively formed on one side (front side) of the base metal 1. The formation of the solder film 2 is performed by, for example, patterning the photoresist film by exposing and developing the photoresist film, and performing electrolytic plating using the photoresist film as a mask. The position at which the solder film 2 is formed corresponds to the position at which the lower metal protrusion of the two metal protrusions described later is to be formed. FIG. 1A shows a state after the formation of the solder film 2.
【００１２】（Ｂ）次に、上記ベースメタル１の上記一
方の側の表面上に、半田膜２形成部上をも含め、該半田
膜３よりも適宜厚い厚い銅膜３を全面的メッキにより形
成する。図１（Ｂ）は該銅膜３形成後の状態を示す。(B) Next, on the surface of the one side of the base metal 1, a thick copper film 3 appropriately thicker than the solder film 3 including the portion where the solder film 2 is formed is entirely plated. Form. FIG. 1B shows a state after the copper film 3 is formed.
【００１３】（Ｃ）次に、上記銅膜３上に絶縁性樹脂か
らなる膜、例えばポリイミド膜５を形成し、該ポリイミ
ド膜５を選択的にエッチングすることにより開口６を形
成する。該開口６は上記ベースメタル１と後で形成され
る配線膜を接続する開口、即ち上下間接続用開口であ
り、後述する低い金属突起（１３）が形成される部分に
対応する位置と、高い金属突起（１２）が形成される部
分に対応する位置に設けられる。(C) Next, a film made of an insulating resin, for example, a polyimide film 5 is formed on the copper film 3, and an opening 6 is formed by selectively etching the polyimide film 5. The opening 6 is an opening for connecting the base metal 1 and a wiring film to be formed later, that is, an opening for connecting between upper and lower sides, and a position corresponding to a portion where a low metal projection (13) to be described later is formed and a high position. It is provided at a position corresponding to the portion where the metal protrusion (12) is formed.
【００１４】（Ｄ）次に、上記ポリイミド膜５上に例え
ば銅からなる配線膜７を無電解メッキ及び電解メッキに
より形成する。具体的には、例えばＰｄ活性処理を施
し、その後、無電解Ｎｉ−Ｐメッキ等により薄い導電層
を全面的に形成し、その後、形成しべきパターンに対し
てネガのパターンのフォトレジスト膜を形成し、該フォ
トレジスト膜をマスクとして銅をメッキすることにより
配線膜７を形成し、その後、上記フォトレジスト膜を除
去し、しかる後、配線膜７をマスクとして、上記薄い導
電層をエッチングするという方法で配線膜７を形成す
る。図１（Ｄ）は配線膜７形成後の状態を示す。(D) Next, a wiring film 7 made of, for example, copper is formed on the polyimide film 5 by electroless plating and electrolytic plating. Specifically, for example, a Pd activation treatment is performed, and thereafter, a thin conductive layer is entirely formed by electroless Ni-P plating or the like, and then a photoresist film having a negative pattern is formed with respect to a pattern to be formed. Then, the wiring film 7 is formed by plating copper using the photoresist film as a mask, and thereafter, the photoresist film is removed. Thereafter, the thin conductive layer is etched using the wiring film 7 as a mask. The wiring film 7 is formed by the method. FIG. 1D shows a state after the wiring film 7 is formed.
【００１５】（Ｅ）次に、上記配線膜７上に絶縁性樹脂
からなる絶縁膜８を選択的に形成する。該絶縁膜８は後
でＬＳＩチップの電極にワイヤを接続される端子部分と
なる部分を露出させる開口９を有する。図２（Ｅ）は該
開口９を有する絶縁膜８の形成後の状態を示す。(E) Next, an insulating film 8 made of an insulating resin is selectively formed on the wiring film 7. The insulating film 8 has an opening 9 for exposing a portion which will be a terminal portion for connecting a wire to an electrode of an LSI chip later. FIG. 2E shows a state after the formation of the insulating film 8 having the opening 9.
【００１６】（Ｆ）その後、上記配線膜７の上記開口９
を通じて露出する部分及びベースメタル１の他方（裏
側）の面の後述する高い金属突起を形成すべき部分に半
田膜１０、１１をメッキにより形成する。図２（Ｆ）は
半田膜１０、１１形成後の状態を示す。半田膜１０は配
線膜７の開口９に露出する部分に形成された半田膜、半
田膜１１のベースメタル１の裏側の面に形成された半田
膜である。(F) Thereafter, the opening 9 of the wiring film 7 is formed.
The solder films 10 and 11 are formed by plating on the portion exposed through through and on the other (back side) surface of the base metal 1 where a high metal projection to be described later is to be formed. FIG. 2F shows a state after the formation of the solder films 10 and 11. The solder film 10 is a solder film formed on a portion of the wiring film 7 exposed to the opening 9 and a solder film formed on the surface of the solder film 11 on the back side of the base metal 1.
【００１７】（Ｇ）次に、上記半田膜２、１１に対して
は侵し得ず、銅に対しては侵し得るエッチング液を用い
て上記ベースメタル１及び銅膜３に対する裏側からのエ
ッチングを行う。換言すれば、半田膜２、１１をマスク
とするベースメタル１及び銅膜３に対する選択的エッチ
ングを行う。すると、図２（Ｇ）に示すように、半田膜
１１で覆われた部分にはベースメタル１及び銅膜３から
なる金属突起１２が形成され、半田膜２で覆われた部分
には銅膜３からなる金属突起１３が形成される。金属突
起１２はベースメタル１及び銅膜３からなるので、その
高さは略ベースメタル１と銅膜３の厚さの和になり、高
くなるのに対して、金属突起１３は銅膜３からのみなる
ので、その高さは略銅膜３の厚さになり、低くなる。(G) Next, the base metal 1 and the copper film 3 are etched from the back side using an etchant that cannot attack the solder films 2 and 11 but can attack copper. . In other words, selective etching is performed on the base metal 1 and the copper film 3 using the solder films 2 and 11 as a mask. Then, as shown in FIG. 2 (G), a metal projection 12 composed of the base metal 1 and the copper film 3 is formed on the portion covered with the solder film 11, and the copper film is formed on the portion covered with the solder film 2. 3 are formed. Since the metal protrusion 12 is composed of the base metal 1 and the copper film 3, the height thereof is substantially equal to the sum of the thicknesses of the base metal 1 and the copper film 3, and the height is increased. Therefore, the height is substantially equal to the thickness of the copper film 3 and becomes lower.
【００１８】（Ｈ）その後、リフロー処理することによ
り、金属突起１２、１３を覆う半田膜２、１１を整形す
ると、図２（Ｈ）に示すような配線基板１４ができる。
該配線基板が本発明配線基板の第１の実施例である。即
ち、本配線基板１４は、開口６を有する絶縁性樹脂膜
（ポリイミド）５の一方の側（表側）には、配線膜７が
形成され、該配線膜７上には後述するＬＳＩチップの電
極と接続される端子部分を露出させる開口９のある絶縁
膜８が形成され、該開口９には半田膜１０が形成されて
いる。(H) After that, when the solder films 2 and 11 covering the metal protrusions 12 and 13 are shaped by reflow treatment, a wiring board 14 as shown in FIG.
The wiring board is a first embodiment of the wiring board of the present invention. That is, in the present wiring board 14, a wiring film 7 is formed on one side (front side) of the insulating resin film (polyimide) 5 having the opening 6, and an electrode of an LSI chip described later is formed on the wiring film 7. An insulating film 8 having an opening 9 for exposing a terminal portion connected to the substrate is formed, and a solder film 10 is formed in the opening 9.
【００１９】また、上記絶縁性樹脂膜５の他方の側（裏
側）には、その開口６を通じて上記配線膜７と電気的に
接続された高さの異なる金属突起１２、１３が形成され
ている。そして、該金属突起１２、１３は半田２、１１
で覆われた状態になっている。低い金属突起１３はＬＳ
Ｉチップのフリップチップボンディング用として用いる
ことができ、高い金属突起１２は配線基板１４の外部端
子として用いることができる。On the other side (back side) of the insulating resin film 5, there are formed metal projections 12 and 13 of different heights electrically connected to the wiring film 7 through the opening 6. . The metal projections 12 and 13 are connected to the solders 2 and 11 respectively.
It is covered with. The low metal projection 13 is LS
It can be used for flip chip bonding of an I chip, and the high metal protrusion 12 can be used as an external terminal of the wiring board 14.
【００２０】図３（Ａ）〜（Ｄ）は図２（Ｈ）に示した
配線基板１４へのＬＳＩチップ１５、１６の搭載方法を
工程順に示す断面図である。 （Ａ）配線基板１４の裏側にＬＳＩチップ１５を低い金
属突起１３にてフリップチップボンディングすることに
より搭載する。図３（Ａ）はＬＳＩチップ１５のフリッ
プチップボンディング後の状態を示す。FIGS. 3A to 3D are sectional views showing a method of mounting the LSI chips 15 and 16 on the wiring board 14 shown in FIG. (A) The LSI chip 15 is mounted on the back side of the wiring board 14 by flip-chip bonding with the low metal projection 13. FIG. 3A shows a state of the LSI chip 15 after flip chip bonding.
【００２１】（Ｂ）次に、図３（Ｂ）に示すように、上
記配線基板１４・ＬＳＩチップ１５間を樹脂１７で封止
する。 （Ｃ）その後、配線基板１４の表側にＬＳＩチップ１６
をボンディングし、該ＬＳＩチップ１６の各電極と、配
線膜７の端子の半田膜１０との間をワイヤ１８により接
続する。図３（Ｃ）はワイヤボンディング後の状態を示
す。 （Ｄ）しかる後、図３（Ｄ）に示すようにＬＳＩチップ
１６を樹脂１９で封止する。(B) Next, as shown in FIG. 3B, the space between the wiring board 14 and the LSI chip 15 is sealed with a resin 17. (C) Then, the LSI chip 16 is placed on the front side of the wiring board 14.
Are bonded to each other, and each electrode of the LSI chip 16 is connected to the solder film 10 as a terminal of the wiring film 7 by a wire 18. FIG. 3C shows a state after wire bonding. (D) Thereafter, the LSI chip 16 is sealed with the resin 19 as shown in FIG.
【００２２】本配線基板１４によれば、上下間導通用開
口６を有する絶縁性樹脂膜（ポリイミド膜）５の表側に
配線膜７が形成され、該絶縁性樹脂膜５の裏側に上記開
口６を通じて上記配線膜７に接続された互いに二通りの
異なる高さの金属突起１２、１３が形成されているの
で、絶縁性樹脂膜５の表側と裏側の両方にＬＳＩチップ
１５、１６を搭載でき、配線基板１４の実装密度を高め
ることができる。According to the present wiring board 14, the wiring film 7 is formed on the front side of the insulating resin film (polyimide film) 5 having the opening 6 for vertical conduction, and the opening 6 is formed on the back side of the insulating resin film 5. Metal bumps 12 and 13 of two different heights connected to the wiring film 7 are formed on the insulating resin film 5 so that the LSI chips 15 and 16 can be mounted on both the front side and the back side of the insulating resin film 5. The mounting density of the wiring board 14 can be increased.
【００２３】尚、図２（Ｈ）に示した配線基板１４は、
上記絶縁性樹脂膜５の表側の配線が一層配線であるが、
この配線は２層配線或いはそれ以上の多層配線であって
も良い。また、上記配線基板１４の製造方法において
は、図２（Ｇ）に示したエッチング工程の終了後、図２
（Ｈ）で示す半田膜２、１１をリフロー処理する工程に
より金属突起１２、１３が半田で覆われた形状に整形さ
れるようにするが、必ずしもそのようにすることは不可
欠ではなく、エッチング工程の終了後、半田膜１０、１
２、１３を剥離により除去するようにしても良い。図４
（Ａ）はそのような半田膜１０、１２、１３を剥離した
場合の配線基板の例１４ａを示す断面図、（Ｂ）はその
配線基板１４ａに一つのＬＳＩチップ１６の搭載例を示
す断面図である。The wiring board 14 shown in FIG.
The wiring on the front side of the insulating resin film 5 is a single-layer wiring.
This wiring may be a two-layer wiring or a multilayer wiring of more layers. Further, in the method for manufacturing the wiring board 14, after the etching step shown in FIG.
The metal projections 12 and 13 are shaped into a shape covered with solder by the step of reflowing the solder films 2 and 11 shown in (H), but this is not essential, and the etching step is not essential. After the completion of the solder film 10, 1
2 and 13 may be removed by peeling. FIG.
(A) is a cross-sectional view showing an example 14a of a wiring board when such solder films 10, 12, and 13 are peeled off, and (B) is a cross-sectional view showing an example of mounting one LSI chip 16 on the wiring board 14a. It is.
【００２４】図５は配線基板１４、２４を二つ積層した
使用例を示す断面図であり、このような態様でも配線基
板を使用できる。配線基板１４は図２（Ｈ）に示したも
のと同じであるが、配線基板２４は配線基板１４の半田
膜１０に代えて半田バンプ２０を形成したもので、配線
基板１４、２４の裏面側にはそれぞれ低い金属突起１３
にてＬＳＩチップ１５、１５が搭載されているが、配線
基板１４の表側にはＬＳＩチップ１８が搭載されている
けれども配線基板２４の表側にはＬＳＩチップ１８を設
けず、半田バンプ２０をプリント配線基板２１の配線膜
２２との接続端子として用いる。そして、配線基板１４
と２４の高い金属突起１２・１２同士を例えば半田２３
等により接続してなる。これにより配線基板を複数積層
してより実装密度の向上を図ることができる。FIG. 5 is a cross-sectional view showing a usage example in which two wiring boards 14 and 24 are stacked, and a wiring board can be used in such an embodiment. The wiring board 14 is the same as that shown in FIG. 2H, but the wiring board 24 is formed by forming solder bumps 20 instead of the solder films 10 of the wiring board 14, and the back side of the wiring boards 14, 24. Each has a low metal projection 13
Although the LSI chips 15 are mounted on the wiring board 14, the LSI chip 18 is mounted on the front side of the wiring board 14, but the LSI chip 18 is not provided on the front side of the wiring board 24, and the solder bumps 20 are printed by wiring. It is used as a connection terminal with the wiring film 22 of the substrate 21. And the wiring board 14
And the high metal projections 12 are connected to each other by solder 23, for example.
And so on. This makes it possible to improve the mounting density by stacking a plurality of wiring boards.
【００２５】[0025]
【発明の効果】本発明配線基板によれば、上下間導通用
開口を有する絶縁性樹脂膜の表側に一層又は多層の配線
膜が形成され、該絶縁性樹脂膜の裏側に上記開口を通じ
て上記配線膜に接続された互いに二通りの異なる高さの
金属突起が形成されているので、絶縁性樹脂膜の表側と
裏側の低い金属突起のある部分の両方にＬＳＩチップを
搭載でき、配線基板の実装密度を高めることができる。According to the wiring board of the present invention, a single-layer or multi-layer wiring film is formed on the front side of the insulating resin film having the opening for vertical conduction, and the wiring is formed through the opening on the back side of the insulating resin film. Since two types of metal projections connected to the film and having different heights are formed, the LSI chip can be mounted on both the front side and the back side of the insulating resin film having the low metal projections, and the wiring board is mounted. Density can be increased.
【００２６】本発明配線基板の製造方法によれば、ベー
スメタルの一方の主面に第１の半田膜を選択的に形成
し、その主面上に上記半田膜上も含め金属膜を形成し、
該金属膜上に絶縁膜を介して配線膜を形成し、上記ベー
スメタルの他方の主面上に第２の半田膜を形成し、その
後、上記第２の半田膜をマスクとして上記ベースメタル
をエッチングすると共に、上記第２の半田膜及び上記第
１の半田膜をマスクとして上記金属膜をエッチングして
第２の半田膜とベースメタルからなる高い金属突起と、
第１の半田膜と上記金属膜からなる低い金属突起を形成
するので、上記本発明配線基板を得ることができる。ま
た、金属突起の形成後、マスクとして用いた半田膜に対
するリフロー処理を施すことにより、その半田で金属突
起を覆い、その半田を半田バンプとして利用できる。According to the method of manufacturing a wiring board of the present invention, a first solder film is selectively formed on one main surface of a base metal, and a metal film including the solder film is formed on the main surface. ,
A wiring film is formed on the metal film via an insulating film, a second solder film is formed on the other main surface of the base metal, and then the base metal is formed using the second solder film as a mask. Etching, the metal film is etched using the second solder film and the first solder film as a mask, and a high metal projection composed of a second solder film and a base metal;
Since the low metal projection made of the first solder film and the metal film is formed, the wiring board of the present invention can be obtained. After the formation of the metal projections, the solder projections are covered with the solder by performing a reflow process on the solder film used as the mask, and the solder can be used as solder bumps.
【図１】（Ａ）〜（Ｄ）は本発明配線基板の製造方法の
一つの実施例の前半を工程順に示す断面図である。FIGS. 1A to 1D are cross-sectional views showing the first half of one embodiment of a method of manufacturing a wiring board according to the present invention in the order of steps.
【図２】（Ｅ）〜（Ｈ）は上記実施例の後半を工程順に
示す断面図である。2 (E) to 2 (H) are cross-sectional views showing the latter half of the embodiment in the order of steps.
【図３】（Ａ）〜（Ｄ）は本発明配線基板への二つのＬ
ＳＩチップの搭載方法を工程順に示す断面図である。3 (A) to 3 (D) show two Ls on a wiring board of the present invention.
It is sectional drawing which shows the mounting method of SI chip in a process order.
【図４】（Ａ）はエッチング工程の終了後、マスクとし
て用いた半田膜を剥離により除去するようにした配線基
板の一例を示す断面図、（Ｂ）はその配線基板へＬＳＩ
チップを一つ搭載した状態を示す断面図である。FIG. 4A is a cross-sectional view showing an example of a wiring board in which a solder film used as a mask is removed by peeling after completion of an etching step, and FIG.
It is sectional drawing which shows the state which mounted one chip.
【図５】複数の配線基板を組み付けた配線基板の使用例
を示す断面図である。FIG. 5 is a cross-sectional view illustrating a usage example of a wiring board in which a plurality of wiring boards are assembled.
１・・・ベースメタル、２・・・半田膜、３・・金属
膜、５・・・絶縁性樹脂膜、６・・・開口、７・・・配
線膜、１０、１１・・・半田膜、１２・・・高い金属突
起、１３・・・低い金属突起、１４、１４ａ、２４・・
・配線基板、１５、１６・・・ＬＳＩチップ。DESCRIPTION OF SYMBOLS 1 ... Base metal, 2 ... Solder film, 3 ... Metal film, 5 ... Insulating resin film, 6 ... Opening, 7 ... Wiring film, 10, 11 ... Solder film , 12 ... high metal protrusion, 13 ... low metal protrusion, 14, 14a, 24, ...
-Wiring board, 15, 16, ... LSI chip.
Claims (5)
の側に一層或いは多層の配線膜が形成され、 上記樹脂膜の他方の側に上記開口を通じて上記配線膜に
接続された互いに二通りの異なる高さの金属突起が形成
されたことを特徴とする配線基板。1. A single-layer or multilayer wiring film is formed on one side of a resin film having an opening for vertical conduction, and is connected to the wiring film through the opening on the other side of the resin film in two ways. A metal projection having different heights formed thereon.
ング用突起とされ、 上記低い金属突起にＬＳＩチップがボンディングされた
ことを特徴とする請求項１記載の配線基板。2. The wiring board according to claim 1, wherein the low metal projection is a flip-chip bonding projection, and an LSI chip is bonded to the low metal projection.
或いは多層の配線膜が形成された側にＬＳＩチップが設
置されたことを特徴とする請求項１又は２記載の配線基
板。3. The wiring board according to claim 1, wherein an LSI chip is provided on a side of the resin film having an opening for vertical conduction, on a side on which one layer or a multilayer wiring film is formed.
膜を選択的に形成する工程と、 上記ベースメタルの上記主面上に上記半田膜上も含め金
属膜を形成する工程と、 上記金属膜上に、後で形成される金属突起と対応する位
置に上下間導通用開口のある絶縁膜を形成する工程と、 上記絶縁膜上に上記一層又は多層の配線膜を形成する工
程と、 上記ベースメタルの他方の主面の高い金属突起を形成す
べき位置に第２の半田膜を形成する工程と、 その後、上記第２の半田膜をマスクとして上記ベースメ
タルを上記他方の主面側からエッチングすると共に、上
記第２の半田膜及び上記第１の半田膜をマスクとして上
記金属膜をエッチングして上記金属膜と上記ベースメタ
ルからなる高い金属突起と、上記金属膜からなる上記低
い金属突起を形成する工程と、 を有することを特徴とする配線基板の製造方法。4. A step of selectively forming a first solder film on one main surface of the base metal; and a step of forming a metal film on the main surface of the base metal including the solder film. A step of forming an insulating film having an opening for vertical conduction at a position corresponding to a metal projection to be formed later on the metal film; and a step of forming the single-layer or multilayer wiring film on the insulating film. Forming a second solder film at a position on the other main surface of the base metal where a high metal projection is to be formed; and thereafter, applying the base metal to the other main surface using the second solder film as a mask. While etching from the side, the metal film is etched by using the second solder film and the first solder film as a mask, and the high metal projection made of the metal film and the base metal and the low metal projection made of the metal film are formed. Form metal protrusions Method for manufacturing a wiring substrate characterized by having a step.
ルを他方の主面側からエッチングすると共に、上記第２
の半田膜及び第１の半田膜をマスクとして金属膜をエッ
チングして該金属膜と上記ベースメタルからなる高い金
属突起と、該金属膜からなる上記低い金属突起を形成す
る工程の後に、上記第１及び第２の半田膜に対するリフ
ローにより上記高い金属突起及び低い金属突起を該半田
膜の半田で覆った状態にする工程を有することを特徴と
する請求項４記載の配線基板の製造方法5. The base metal is etched from the other main surface side using the second solder film as a mask, and the second metal is etched.
After the step of forming a high metal projection made of the metal film and the base metal and forming the low metal projection made of the metal film by etching the metal film using the solder film and the first solder film as masks, 5. The method for manufacturing a wiring board according to claim 4, further comprising a step of reflowing the first and second solder films so that the high and low metal protrusions are covered with the solder of the solder film.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22914099A JP3497774B2 (en) | 1999-08-13 | 1999-08-13 | Wiring board and its manufacturing method |
| US09/466,895 US6782610B1 (en) | 1999-05-21 | 1999-12-20 | Method for fabricating a wiring substrate by electroplating a wiring film on a metal base |
| KR1020000021688A KR100553405B1 (en) | 1999-05-21 | 2000-04-24 | Wiring substrate for mounting semiconductor elements and fabricating method thereof |
| TW089107741A TW508705B (en) | 1999-05-21 | 2000-04-25 | Wiring substrate and fabricating method thereof |
| KR1020050003199A KR100562601B1 (en) | 1999-05-21 | 2005-01-13 | Wiring substrate for mounting semiconductor elements and fabricating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22914099A JP3497774B2 (en) | 1999-08-13 | 1999-08-13 | Wiring board and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001053189A true JP2001053189A (en) | 2001-02-23 |
| JP3497774B2 JP3497774B2 (en) | 2004-02-16 |
Family
ID=16887401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22914099A Expired - Fee Related JP3497774B2 (en) | 1999-05-21 | 1999-08-13 | Wiring board and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3497774B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004273785A (en) * | 2003-03-10 | 2004-09-30 | Advanced Systems Japan Inc | Connection terminal and manufacturing method therefor |
| JP2010004064A (en) * | 1999-08-02 | 2010-01-07 | Toyo Kohan Co Ltd | Method of manufacturing semiconductor package unit |
-
1999
- 1999-08-13 JP JP22914099A patent/JP3497774B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010004064A (en) * | 1999-08-02 | 2010-01-07 | Toyo Kohan Co Ltd | Method of manufacturing semiconductor package unit |
| JP2004273785A (en) * | 2003-03-10 | 2004-09-30 | Advanced Systems Japan Inc | Connection terminal and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3497774B2 (en) | 2004-02-16 |
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