JP3497774B2 - Wiring board and its manufacturing method - Google Patents
Wiring board and its manufacturing methodInfo
- Publication number
- JP3497774B2 JP3497774B2 JP22914099A JP22914099A JP3497774B2 JP 3497774 B2 JP3497774 B2 JP 3497774B2 JP 22914099 A JP22914099 A JP 22914099A JP 22914099 A JP22914099 A JP 22914099A JP 3497774 B2 JP3497774 B2 JP 3497774B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- solder
- wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線基板とその製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board and its manufacturing method.
【０００２】[0002]
【従来の技術】配線基板として、ＬＳＩチップを搭載
し、プリント配線等に接続される、半導体実装用インタ
ーポーザー等と称されるものがある。2. Description of the Related Art There is a wiring board called an interposer for mounting semiconductors, which is mounted with an LSI chip and is connected to a printed wiring or the like.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上述した配
線基板において要求されることの一つは、実装密度を高
めることである。この実装密度は、例えば配線基板の両
側の主面にＬＳＩチップを搭載できるようにしたり、Ｌ
ＳＩチップを搭載した複数の配線基板同士を積層できる
ようにすれば、顕著に高めることが出来るが、従来にお
いてはそれは容易には為し難かった。By the way, one of the requirements for the above-mentioned wiring board is to increase the packaging density. This mounting density is, for example, such that the LSI chips can be mounted on both main surfaces of the wiring board,
It is possible to remarkably improve the performance by stacking a plurality of wiring boards on which SI chips are mounted, but in the past, it was difficult to do so easily.
【０００４】本発明はこのような問題点を解決すべく為
されたものであり、両側の主面にＬＳＩチップを搭載で
きるようにしたり、ＬＳＩチップを搭載した複数の配線
基板同士を積層できるようにすることを目的とする。The present invention has been made to solve such a problem, and makes it possible to mount an LSI chip on both main surfaces or to stack a plurality of wiring boards on which an LSI chip is mounted. The purpose is to
【０００５】[0005]
【課題を解決するための手段】請求項１の配線基板は、
上下間導通用開口を有する樹脂膜の一方の側に配線膜
が、他方の側に上記開口を通じて上記配線膜に接続され
た銅或いは銅合金からなる金属突起と該金属突起より高
さの低い銅からなる金属突起とが形成され、高さの低い
金属突起がフリップチップボンディング用突起とされ、
上記高さの高い金属突起が外部端子とされたことを特徴
とする。A wiring board according to claim 1 is
A wiring film is provided on one side of the resin film having an opening for vertical conduction, and a metal projection made of copper or a copper alloy connected to the wiring film through the opening on the other side and a copper having a height lower than the metal projection. Is formed, and the metal projection with a low height is used as a flip chip bonding projection.
It is characterized in that the metal projection having a high height is used as an external terminal.
【０００６】 請求項２の配線基板は、請求項１の配線
基板において、上記上下間導通用開口を有する絶縁性樹
脂膜の配線膜が形成された側にＬＳＩチップが設置され
たことを特徴とする。A wiring board according to a second aspect is the wiring board according to the first aspect, wherein an LSI chip is installed on a side where the wiring film of the insulating resin film having the opening for vertical conduction is formed. To do.
【０００７】 請求項３の配線基板の製造方法は、ベー
スメタルの一方の主面に第１の半田膜を選択的に形成
し、更に該主面上に上記半田膜上も含め金属膜を形成
し、該金属膜上に、後で形成される金属突起と対応する
位置に上下間導通用開口のある絶縁膜を形成し、該絶縁
膜上に配線膜を形成し、上記べースメタルの他方の主面
の高い金属突起を形成すべき位置に第２の半田膜を形成
し、その後、上記第２の半田膜をマスクとして上記べー
スメタルをエッチングすると共に、上記第２の半田膜及
び上記第１の半田膜をマスクとして上記金属膜をエッチ
ングして上記金属膜とべ一スメタルからなる高い金属突
起と、上記金属膜からなる低い金属突起を形成すること
を特徴とする。According to a third aspect of the present invention, there is provided a method of manufacturing a wiring board, wherein a first solder film is selectively formed on one main surface of a base metal, and a metal film including the solder film is formed on the main surface. Then, an insulating film having a vertical conduction opening is formed on the metal film at a position corresponding to a metal protrusion to be formed later, a wiring film is formed on the insulating film, and the other of the base metals is formed. A second solder film is formed on the main surface at a position where a high metal protrusion is to be formed, and then the base metal is etched using the second solder film as a mask, and the second solder film and the first solder film are formed. The metal film is etched using the solder film as a mask to form high metal protrusions made of the metal film and the base metal and low metal protrusions made of the metal film.
【０００８】 請求項４の配線基板の製造方法は、請求
項３の配線基板の製造方法において、高い金属突起と低
い金属突起を形成した後、半田のリフロー処理により第
１の半田膜で低い金属突起表面を覆い、第２の半田膜で
高い金属突起表面を覆う状態にすることを特徴とする。A method for manufacturing a wiring board according to a fourth aspect is the method for manufacturing a wiring board according to the third aspect, wherein after forming the high metal protrusions and the low metal protrusions, a low metal is formed in the first solder film by a reflow process of solder. It is characterized in that the projection surface is covered and the high metal projection surface is covered with the second solder film.
【０００９】[0009]
【発明の実施の形態】以下、本発明を図示実施例に従っ
て詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the illustrated embodiments.
【００１０】 図１（Ａ）〜（Ｄ）及び図２（Ｅ）〜
（Ｈ）は本発明配線基板の製造方法の一つの実施例を工
程順（Ａ）〜（Ｈ）に示す断面図である。1A to 1D and 2E to
(H) is sectional drawing which shows one Example of the manufacturing method of the wiring substrate of this invention in order of process (A)-(H).
【００１１】（Ａ）例えば銅或いは銅合金からなるベー
スメタル１を用意し、該ベースメタル１の一方の側（表
側）の表面に第１の半田膜２を選択的に形成する。該半
田膜２の形成は、例えば、フォトレジスト膜を露光、現
像することによりパターニングし、該フォトレジスト膜
をマスクとして電解メッキすることにより行う。該半田
膜２の形成位置は、後述する高さが二通りある金属突起
のうちの高さが低い方の金属突起を形成すべき位置と対
応したところである。図１（Ａ）は半田膜２形成後の状
態を示す。(A) A base metal 1 made of, for example, copper or a copper alloy is prepared, and a first solder film 2 is selectively formed on the surface of one side (front side) of the base metal 1. The solder film 2 is formed by, for example, patterning by exposing and developing a photoresist film, and electrolytically plating using the photoresist film as a mask. The position where the solder film 2 is formed corresponds to the position where the metal projection having the lower height of the two metal projections having two different heights to be described later is to be formed. FIG. 1A shows a state after the solder film 2 is formed.
【００１２】（Ｂ）次に、上記ベースメタル１の上記一
方の側の表面上に、半田膜２形成部上をも含め、該半田
膜３よりも適宜厚い厚い銅膜３を全面的メッキにより形
成する。図１（Ｂ）は該銅膜３形成後の状態を示す。(B) Next, on the surface of the one side of the base metal 1, including the solder film 2 forming portion, a copper film 3 thicker than the solder film 3 is appropriately plated. Form. FIG. 1B shows a state after the copper film 3 is formed.
【００１３】（Ｃ）次に、上記銅膜３上に絶縁性樹脂か
らなる膜、例えばポリイミド膜５を形成し、該ポリイミ
ド膜５を選択的にエッチングすることにより開口６を形
成する。該開口６は上記ベースメタル１と後で形成され
る配線膜を接続する開口、即ち上下間接続用開口であ
り、後述する低い金属突起（１３）が形成される部分に
対応する位置と、高い金属突起（１２）が形成される部
分に対応する位置に設けられる。(C) Next, a film made of an insulating resin, for example, a polyimide film 5 is formed on the copper film 3, and the polyimide film 5 is selectively etched to form an opening 6. The opening 6 is an opening for connecting the base metal 1 and a wiring film to be formed later, that is, an opening for vertical connection, and a position corresponding to a portion where a low metal protrusion (13) described later is formed and a high position. It is provided at a position corresponding to the portion where the metal protrusion (12) is formed.
【００１４】（Ｄ）次に、上記ポリイミド膜５上に例え
ば銅からなる配線膜７を無電解メッキ及び電解メッキに
より形成する。具体的には、例えばＰｄ活性処理を施
し、その後、無電解Ｎｉ−Ｐメッキ等により薄い導電層
を全面的に形成し、その後、形成しべきパターンに対し
てネガのパターンのフォトレジスト膜を形成し、該フォ
トレジスト膜をマスクとして銅をメッキすることにより
配線膜７を形成し、その後、上記フォトレジスト膜を除
去し、しかる後、配線膜７をマスクとして、上記薄い導
電層をエッチングするという方法で配線膜７を形成す
る。図１（Ｄ）は配線膜７形成後の状態を示す。(D) Next, a wiring film 7 made of, for example, copper is formed on the polyimide film 5 by electroless plating and electrolytic plating. Specifically, for example, Pd activation treatment is performed, then a thin conductive layer is entirely formed by electroless Ni-P plating, and then a photoresist film having a negative pattern with respect to the pattern to be formed is formed. Then, the wiring film 7 is formed by plating copper using the photoresist film as a mask, then the photoresist film is removed, and then the thin conductive layer is etched using the wiring film 7 as a mask. The wiring film 7 is formed by the method. FIG. 1D shows a state after the wiring film 7 is formed.
【００１５】（Ｅ）次に、上記配線膜７上に絶縁性樹脂
からなる絶縁膜８を選択的に形成する。該絶縁膜８は後
でＬＳＩチップの電極にワイヤを接続される端子部分と
なる部分を露出させる開口９を有する。図２（Ｅ）は該
開口９を有する絶縁膜８の形成後の状態を示す。(E) Next, the insulating film 8 made of an insulating resin is selectively formed on the wiring film 7. The insulating film 8 has an opening 9 for exposing a portion which will be a terminal portion to which a wire is connected to an electrode of an LSI chip later. FIG. 2E shows a state after the insulating film 8 having the opening 9 is formed.
【００１６】（Ｆ）その後、上記配線膜７の上記開口９
を通じて露出する部分及びベースメタル１の他方（裏
側）の面の後述する高い金属突起を形成すべき部分に半
田膜１０、１１をメッキにより形成する。図２（Ｆ）は
半田膜１０、１１形成後の状態を示す。半田膜１０は配
線膜７の開口９に露出する部分に形成された半田膜、半
田膜１１のベースメタル１の裏側の面に形成された半田
膜である。(F) After that, the opening 9 of the wiring film 7 is formed.
Solder films 10 and 11 are formed by plating on the exposed portion and the portion on the other (back side) surface of the base metal 1 where a high metal protrusion to be described later is to be formed. FIG. 2F shows a state after the solder films 10 and 11 are formed. The solder film 10 is a solder film formed on a portion of the wiring film 7 exposed in the opening 9, and a solder film formed on the surface of the solder film 11 on the back side of the base metal 1.
【００１７】（Ｇ）次に、上記半田膜２、１１に対して
は侵し得ず、銅に対しては侵し得るエッチング液を用い
て上記ベースメタル１及び銅膜３に対する裏側からのエ
ッチングを行う。換言すれば、半田膜２、１１をマスク
とするベースメタル１及び銅膜３に対する選択的エッチ
ングを行う。すると、図２（Ｇ）に示すように、半田膜
１１で覆われた部分にはベースメタル１及び銅膜３から
なる金属突起１２が形成され、半田膜２で覆われた部分
には銅膜３からなる金属突起１３が形成される。金属突
起１２はベースメタル１及び銅膜３からなるので、その
高さは略ベースメタル１と銅膜３の厚さの和になり、高
くなるのに対して、金属突起１３は銅膜３からのみなる
ので、その高さは略銅膜３の厚さになり、低くなる。(G) Next, etching is performed from the back side of the base metal 1 and the copper film 3 by using an etching solution that cannot attack the solder films 2 and 11 but can attack the copper. . In other words, the base metal 1 and the copper film 3 using the solder films 2 and 11 as a mask are selectively etched. Then, as shown in FIG. 2G, a metal protrusion 12 formed of the base metal 1 and the copper film 3 is formed in the portion covered with the solder film 11, and a copper film is formed in the portion covered with the solder film 2. The metal protrusion 13 made of 3 is formed. Since the metal protrusion 12 is composed of the base metal 1 and the copper film 3, its height is approximately the sum of the thicknesses of the base metal 1 and the copper film 3 and becomes higher, whereas the metal protrusion 13 is higher than the copper film 3. Therefore, the height becomes substantially the same as the thickness of the copper film 3 and becomes lower.
【００１８】（Ｈ）その後、リフロー処理することによ
り、金属突起１２、１３を覆う半田膜２、１１を整形す
ると、図２（Ｈ）に示すような配線基板１４ができる。
該配線基板が本発明配線基板の第１の実施例である。即
ち、本配線基板１４は、開口６を有する絶縁性樹脂膜
（ポリイミド）５の一方の側（表側）には、配線膜７が
形成され、該配線膜７上には後述するＬＳＩチップの電
極と接続される端子部分を露出させる開口９のある絶縁
膜８が形成され、該開口９には半田膜１０が形成されて
いる。(H) After that, the solder films 2 and 11 covering the metal projections 12 and 13 are shaped by a reflow process, whereby a wiring board 14 as shown in FIG. 2H is formed.
The wiring board is the first embodiment of the wiring board of the present invention. That is, in the wiring board 14, a wiring film 7 is formed on one side (front side) of the insulating resin film (polyimide) 5 having the opening 6, and electrodes of an LSI chip described later are formed on the wiring film 7. An insulating film 8 having an opening 9 for exposing a terminal portion connected to is formed, and a solder film 10 is formed in the opening 9.
【００１９】また、上記絶縁性樹脂膜５の他方の側（裏
側）には、その開口６を通じて上記配線膜７と電気的に
接続された高さの異なる金属突起１２、１３が形成され
ている。そして、該金属突起１２、１３は半田２、１１
で覆われた状態になっている。低い金属突起１３はＬＳ
Ｉチップのフリップチップボンディング用として用いる
ことができ、高い金属突起１２は配線基板１４の外部端
子として用いることができる。Further, on the other side (back side) of the insulating resin film 5, metal protrusions 12 and 13 having different heights electrically connected to the wiring film 7 through the opening 6 are formed. . The metal protrusions 12 and 13 are connected to the solder 2 and 11
Is covered with. Low metal protrusion 13 is LS
It can be used for flip chip bonding of an I chip, and the high metal protrusion 12 can be used as an external terminal of the wiring board 14.
【００２０】図３（Ａ）〜（Ｄ）は図２（Ｈ）に示した
配線基板１４へのＬＳＩチップ１５、１６の搭載方法を
工程順に示す断面図である。
（Ａ）配線基板１４の裏側にＬＳＩチップ１５を低い金
属突起１３にてフリップチップボンディングすることに
より搭載する。図３（Ａ）はＬＳＩチップ１５のフリッ
プチップボンディング後の状態を示す。3A to 3D are sectional views showing a method of mounting the LSI chips 15 and 16 on the wiring board 14 shown in FIG. 2H in the order of steps. (A) The LSI chip 15 is mounted on the back side of the wiring board 14 by flip-chip bonding with the low metal protrusions 13. FIG. 3A shows a state of the LSI chip 15 after flip chip bonding.
【００２１】（Ｂ）次に、図３（Ｂ）に示すように、上
記配線基板１４・ＬＳＩチップ１５間を樹脂１７で封止
する。
（Ｃ）その後、配線基板１４の表側にＬＳＩチップ１６
をボンディングし、該ＬＳＩチップ１６の各電極と、配
線膜７の端子の半田膜１０との間をワイヤ１８により接
続する。図３（Ｃ）はワイヤボンディング後の状態を示
す。
（Ｄ）しかる後、図３（Ｄ）に示すようにＬＳＩチップ
１６を樹脂１９で封止する。(B) Next, as shown in FIG. 3B, the space between the wiring board 14 and the LSI chip 15 is sealed with a resin 17. (C) After that, the LSI chip 16 is provided on the front side of the wiring board 14.
Are bonded, and each electrode of the LSI chip 16 and the solder film 10 of the terminal of the wiring film 7 are connected by a wire 18. FIG. 3C shows a state after wire bonding. (D) After that, the LSI chip 16 is sealed with resin 19 as shown in FIG.
【００２２】本配線基板１４によれば、上下間導通用開
口６を有する絶縁性樹脂膜（ポリイミド膜）５の表側に
配線膜７が形成され、該絶縁性樹脂膜５の裏側に上記開
口６を通じて上記配線膜７に接続された互いに二通りの
異なる高さの金属突起１２、１３が形成されているの
で、絶縁性樹脂膜５の表側と裏側の両方にＬＳＩチップ
１５、１６を搭載でき、配線基板１４の実装密度を高め
ることができる。According to the present wiring board 14, the wiring film 7 is formed on the front side of the insulating resin film (polyimide film) 5 having the opening 6 for vertical conduction, and the opening 6 is formed on the back side of the insulating resin film 5. Since the metal protrusions 12 and 13 of two different heights connected to the wiring film 7 are formed through, the LSI chips 15 and 16 can be mounted on both the front side and the back side of the insulating resin film 5, The mounting density of the wiring board 14 can be increased.
【００２３】尚、図２（Ｈ）に示した配線基板１４は、
上記絶縁性樹脂膜５の表側の配線が一層配線であるが、
この配線は２層配線或いはそれ以上の多層配線であって
も良い。また、上記配線基板１４の製造方法において
は、図２（Ｇ）に示したエッチング工程の終了後、図２
（Ｈ）で示す半田膜２、１１をリフロー処理する工程に
より金属突起１２、１３が半田で覆われた形状に整形さ
れるようにするが、必ずしもそのようにすることは不可
欠ではなく、エッチング工程の終了後、半田膜１０、１
２、１３を剥離により除去するようにしても良い。図４
（Ａ）はそのような半田膜１０、１２、１３を剥離した
場合の配線基板の例１４ａを示す断面図、（Ｂ）はその
配線基板１４ａに一つのＬＳＩチップ１６の搭載例を示
す断面図である。The wiring board 14 shown in FIG.
The wiring on the front side of the insulating resin film 5 is a single layer wiring,
This wiring may be a two-layer wiring or a multilayer wiring of more than two layers. In addition, in the method of manufacturing the wiring board 14, after the etching step shown in FIG.
Although the metal projections 12 and 13 are shaped into the shape covered with the solder by the step of reflowing the solder films 2 and 11 shown in (H), it is not essential to do so, and the etching step After the end of the solder film 10,1
You may make it remove 2 and 13 by peeling. Figure 4
(A) is a sectional view showing an example 14a of a wiring board when such solder films 10, 12, 13 are peeled off, and (B) is a sectional view showing an example of mounting one LSI chip 16 on the wiring board 14a. Is.
【００２４】図５は配線基板１４、２４を二つ積層した
使用例を示す断面図であり、このような態様でも配線基
板を使用できる。配線基板１４は図２（Ｈ）に示したも
のと同じであるが、配線基板２４は配線基板１４の半田
膜１０に代えて半田バンプ２０を形成したもので、配線
基板１４、２４の裏面側にはそれぞれ低い金属突起１３
にてＬＳＩチップ１５、１５が搭載されているが、配線
基板１４の表側にはＬＳＩチップ１８が搭載されている
けれども配線基板２４の表側にはＬＳＩチップ１８を設
けず、半田バンプ２０をプリント配線基板２１の配線膜
２２との接続端子として用いる。そして、配線基板１４
と２４の高い金属突起１２・１２同士を例えば半田２３
等により接続してなる。これにより配線基板を複数積層
してより実装密度の向上を図ることができる。FIG. 5 is a sectional view showing an example of use in which two wiring boards 14 and 24 are laminated, and the wiring board can be used even in such a mode. The wiring board 14 is the same as that shown in FIG. 2H, but the wiring board 24 is formed by forming the solder bumps 20 in place of the solder film 10 of the wiring board 14, and the back side of the wiring boards 14 and 24. Each has a low metal protrusion 13
Although the LSI chips 15 and 15 are mounted on the wiring board 14, the LSI chip 18 is mounted on the front side of the wiring board 14, but the LSI chip 18 is not provided on the front side of the wiring board 24, and the solder bumps 20 are printed on the wiring. It is used as a connection terminal with the wiring film 22 of the substrate 21. Then, the wiring board 14
And the high metal projections 12 and 24 of the
Etc. are connected. As a result, a plurality of wiring boards can be stacked to further improve the packaging density.
【００２５】[0025]
【発明の効果】本発明配線基板によれば、上下間導通用
開口を有する絶縁性樹脂膜の表側に一層又は多層の配線
膜が形成され、該絶縁性樹脂膜の裏側に上記開口を通じ
て上記配線膜に接続された互いに二通りの異なる高さの
金属突起が形成されているので、絶縁性樹脂膜の表側と
裏側の低い金属突起のある部分の両方にＬＳＩチップを
搭載でき、配線基板の実装密度を高めることができる。According to the wiring board of the present invention, a single-layer or multilayer wiring film is formed on the front side of the insulating resin film having the opening for vertical conduction, and the wiring is formed through the opening on the back side of the insulating resin film. Two different heights of metal protrusions connected to the film are formed, so LSI chips can be mounted on both the front side and backside of the insulating resin film that have low metal protrusions. The density can be increased.
【００２６】本発明配線基板の製造方法によれば、ベー
スメタルの一方の主面に第１の半田膜を選択的に形成
し、その主面上に上記半田膜上も含め金属膜を形成し、
該金属膜上に絶縁膜を介して配線膜を形成し、上記ベー
スメタルの他方の主面上に第２の半田膜を形成し、その
後、上記第２の半田膜をマスクとして上記ベースメタル
をエッチングすると共に、上記第２の半田膜及び上記第
１の半田膜をマスクとして上記金属膜をエッチングして
第２の半田膜とベースメタルからなる高い金属突起と、
第１の半田膜と上記金属膜からなる低い金属突起を形成
するので、上記本発明配線基板を得ることができる。ま
た、金属突起の形成後、マスクとして用いた半田膜に対
するリフロー処理を施すことにより、その半田で金属突
起を覆い、その半田を半田バンプとして利用できる。According to the method for manufacturing a wiring board of the present invention, the first solder film is selectively formed on one main surface of the base metal, and the metal film including the solder film is formed on the main surface. ,
A wiring film is formed on the metal film via an insulating film, a second solder film is formed on the other main surface of the base metal, and then the base metal is used as a mask with the second solder film. A high metal protrusion formed of the second solder film and the base metal by etching and etching the metal film using the second solder film and the first solder film as a mask;
Since the low metal protrusion composed of the first solder film and the metal film is formed, the wiring board of the present invention can be obtained. Further, after forming the metal protrusions, the solder film used as the mask is subjected to a reflow process, so that the metal protrusions are covered with the solder, and the solder can be used as solder bumps.
【図面の簡単な説明】[Brief description of drawings]
【図１】（Ａ）〜（Ｄ）は本発明配線基板の製造方法の
一つの実施例の前半を工程順に示す断面図である。1A to 1D are cross-sectional views showing the first half of one embodiment of a method for manufacturing a wiring board of the present invention in the order of steps.
【図２】（Ｅ）〜（Ｈ）は上記実施例の後半を工程順に
示す断面図である。2 (E) to (H) are cross-sectional views showing the latter half of the above embodiment in the order of steps.
【図３】（Ａ）〜（Ｄ）は本発明配線基板への二つのＬ
ＳＩチップの搭載方法を工程順に示す断面図である。3 (A) to (D) are two L's for the wiring board of the present invention.
It is sectional drawing which shows the mounting method of SI chip in order of a process.
【図４】（Ａ）はエッチング工程の終了後、マスクとし
て用いた半田膜を剥離により除去するようにした配線基
板の一例を示す断面図、（Ｂ）はその配線基板へＬＳＩ
チップを一つ搭載した状態を示す断面図である。FIG. 4A is a cross-sectional view showing an example of a wiring board in which a solder film used as a mask is removed by peeling after the etching process is completed, and FIG.
It is sectional drawing which shows the state which mounts one chip.
【図５】複数の配線基板を組み付けた配線基板の使用例
を示す断面図である。FIG. 5 is a cross-sectional view showing an example of use of a wiring board assembled with a plurality of wiring boards.
１・・・ベースメタル、２・・・半田膜、３・・金属
膜、５・・・絶縁性樹脂膜、６・・・開口、７・・・配
線膜、１０、１１・・・半田膜、１２・・・高い金属突
起、１３・・・低い金属突起、１４、１４ａ、２４・・
・配線基板、１５、１６・・・ＬＳＩチップ。1 ... Base metal, 2 ... Solder film, 3 ... Metal film, 5 ... Insulating resin film, 6 ... Opening, 7 ... Wiring film, 10, 11 ... Solder film , 12 ... high metal projections, 13 ... low metal projections, 14, 14a, 24 ...
-Wiring board, 15, 16 ... LSI chip.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平11−186443（ＪＰ，Ａ) 特開 平10−284544（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 23/50 H01L 23/52 H01L 25/00 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-11-186443 (JP, A) JP-A-10-284544 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12 H01L 23/50 H01L 23/52 H01L 25/00
Claims (4)
の側に一層或いは多層の配線膜が形成され、 上記樹脂膜の他方の側に上記開口を通じて上記配線膜に
接続された銅或いは銅合金からなる金属突起と該金属突
起より高さの低い銅からなる金属突起とが形成され、 高さの低い金属突起がフリップチップボンディング用突
起とされ、 上記高さの高い金属突起が外部端子とされたことを特徴
とする配線基板。1. A one-layer or multi-layer wiring film is formed on one side of a resin film having an opening for vertical conduction, and copper or copper connected to the wiring film through the opening on the other side of the resin film. metal protrusion and the metal collision of an alloy
A metal projection made of copper having a height lower than the initial height is formed, the metal projection having a low height is used as a flip chip bonding projection, and the metal projection having a high height is used as an external terminal. substrate.
一層或いは多層の配線膜が形成された側にＬＳＩチップ
が設置されたことを特徴とする請求項１記載の配線基板2. The wiring board according to claim 1, wherein the LSI chip is installed on the side of the resin film having the opening for vertical connection formed with one or more wiring films.
膜を選択的に形成する工程と、 上記ベースメタルの上記主面上に上記半田膜上も含め金
属膜を形成する工程と、 上記金属膜上に、後で形成される金属突起と対応する位
置に上下間導通用開口のある絶縁膜を形成する工程と、 上記絶縁膜上に一層又は多層の配線膜を形成する工程
と、 上記べースメタルの他方の主面の高い金属突起を形成す
べき位置に第２の半田膜を形成する工程と、 その後、上記第２の半田膜をマスクとして上記べースメ
タルを上記他方の主面側からエッチングすると共に、上
記第２の半田膜及び上記第１の半田膜をマスクとして上
記金属膜をエッチングして上記金属膜と上記べ一スメタ
ルからなる高い金属突起と、上記金属膜からなる上記低
い金属突起を形成する工程と、 を有することを特徴とする配線基板の製造方法。 3. A step of selectively forming a first solder film on one main surface of a base metal, and a step of forming a metal film on the main surface of the base metal including the solder film. A step of forming an insulating film having a vertical conduction opening at a position corresponding to a metal projection to be formed later on the metal film, and a step of forming a single-layer or multilayer wiring film on the insulating film; A step of forming a second solder film at a position where a high metal protrusion on the other main surface of the base metal is to be formed, and thereafter, using the second solder film as a mask, the base metal is on the other main surface side And the metal film is etched by using the second solder film and the first solder film as a mask and the metal film and the base metal are high metal protrusions and the metal film is low. Process for forming metal protrusions When manufacturing step of a wiring board and having a.
ルを他方の主表面側からエッチングすると共に、上記第
２の半田膜及び第１の半田膜をマスクとして金属膜をエ
ッチングして該金属膜と上記ベースメタルからなる高い
金属突起と、該金属膜からなる上記低い金属突起を形成
する工程の後に、上記第１及び第２の半田膜に対するリ
フローにより上記高い金属突起表及び低い金属突起を該
半田膜の半田で覆った状態にする工程を有することを特
徴とする請求項２の配線基板の製造方法。 4. A base metal is etched from the other main surface side by using the second solder film as a mask, and a metal film is etched by using the second solder film and the first solder film as masks. After the step of forming the high metal protrusion made of the base metal and the low metal protrusion made of the metal film, the high metal protrusion surface and the low metal protrusion are removed by reflowing the first and second solder films. The method of manufacturing a wiring board according to claim 2, further comprising a step of covering the solder film with solder.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22914099A JP3497774B2 (en) | 1999-08-13 | 1999-08-13 | Wiring board and its manufacturing method |
| US09/466,895 US6782610B1 (en) | 1999-05-21 | 1999-12-20 | Method for fabricating a wiring substrate by electroplating a wiring film on a metal base |
| KR1020000021688A KR100553405B1 (en) | 1999-05-21 | 2000-04-24 | Wiring substrate for mounting semiconductor elements and fabricating method thereof |
| TW089107741A TW508705B (en) | 1999-05-21 | 2000-04-25 | Wiring substrate and fabricating method thereof |
| KR1020050003199A KR100562601B1 (en) | 1999-05-21 | 2005-01-13 | Wiring substrate for mounting semiconductor elements and fabricating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22914099A JP3497774B2 (en) | 1999-08-13 | 1999-08-13 | Wiring board and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001053189A JP2001053189A (en) | 2001-02-23 |
| JP3497774B2 true JP3497774B2 (en) | 2004-02-16 |
Family
ID=16887401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22914099A Expired - Fee Related JP3497774B2 (en) | 1999-05-21 | 1999-08-13 | Wiring board and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3497774B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW522530B (en) * | 1999-08-02 | 2003-03-01 | Toyo Kohan Co Ltd | Semiconductor package unit |
| JP2004273785A (en) * | 2003-03-10 | 2004-09-30 | Advanced Systems Japan Inc | Connection terminal and manufacturing method therefor |
-
1999
- 1999-08-13 JP JP22914099A patent/JP3497774B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001053189A (en) | 2001-02-23 |
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