TW522530B - Semiconductor package unit - Google Patents

Semiconductor package unit Download PDF

Info

Publication number
TW522530B
TW522530B TW89115381A TW89115381A TW522530B TW 522530 B TW522530 B TW 522530B TW 89115381 A TW89115381 A TW 89115381A TW 89115381 A TW89115381 A TW 89115381A TW 522530 B TW522530 B TW 522530B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor package
nickel
copper
etching
Prior art date
Application number
TW89115381A
Other languages
Chinese (zh)
Inventor
Saijo Kinji
Yoshida Kazuo
Okamoto Hiroaki
Osawa Shinji
Original Assignee
Toyo Kohan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Kohan Co Ltd filed Critical Toyo Kohan Co Ltd
Application granted granted Critical
Publication of TW522530B publication Critical patent/TW522530B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

Disclosed is to provide semiconductor package unit having at least duplicate capacity. By using one or at least two solution selected from the group of ferric chloride, cupric chloride, sulfuric acid + hydrogen peroxide as wet etchant liquid, and selectively etching the two faces of clad sheet 34, to form substrate having inner lead layer, forming insulation layer and outer lead layer onto the said substrate, to undergo the fabrication of circuit pattern on the outer lead layer. Furthermore by etching the columnar lead formed in the inner lead layer and outer lead layer in the said substrate, to electrically connect with the semiconductor chip 1, 2 onto the two faces of the clad sheet, to form integrally constructed semiconductor package unit.

Description

522530 五、發明說明(1) 的技彳 本發明係有關可對應於半導體之 封裝体單位。又+义 、 蒌積體化的半導靜 ^ 务明尤指有關於習用的半導體壯 " 同的空間容積内可載罾 體封裝体相 m 片之新穎的半導體封裝体單位。 心今里之+導體 刑近年,^著半導體裝置之高度積體化、多接胎 型化、又電子機器之小型、蘇旦 古6夕接腳化、小 被要求著,為使該高宓 :^ 问始、度的裝配基板乃 軛$夕s 山又的凌配基板成為可能,盥佈飧其 板之夕層A、與佈線密度之提高,:佈線基 研究、開發正蓬勃進展著。 θ 口構k有關的 此種多層化方法,雖隨著 少的變化,麩而習用古y< 夂遷有或多或 夂丨U ”、、向白用方法係大致於一個封麥伙肉p ,人 個晶片者,只要不擗4曰u 丨口 2了衣体内已組合一 _ ^ 不曰加日日片容量下每個封裝体之交旦又处 增加的問題即被指責著。 不之谷里不月b 至於改善此種狀態之方法,例如在日本特開平 袓m: Λ 不者介由多數個接合部半導体模 組間進仃電氣連接,以電氧拿桩 ^ ^ 之接人邱門媸屮目士礼連接I予έ又於各半導體模數間 道Μ二邛1,構成具有指定的功能之多數個電極,以各半 至”體晶片所具有的接端接合部為止的ii 二ίΓ極之任一者作為各半導體晶片之固 ^電極予以構成,又於半導體晶 合部之晶墊(pad),以各半導㈣“、上蛋孔連接接 千V體換組使由半導體晶片所具 第5頁 91047-TYJP-1574TW.ptd 522530 五、發明說明(2) ^^ 有的接姓 接合部間之圖案”,再以半導體模組使 各半導體θ曰片夕=f同下,以夕數個電極之任一者作為 且曰日片之固有電極予以構成者。 及第二;膜=?Γ則使於第一薄膜載体半導體模組 氣連接片選擇用佈線圖形之間隔件,藉由電 配及裝ί空導體I组,於與習用封裝体同樣的裝 可層==體模組約略相等厚度時,因介由間隔: 封裳体之晶片容量ΐίϊ体丰導體模組…再使每-個 有薄膜載:二223”3,公報之提案,係藉由使 輪出入而士 Μ 線(nner lead)之面與有半導體晶片之 過的程产目门配0 ,且減少裝置空洞至使半導體晶片不通 之结=21 *可使層間隔狹窄至使半導體晶片及薄膜載体 容旦合ΐ ΐ接觸為止,故空間容積會減少而使封裝体内的 奋里會貫質上增加者〇 發明欲解決的問題 , 然而/在依日本特開平1 0- 1 63 4 1 4號公報之提案方 1 &個半‘體曰曰片係藉由1個隆起物(bumP)及與該隆起物 ^接的内導線部可電氣連接,故在限於採用此形式之構造 面未此填埋各晶片間存在的空間,因此愈增加層合個 ΐ則愈增加,Λ空間容積亦增大著,故形成未能充分活用 由此層合引起的效果。522530 V. Technology of Invention Description (1) The present invention relates to a package unit that can correspond to a semiconductor. In addition, the semiconducting statics of integrated and integrated semiconductors ^ Wu Ming especially refers to the novel semiconductor package unit that can hold m packages of the body package in the same space volume. In recent years, the + conductor sentence in the heart has been highly integrated with semiconductor devices, multi-connected tires, and small electronic devices, and the requirements of the Soviet Union are small and small. In order to make this high: ^ It is possible that the assembly substrates of the beginning and the end are yoke and slab substrates. It is possible to increase the density of the wiring layer A and the wiring board: the research and development of the wiring base is progressing vigorously. Although this kind of multi-layered method related to the θ mouth structure k, with little change, the ancient y < has more or less U U U '', the method used to the white is roughly a seal wheat p If you are a chip person, as long as you do n’t miss 4 u u 丨 mouth 2 has already been combined in the body ^ ^ No, plus the increase in the daily capacity of each package and the increase in the volume of each package will be blamed. As for the method to improve such a state, for example, in Japanese Unexamined Patent Application No. Hirakai: m: Λ, the electrical connection is made between the semiconductor modules of a plurality of junctions, and the oxygen is used to pick up the pile ^ ^ The door-to-door ceremony is connected between each semiconductor module and the channel M2 to form a plurality of electrodes having a specified function, and each half is up to the terminal junction portion of the body wafer. Any one of the two Γ poles is configured as a solid electrode of each semiconductor wafer, and is connected to the thousands of V-shaped bodies on the crystal pad of the semiconductor crystal junction (pad) with a semi-conductor, and an egg hole. Page 5 of the semiconductor wafer 91047-TYJP-1574TW.ptd 522530 V. Description of the invention (2) ^^ Some joints The inter-pattern ", and then the semiconductor module to each said semiconductor substrate θ = f at the same evening, evening to be constituted by a plurality of electrodes according to any one of said electrodes, and as a natural substrate of the date. And second; film =? Γ is used to select the wiring pattern spacer for the first thin-film carrier semiconductor module gas connection sheet. It can be installed in the same package as the conventional package by electrical distribution and installation of the empty conductor I group. When the layer == the body module is approximately equal in thickness, it is caused by the interval: the chip capacity of the package body ΐ the body conductor module ... and then each one has a thin film load: two 223 "3, the proposal of the bulletin, by Make the wheel in and out, and the side of the N lead and the gate of the process with the semiconductor wafer match 0, and reduce the device cavity to the junction that makes the semiconductor wafer inaccessible = 21 * It can narrow the layer interval to make the semiconductor wafer And the thin film carrier Rongdan until the contact, so the space volume will be reduced and the quality in the package will increase qualitatively. 0 The problem to be solved by the invention, however, according to Japanese Patent Laid-Open No. 1 0- 1 63 4 1 Proposer 1 of the 4th bulletin & a half-body sheet is electrically connected by a bump (bumP) and the inner lead part connected to the bump, so it is limited to adopt this type of structural surface The space between the wafers is not filled, so the rule of lamination is increased. Increases, the volume also increases significantly Lambda space, so that the effect could not be fully utilized thereby forming a laminated caused.

522530 五、發明說明(3) 軟J二:i特開平1 "23683號公報提案方 '去田 穿孔間之層間接合,故有此部份之二 ‘司亚不足夠的問題存在。 切之活用空 本發明係藉由儘可能的減少在層人 生成之存在☆晶片㈤之空間容·,可;是的晶片時 :::藉由採用此方法,成為可將半導“裝;本:來=問 合里设成習用方式之至少二倍。 、本内之晶片 凝課題而採的手與 本發明之半 用之包層板,於 設置於前述包層 徵。再者,藉由 多數個半導體晶 形成本發明 箔及鎳箔之包層 (Cu) fg、鎳(Ni) 層板為宜。 且此包層板 刻層之鎳箔材或 製作者,在製作 或鍍鎳層之接合 及前述鎳箔或鍍 以形成。 導體封 包層板 板之上 層合本 片成為 之單位 板,具 箔之組 係將形 錢鎳層 後於真 面予以 鎳層並 裝体,係以濕式法蝕刻封裝体單位 表面上形成電路’連接該電路及已 下的半導體晶片使成整體化為特 單位於印刷基板等上,可製造出使 整體化的單位。 而用的包層板,宜為由多數組合銅 體而言此包層板之材質係以使用鋼 合’例如(:11/“/(:11/^:1/(:11而成的包 成導體層等的銅箔材及形成停止餘 合体同時以〇 · 1〜3 %輾軋率壓焊予以 空槽内事先對前述銅箔及前述鎳箱 活性化處理後,藉由層合前述鋼= 以0 · 1〜3 %之輕軋率進行冷壓焊而予 第7頁 91047-TYJP-157 恨 ptd 522530 五、發明說明(4) 該時,前述活性化處理宜為使用藉由(丨)於 1乂10-1〜1\101〇1^之極低壓惰性氣圍中,(2)以具 之前述銅箔及前述鎳層作為各自已接地的一側之 σ, 於經予絕緣支持的其他電極Β之間施加卜5〇ΜΗζ之交流’ 進行輝光.放電’(3)且使曝露於由前述輝光放電生的 聚中之電極,其面積在電極Β之面積之1/3以下1 = ^ 濺鍍蝕刻處理予以進行者。 V〜猎由 使用由組合氯化鐵、氯化銅、或硫酸 種或二種以上而成的水溶液作為濕式蝕 登^之一 刻處理包層板之表面並於此包# / 込擇性的蝕 成佈線層。 此包層板上形成柱狀導體,再形 =由塗布絕緣樹脂餘包層板 大包層板之強度。層合封裝体 I刀之上,可增 封裝体之情形,在強度上2 個:亡並使用作多層 發明之封裝体單位之外周並 乳樹脂等覆蓋本 丄j形成完全密閉封裝体。 發明之實施形啤 以下’茶閱附圖所示的 明。 的只轭形態,具體的說明本發 首先,就與本發明之一實〜 單位之構造,參閱第1〇圖及第= =半導體封裳体 如圖不般,於由銅箔所形 //m為宜)而成的銅箔層19之兩々佈線圖(以厚度10〜1〇〇 鍍鎳層(以厚度〇. 5〜3 \ ,上,使成為停止蝕刻層之 為且)或鎳荡層(以厚度5〜1〇// 522530 五、發明說明(5) m)2 0、21接合,形成基座之芯。 其次’於成為佈線層之銅箔層丨9 3 體晶片1之連接用隆起物18(以厚;;二:形上者與半導 佈線芦夕如反丨甘_ι ΙΟΟ#111為且),又於 於連^爾ϋ 形成絕緣樹脂而成的裝配基板41, 物17=厚度1〇〜⑽心為宜)之下部連接有 糾。侧的曰曰片2,再者於印刷基板之下部形成著軟谭隆起 方法其次採用第23圖說明上述的半導體封裝体單位之製造 首先說明三層包層板之形成。 體声製造半導體封裝体單位之際,於成為内部導 停止㈣層2。、21/i度;為宜)之兩面 銅笮之Λ而卜# v $山又· # m之鍍鎳層。此鍍鎳係於 5Π泊之兩面上施以通常所用的鍍鎳。 又’於使用鎳箔取代鍍鉾屛主 的包層板製造裝置,首先將厚二月’’採用第23圖所示 箔之显ft卜ϋ π 將厚度5〜10 鎳箔壓著於銅 冶之早面上。再者將鎳箱壓著於反對 箔/Ni箔之三層包層板。 上氷成N!泊/Cu 且,為說明之方#,太LV 丁 > μ 形予以說明。 在乂下的§己載謹就鍍鎳銅箱之情 其次,將兩面上已施加鍍鎳的^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 一 層包層板)22捲繞於第23圖所示的 =/Cu/Nl之, 的回繞捲軸23上。又將成為柱肤m日衣坆名置之一側 另-側的回繞轉軸為心導體Π之銅羯材24捲繞於 第9頁 91047-TOP-1574TW.ptd 522530522530 V. Description of the invention (3) Soft J2: Proposal No. 23683 of “i Kaikai No. 1” “Go to the field for interlayer bonding between perforations, so there is the second part of this part,‘ Siya is not enough. The present invention is to make use of the present invention by reducing as much as possible the existence of human beings in the layer. ☆ The space capacity of the chip is ok, but when it is a chip :: By using this method, the semiconductor can be "installed; Ben: Lai = Wenli is set to be at least twice the customary method. The hand used in the book to condense the subject and the semi-used cladding board of the present invention are set in the aforementioned cladding sign. Furthermore, borrow The cladding (Cu) fg and nickel (Ni) laminates of the foil and nickel foil of the present invention are preferably formed from a plurality of semiconductor crystals, and the nickel foil material or producer of the cladding engraving layer is producing or plating a nickel layer. The joint and the aforementioned nickel foil or plating are used to form the unit board which is laminated on the conductor enveloping board. The group with a foil is a nickel layer formed on the real surface and the body is packed with wet nickel. A method of forming a circuit on the surface of the package body by the method of etching is used to connect the circuit and the semiconductor wafer that has been lowered and integrated into a special unit on a printed circuit board or the like, so that an integrated unit can be manufactured. For most composite copper bodies, the material of this clad board is steel. 'For example, (: 11 / "/ (: 11 / ^: 1 / (: 11), a copper foil material such as a clad conductor layer, and a stop-over body are formed by pressure welding at a rolling rate of 0.1 to 3%. After the activation of the copper foil and the nickel box in the empty tank in advance, cold lamination was performed by laminating the steel = cold rolling at a light rolling rate of 0. 1 to 3%. Page 7 91047-TYJP-157 ptd 522530 V. Description of the invention (4) At this time, the aforementioned activation treatment should be used in the extremely low-pressure inert gas range of (1) 10-1 ~ 1 \ 101〇1 ^, (2) with The aforementioned copper foil and the aforementioned nickel layer are σ on each side which has been grounded, and an alternating current of 50 MHz is applied between the other electrodes B which are pre-insulated, to perform a glow. Discharge '(3) and expose to The area of the electrode in the polymer generated by the above-mentioned glow discharge is less than 1/3 of the area of the electrode B. 1 = ^ Sputtering etching process is performed. V ~ hunting by using a combination of ferric chloride, copper chloride, or sulfuric acid One or two or more kinds of aqueous solutions are used as a wet etching method to etch the surface of the clad board and selectively etch the wiring layer in this bag. Form a columnar conductor on the board, reshape = the strength of the large cladding board coated with insulating resin and the remaining cladding board. The laminated package I can increase the strength of the package when it is 2 knives: die and use The outer layer of the package unit of the multi-layer invention is covered with milk resin and the like to form a completely sealed package. Implementation of the invention The shape of the beer is as shown in the following figure. The specific description of the yoke is as follows. As for the structure of the unit with one of the present invention, please refer to FIG. 10 and FIG. == the semiconductor package is not as shown in the figure, and is formed by a copper foil layer 19 /). The two wiring diagrams (with a thickness of 10 ~ 100), a nickel plating layer (with a thickness of 0.5 ~ 3 \, above, so as to stop the etching layer) or a nickel layer (with a thickness of 5 ~ 10 // 522530 V. Description of the invention (5) m) 2 0, 21 are joined to form the core of the base. Secondly, the copper foil layer that becomes the wiring layer 丨 9 3 The bump 18 for the connection of the body wafer 1 (thickness ;; 2: the shape above and the semiconducting wiring are like 丨 gan_ι ΙΟΟ # 111 is and) In addition, a mounting substrate 41 made of insulating resin is formed in Yulian, where the thickness of the substrate 17 is equal to the thickness of 10 and the center is preferably connected). The second sheet is on the side, and a soft tan ridge is formed on the lower part of the printed circuit board. Next, FIG. 23 is used to explain the manufacturing of the above-mentioned semiconductor package unit. First, the formation of a three-layer clad board is described. When manufacturing a semiconductor package unit for bulk acoustics, it becomes an internal conduction stop layer 2. , 21 / i 度; It is advisable) on both sides of copper 笮 of Λ and Bu # v $ 山 又 · # m of nickel plating. This nickel plating is performed on both sides of 5 Π Po with nickel plating commonly used. Also, in the clad board manufacturing device that uses nickel foil instead of the main metal plating, first the thickness of February is used. The thickness of the foil shown in Figure 23 is used to press the nickel foil to a thickness of 5 to 10 mm. Early on. Furthermore, the nickel box was pressed against a three-layer clad plate of an opposing foil / Ni foil. Put ice into N! Po / Cu and, for explanation, # LV D > μ shape will be explained. In the § His Majesty, I would like to take the case of nickel-plated copper boxes next, and ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ a layer of clad sheet 22 on which nickel has been applied on both sides. The indicated = / Cu / Nl is on the reel 23. The copper-backed material 24, which has become the name of the column skin m-day clothing, is wound on the other side, and the coil 24 is a core conductor. The coil is wound on page 9 91047-TOP-1574TW.ptd 522530

由二回繞捲軸23上同時回繞鍍鎳銅箔材22及銅箔 24,將其一部份捲繞於已突出於蝕刻室26内之滾動電極 27、28上,在刻蝕室26内經濺鍍處理予以活性化。其 用輥軋輥輪29、30使鍍鎳銅箔材22及銅箔材24壓著,將勺 層板31捲取於捲取輥輪32上。利用壓著接合使形成、已 Cu/Ni/Cu/Ni之四層包層,板。 此時,活性化處理係如本申請人先前於曰本特開平 1 2 24 1 84號公報所揭示,係(1)於} χ ^ 〜1 χ 之極 ,壓惰性氣圍中,(2)以具有接合面之鍍鎳銅箔材2 2及銅 vl材2 4作為各自已接地的一側之電極A,於經予絕緣支持 的其他電極B之間施加1〜5〇MHz之交流電並使進行輝光放 電’(3)且使曝露於由前述輝光放電生成的電漿中之電 極,其面積在電極B之面積之1/3以下,(4)藉由濺鍍蝕刻 處理予以進行。 其次’將此具有四層構造之包層板再度捲繞於回繞捲 軸23之上。又將成為連接用隆起物18之銅箔材33(參閱第夏 圖)捲繞於回繞捲軸25上。由二回繞捲軸23、25各自回繞 四層包層板及銅箔材,將其一部份捲繞於已突出於蝕刻室 522530 五、發明說明(7) 放電乂3)/Λ=於由前述輝光放電生成的電漿甲之電 積之1/3以下,⑷藉由…刻 處理予以進灯。 利乳輥輪29、30,使包層板22之錄面及銅落 材24磨者,捲取於捲取輥輪32 ::Nickel-plated copper foil 22 and copper foil 24 are simultaneously wound on the two winding rolls 23, and a part of them is wound on rolling electrodes 27 and 28 protruding in the etching chamber 26, and in the etching chamber 26 Activated by sputtering. It presses the nickel-plated copper foil material 22 and the copper foil material 24 with rolling rollers 29 and 30, and winds the scoop plate 31 onto the winding roller 32. A four-layer cladding layer of Cu / Ni / Cu / Ni was formed by pressure bonding, and the plate was formed. At this time, the activation treatment is as disclosed by the present applicant in Japanese Patent Application Laid-Open No. 1 2 24 1 84, which is (1) at the pole of} χ ^ ~ 1 χ, in an inert gas atmosphere, (2) Using nickel-plated copper foil 22 and copper vl material 24 with joint surfaces as the electrodes A on the grounded side, an alternating current of 1 to 50 MHz was applied between the other electrodes B supported by insulation and Glow discharge '(3) is performed, and the electrode exposed to the plasma generated by the aforementioned glow discharge has an area less than 1/3 of the area of electrode B, and (4) is performed by sputtering etching. Secondly, this clad plate having a four-layer structure is wound on the rewinding shaft 23 again. The copper foil 33 (see Fig. 1) which becomes the connection bump 18 is wound on the winding reel 25. Four winding cladding plates and copper foil are respectively wound by two winding reels 23 and 25, and a part of them is wound around the protrusion chamber 522530. V. Description of the invention (7) Discharge 乂 3) / Λ = 于Less than 1/3 of the electrical product of the plasma armor generated by the aforementioned glow discharge, the lamp is put into the lamp through a engraving process. Breast rollers 29 and 30, so that the recording surface of the cladding plate 22 and the copper falling material 24 are ground by the take-up roller 32 ::

Cn/Ni/ Cu/Ni/Cu之五層包層板。 i者接。使φ成 利用上述操作,如第1圖所示般,且 層板34可予製造出。 八有層構仏之包 如此,藉由使用第23圖之包声軛迤、生驻罢*去… 塵焊,以銅/錄/銅/鎳/銅之順序:= 層,中間層内介由錄層之多層包層板^出銅層以表背 再者’設置三台以上的μ、+、 設置銅賴鎳菌材等,藉由= 供給Ϊί材將的麗烊可製造出多層構:之心: /、 將匕層板3 4裁切成戶斤爱日佐从丄 圖〜第11圖’經過下述的步驟1、導体y ’參閱第2 首先,如第2圖V 之第一實施形態而用者。 膜35後,進行曝光"、顯^。於銅泊材24之表面上形成光阻 狀導体18殘存著^容不解進订銅箱材24之選擇#刻,將柱 五兀岭解、去除銅箔材24。 至於此日守之蝕刻液,以使用石亡 過硫酸銨水溶液為宜。 ’丨L咬+過乳化虱水溶液或 且’蝕刻處理係浸潰被處理体於蝕刻水溶液中予以進 91047-TYJP.1574TW.ptd 第11頁 522530Cn / Ni / Cu / Ni / Cu five-layer clad board. i 者 接。 Using the above operation, as shown in Fig. 1, the laminate 34 can be manufactured. The package of the eight-layer structure is like this. By using the sound yoke package and resident in Figure 23 to go ... Dust welding, in the order of copper / recording / copper / nickel / copper: = layer, interlayer intermediary Multi-layer clad board with recording layer ^ Copper layer is used as the front and back, and more than three μ, +, copper and nickel fungi are set, and multi-layer structure can be manufactured by = supply : 心 : / 、 Cut the dagger layer board 3 4 into the household weight Ai Rizuo from the figure to the 11th figure 'After the following steps 1, the conductor y' Refer to the second first, as shown in the second of the second figure V For one embodiment. After the film 35, exposure is performed. A photoresist-like conductor 18 is formed on the surface of the copper anchoring material 24, and the choice of the copper box material 24 is intricate. The pillar Wuwuling is decomposed and the copper foil material 24 is removed. As for the etching solution used today, it is advisable to use an aqueous solution of ammonium persulfate. ’丨 L bite + Superemulsified lice aqueous solution or’ Etching treatment system impregnates the object to be treated in the etching solution 91047-TYJP.1574TW.ptd Page 11 522530

=’惟將餘刻水溶液喷布噴霧或滴下至被蝕刻面上進行即 ^ 於喷布噴霧、滴下的情形,光阻處理若以旋塗器塗布 等方法對僅最上層實施時即足夠。浸潰於蝕刻液中並予蝕 1處理的情形,雖於5 〇 °C之蝕刻液浴中浸潰蝕刻卜1 〇分 里丨隹對各個的冷溫、浸潰時間則依作業量,時間等可決 定出最適條件。 /' 、其次如第4圖所示,藉由選擇蝕刻可去除鎳層2〇。至 於蝕刻液,可使用例如Mertex公司製造的Mers忖ip 等市售的鎳蝕刻劑。 其後’如第5圖所示 系巴緣樹脂3 9並予塗布,甘 表面成為均勻狀。且,此 表面,同時去除殘存的光 ’以環氧樹脂或聚醯亞胺樹脂為 次進行研磨至使絕緣樹脂層3 g之 時使柱狀導体1 8之頭部作成露出 阻膜。 其认如弟6圖所示,料壯 同的處理。亦即,於銅之另一面上亦進行相 予圖示)後,進行曝光、:旦3之甘表面上已形成光阻膜(未 敍刻,將柱狀導体17殘/^,/^欠進行銅箱材33之選澤 ㈣液,以使用硫酸羯材33。至於… 為宜。 °乳化氫水,合液或過硫酸銨水溶洛 此時:蝕刻液,:與二再藉由選擇蝕刻去除鎳層21= ’However, spraying or dropping the remaining aqueous solution onto the surface to be etched, that is, ^ In the case of spraying or dropping on the cloth, photoresist treatment is sufficient if only the top layer is implemented by a spin coater or other methods. In the case of immersion in the etching solution and pre-etching 1, although the etching is immersed in the etching bath at 50 ° C for 10 minutes, the cold temperature and immersion time of each are based on the amount of work and time. Etc. can determine the optimal conditions. / 'Second, as shown in FIG. 4, the nickel layer 20 can be removed by selective etching. As the etchant, a commercially available nickel etchant such as Mers 忖 ip manufactured by Mertex can be used. After that, as shown in Fig. 5, the rim resin 39 was applied and applied, and the surface of the sugar was uniform. And, the surface was simultaneously removed with the remaining light ′. The surface was polished with an epoxy resin or polyimide resin to 3 g of the insulating resin layer, and the head of the columnar conductor 18 was exposed as a resist film. It is believed to be the same as shown in Figure 6. That is to say, the other side is also shown on the other side of the copper), and then exposed to light: a photoresist film has been formed on the surface of the Gan 3 (not described, the columnar conductor 17 is left / ^, / ^ ow) The copper bath material 33 is selected for use, and the sulfuric acid bath 33 is preferred. As for ... Emulsified hydrogen water, liquid or ammonium persulfate water soluble. At this time: Etching liquid, and He Er by selective etching Remove the nickel layer 21

Merstrip Ν-950等市隹铉目同,使用Mertex公司製造的 π丨售鎳蝕刻劑。 其次,為於已結走士级a〜 路,如第8圖所示,在冷地理的基板之表面上形成電 仕主布光阻膜37,進行曝光、顯影 522530 五、發明說明(9) $ ’如第9圖所示,對銅箔丨9進行選擇蝕刻處理並形成電 於此時之選擇餘刻液,可使用氯化鐵水溶液,硫酸 嘈^氧1匕氯水溶液等。藉由此種處理’可形成佈線層’此 如第10圖所示,以環氧樹脂或聚醯亞胺樹脂為絕緣樹 並予塗布,其次進行研磨至絕緣樹脂層39之表面成為 1 。且,此時使柱狀導体17之頭部作成露出表面,同 日才去除殘存的光阻膜。 技“ ^後如第11圖所示,藉由含有導電粒子之異向性導電 接者劑連接市隹丰瀑伙曰ΰ5德 ¥电 口牛V体θ曰片1及2至佈線層之兩表面上,以 上載;=覆於兩面上已載置的裝配基板40之印刷基板41 軟焊/作為封裝体單位。χ,印刷基板下部係藉由 ίϊ又其:,基/連接、再予層合並可作成半導體封 ;;填:::氧樹脂、聚酿亞胺樹脂等的絕緣樹脂進 二次採用第12圖〜第22圖說明 悲有關的封裝体單位之製造。杏弟鉍形 包#柘夕石二t 乐一貝施形態係不藉由蝕刻 i曰板之兩面兩端部分予以削除 =至成固定值。如此進行的理由," j層”代替半導體封裝体單位之導線架所致。:係:用 只施形恶,包層板之製造方 在此 其記載亦可省略。 兀與第λ轭形怒相同,故 膜35:先進圖所於銅落材24之表面上形成光阻 廳後心丁曝光、顯影。於此情形下,與第—實施形態Merstrip NR-950 and other cities use the same π 丨 nickel etchant manufactured by Mertex. Next, in order to take away the class a ~ road, as shown in Fig. 8, an electric main cloth photoresist film 37 is formed on the surface of the substrate of the cold geography, and exposed and developed 522530. V. Description of the invention (9) As shown in FIG. 9, the copper foil 9 is subjected to a selective etching process to form a selective etching solution at this time, and an aqueous solution of ferric chloride, an aqueous solution of sulfuric acid, oxygen, and an aqueous solution of chlorine can be used. By this process, a wiring layer can be formed. As shown in FIG. 10, an epoxy resin or a polyimide resin is used as the insulating tree and coated, and then the surface is polished until the surface of the insulating resin layer 39 becomes 1. Also, at this time, the head of the columnar conductor 17 was made to be exposed, and the remaining photoresist film was removed on the same day. As shown in Fig. 11, after the technique, the anisotropic conductive contact agent containing conductive particles is used to connect the city's Fengpu waterfall to the 5th ¥ Diankou cattle V body θ film 1 and 2 to the two of the wiring layer On the surface, uploading; = the printed circuit board 41 covering the mounting substrate 40 already mounted on both sides is soldered / as a package unit. Χ, the lower part of the printed circuit board is based on: 基 / connection, and then a layer The combination can be used to make a semiconductor package. Filling ::: Insulating resins such as oxygen resins and polyimide resins are used a second time to illustrate the manufacturing of package-related units using Figure 12 to Figure 22. The Xixi Stone II t Le Yi Beishi morphology is not removed by etching the two ends of the two sides of the plate, i.e. to a fixed value. The reason for this is that the "layer j" replaces the lead frame of the semiconductor package unit. To. : Department: Use only for evil, the manufacturer of clad board, its description can be omitted here. It is the same as the λ yoke, so film 35: a photoresist is formed on the surface of the copper falling material 24 by the advanced image. In this case, the first embodiment

第13頁; 522530 五、發明說明(ίο) + 之:同:在於此第二實施形態,可形成導線架形用 膜36於基板兩端部上。其次如第u圖所示,進行 = =刻,將柱狀導体18及導線㈣殘存著並溶解去除 至於此時之蝕刻液,以使用硫酸 過:!酸;水溶液為宜。此時之银刻處理 形悲之情形相同。 ,、弟 只施 其次如第1 5圖所示,與第一眚祐 蝕刻去除鎳層20,其後如第^圈所_形恶相同,藉由選擇 亞胺樹脂為絕緣樹脂39並^塗I所::環氧樹脂或聚酿 樹脂層39之表面成均勻狀。且布此時使絕緣 作成露出表面,同時去除殘存的光^狀導体18之頭部 ,次如第1 7圖所示,對裝配基 同的處理。亦即,於銅箱材反亦進行相 予圖示)後,進行曝光、顯成光阻膜(未 ㈣,將柱狀導体17及導線架38m仃銅泪⑽之選澤 至於此時之則液,以使用 除㈣材33。 酸銨水溶液為宜。 · 匕乳化氧水溶液或過硫 其次,如第18圖所示,盅益 此時之蝕刻液,亦與前述第―:由二f蝕刻去除鎳層2!。 其次,為於已結束此等處;=?之情形相同。 路,如第19圖所示,在塗希 、土板之表面上形成電 後,如第2 0圖所示,對銅、〇阻,3 7,進行曝光、顯影 路。至於此時之選擇蝕刻 進仃選擇蝕刻處理並形成電 J條件,亦與第一實施形態之情形 91047.TYJP_i574TW.ptd 苐14頁 522530 五、發明說明cn) ^,此後,如第21圖所示,以環氧樹脂或聚醯亞胺樹脂 :、、s ’’彖树月曰3 9並予塗布,其次使絕緣樹脂層3 9之表面成均 句狀。 最後,與第一實施形態之情形同法實施並藉由含有導 :::之異向性導電接著劑連接市售半導体晶片至佈線層 ^兩表面上,作成兩面上已載置晶片之 上已載置晶片i、2之袭配基板係成為如第22圖般,::: 以被2;藉】;氧樹脂或聚酿亞胺樹脂等的絕心 架部分38摺曲並作成第22圖之端部43狀, 位:介由間隔件等將附有如此製作的導線架 早 予以多數連接,可使用作半導体封裝体。 、、早立 發明之功效 如上述,藉由使用申請專利範圍第1項之包居如廿I 成於其兩面上已載置晶片之封曰板並作 合等之空間,可使半導体封裝体整体之容ϋ文的排除層 發明使用的包層板因使用壓焊物,故可謀降^ :又在本 =藉由採用此包層板並進行選擇餘刻,可容^本, V體封裝体單位,故製作費用亦低廉的。 易的1造半 星之簡 第1圖為與本發明之第一實施形態有關的 体单位之製造方法之步驟1 ¥體封裝 圖。 、方法m明圖中未加工的包層材之截面 第15頁 9l047-TYJP.1574TW.ptd 522530Page 13; 522530 V. Description of the invention + Same: In this second embodiment, a lead frame-shaped film 36 can be formed on both ends of the substrate. Secondly, as shown in Fig. U, carry out == engraving, and the columnar conductor 18 and the wire ㈣ remain and are dissolved and removed. As for the etching solution at this time, sulfuric acid is used. At this time, the situation of silver engraving is the same. As shown in FIG. 15, the younger brother only applied the second layer to remove the nickel layer 20 as shown in FIG. 15. After that, the shape of the nickel layer 20 was the same as that in the first circle, and the imine resin was selected as the insulating resin 39 and coated. I: The surface of the epoxy resin or polymer resin layer 39 is uniform. And the cloth makes the insulation exposed at this time, and at the same time, the head of the remaining light conductor 18 is removed, and the assembly is treated in the same way as shown in FIG. 17. That is, after the copper box material is shown in reverse, it is exposed and developed into a photoresist film (not yet, the selection of the columnar conductor 17 and the lead frame 38m, copper tears) is as of this time In order to use liquid, in addition to ㈣33. Ammonium acid aqueous solution is suitable. · Emulsified oxygen aqueous solution or persulfur is the second, as shown in Figure 18, the etching solution at this time is also the same as the above-mentioned: etched by two f Remove the nickel layer 2.! Secondly, the situation is the same as before; =? The way, as shown in Figure 19, after the formation of electricity on the surface of Tu Xi, soil plate, as shown in Figure 20 As shown in the figure, exposure and development are performed on copper, 0, 3 and 7. As for the selective etching at this time, the selective etching process and the electrical J conditions are formed, which is also the same as that of the first embodiment 91047.TYJP_i574TW.ptd 苐 page 14 522530 V. Description of the invention cn) ^, and then, as shown in FIG. 21, epoxy resin or polyimide resin: ,, s, 彖, 彖, 9, 9, 9, 9, 9, 9, and 涂布, and then apply the insulating resin layer 3 The surface of 9 is evenly sentenced. Finally, it is implemented in the same way as in the case of the first embodiment, and a commercially available semiconductor wafer is connected to both surfaces of the wiring layer by an anisotropic conductive adhesive containing a conductive :::, and the wafer is placed on both sides. As shown in FIG. 22, the substrates on which the wafers i and 2 are placed are as shown in FIG. 22: The quilting part 38 of the oxygen resin or polyimide resin is bent and made into FIG. 22 The end portion 43 is in the shape of a bit: The lead frame with the above-mentioned production is connected to a large number via a spacer, etc., and can be used as a semiconductor package. The effect of the early invention is as described above. By using the enclosure such as 廿 I in the scope of patent application No. 1 to form a space on the two sides of which the wafer has been mounted and combined, the semiconductor package can be made. The cladding plate used in the invention of the exclusion layer of the overall content can be reduced due to the use of pressure-welded materials. ^: Again in this = By using this cladding plate and making selections for the rest of the time, it can accommodate ^ this, V body Package unit, so the production cost is low. Easy to make half of the star. Figure 1 is a diagram of the step 1 of the method of manufacturing the body unit related to the first embodiment of the present invention. 、 Method m Cross section of unprocessed cladding material in the picture on page 15 9047-TYJP.1574TW.ptd 522530

口第2圖為與本發明之第一實施形態有關的半導體封裝 体單位之製造方法之步驟說明圖中表示出已塗布柱狀導體 形成用光阻於銅層上的狀態之截面圖。 旦 口第3圖為與本發明之第一實施形態有關的半導體封裝 体單位之製造方法之步驟說明圖中表示出進行表面銅層^之 選擇#刻並已形成柱狀導體的狀態之截面圖。 曰 第4圖為與本發明之第一實施形態有關的半導體封裝 体單位之製造方法之步驟說明圖中表示已進行鎳層之弯^ 蝕刻後的狀態之截面圖。 、 第5圖為與本發明之第一實施形態有關的半導體封事 体單位之製造方法之步驟說明圖中表示出塗布絕緣樹脂(並 已研磨表層後的狀態之截面圖。 a曰“ 第6圖為與本發明之第一實施形態有關的半導體封寒 体單位之製造方法之步驟說明圖中表示出於相對面上已^ 成柱狀導体的狀態之截面圖。 7 第7圖為與本發明之第一實施形態有關的半導體封事 体單位之製造方法之步驟說明圖中表示出已選擇性的餘^ 相對面之鎳層後的狀態之截面圖。 x 第8圖為與本發明之第一實施形態有關的半導體封裝 体單位之製造方法之步驟說明圖中表示出已將電路圖案形 成用光阻樹脂賦與基底後的狀態之截面圖。 / 第9圖為與本發明之第一實施形態有關的半導體封裝 体單位之製造方法之步驟說明圖中表示出藉由蝕刻已形<成 電路圖案後的狀態之截面圖。Figure 2 is a cross-sectional view showing a state in which a method for manufacturing a semiconductor package unit according to the first embodiment of the present invention is applied to a copper layer for forming a columnar conductor. FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor package unit related to the first embodiment of the present invention, showing a state where the surface copper layer is selected and the columnar conductor has been formed. . FIG. 4 is a cross-sectional view showing a state of a method for manufacturing a semiconductor package unit according to the first embodiment of the present invention, after the nickel layer is bent and etched. Fig. 5 is a cross-sectional view showing a state of a method for manufacturing a semiconductor envelope unit according to a first embodiment of the present invention, in which an insulating resin is applied (and a surface layer has been ground. A "" 6 The figure is a cross-sectional view showing the steps of a method for manufacturing a semiconductor package body related to the first embodiment of the present invention. The figure shows a state where a columnar conductor has been formed on the opposite side. A cross-sectional view showing the state of the nickel layer on the opposite side which has been selectively selected from the drawing explaining the steps of the method for manufacturing a semiconductor envelope unit according to the first embodiment of the invention. The step description of the method for manufacturing a semiconductor package unit according to the first embodiment is a cross-sectional view showing a state where a photoresist resin for circuit pattern formation has been applied to a substrate. / FIG. 9 is the first embodiment of the present invention. The figure explaining the steps of the method for manufacturing a semiconductor package unit according to the embodiment is a cross-sectional view showing a state after the circuit pattern has been formed by etching.

522530 五、發明說明(13) 第10圖 体單位之製 已形成電路 第11圖 体單位之製 於裝配基板 上的狀態之 第12圖 体單位之製 圖。 第13圖 体單位之製 布導線架形 第14圖 体單位之製 選擇蝕刻並 第15圖 体單位之製 擇钱刻後的 第16圖 体單位之製 已研磨表層 第17圖 体單位之製 為與本發明之第— 造方法之步驟說明 之相對面上且已研 為與本發明之第— 造方法之步驟說明 之兩面上並予連接 截面圖。 為與本發明之第二 造方法之步驟說明 為與本發 造方法之 成用光阻 為與本發 造方法之 已形成柱 為與本發 造方法之 狀態之截 為與本發 造方法之 後的狀態 為與本發 造方法之 明之第二 步驟說明 於銅層上 明之第二 步驟說明 狀導体及 明之第二 步驟說明 面圖。 明之第二 步驟說明 之截面圖 明之第二 步驟說明522530 V. Description of the invention (13) Figure 10 The system of the body unit The circuit has been formed Figure 11 The system of the unit body The state of the body unit on the assembly substrate Figure 12 The system of the unit body. Fig. 13 Body unit fabric lead frame shape Fig. 14 Body unit selection Etch and Fig. 15 Body unit selection After engraving 16th body unit Milled surface 17th body unit It is a cross-sectional view on the opposite side of the description of the steps of the first method of the present invention and has been developed on both sides of the description of the steps of the first method of the present invention. The steps for the second manufacturing method of the present invention are described as being related to the achievement of the present manufacturing method. The photoresist is the same as the formed column of the present manufacturing method. The state of the step is the same as that described in the second step of the method of the present invention. The second step is described on the copper layer, and the second step is described in the figure. Sectional illustration of the second step description

91047-TOP-1574TW.ptd 實施形態有關的半導體封裝 圖中表示出塗布絕緣樹脂至 磨其上面的狀態之截面圖。 實施形態有關的半導體封裝 圖中表示出載置半導体晶片 ,再者已載置於印刷電路板 實施形態有關的半導體封寰 圖中未加工的包層材之截面 實施形悲有關的半導體封裝 圖中表示出柱狀導体及已塗 的狀態之截面圖。 實施形態有關的半導體封裝 圖中表示出進行表面銅層之 導線架線的狀態之截面圖。 實施形態有關的半導體封裝 圖中表示出已進行鎳層之選 實施形態有關的半導體封裝 圖中表示出塗布絕緣樹脂並 〇 實施形態有關的半導體封裝 圖中表示出於相對面上亦已 第17頁 522530 五、發明說明(14) 形成柱狀導体及導線架的狀態之截面圖。 第1 8圖為與本發明之第二實施形態有關的半導體封裝 体單位之製造方法之步驟說明圖中表示出已選擇性的餘刻 相對面之鎳層後的狀態之截面圖。 第1 9圖為與本發明之第二實施形態有關的半導體封裝 体單位之製造方法之步驟說明圖中表示已將電路圖案及導 線架形成用光阻樹脂賦與基底後的狀態之截面圖。 第2 0圖為與本發明之第二實施形態有關的半導體封裝 体單位之製造方法之步驟說明圖中表示出藉由蝕刻已形成 電路圖案後的狀態之截面圖。 第2 1圖為與本發明之第二實施形態有關的半導體封^ 体單位之製造方法之步驟說明圖中表示出已以絕緣樹脂^ 布基板並予填充後的狀態之截面圖。 第22圖為與本發明之第二實施形態有關的半導體封# 体早位之製造方法之步驟說明圖中表不出載置半導體曰片 於基板上並對端部已予導線架加工的狀態之截面圖。& 第23圖為本發明使用的包層金屬板之製造裝置之 正面圖。 圖號之說明 1、2 半導体晶片 3 軟焊隆起物 1 7、1 8 柱狀導體 19 銅箔層91047-TOP-1574TW.ptd Semiconductor package according to an embodiment A cross-sectional view showing a state in which an insulating resin is applied to a surface thereof after being polished. The semiconductor package diagram related to the embodiment shows the placement of a semiconductor wafer, and the semiconductor package diagram related to the embodiment of the printed circuit board. The cross section of the unprocessed cladding material in the semiconductor package diagram. A cross-sectional view showing a columnar conductor and a coated state. The semiconductor package according to the embodiment is a cross-sectional view showing a state in which a lead wire is wired on a surface copper layer. The semiconductor package diagram related to the embodiment shows that the nickel layer has been selected. The semiconductor package diagram related to the embodiment shows the coating of insulating resin and the semiconductor package diagram according to the embodiment is shown on the opposite side. Page 17 522530 V. Description of the invention (14) A sectional view of a state where a columnar conductor and a lead frame are formed. Fig. 18 is a cross-sectional view showing a state of a method of manufacturing a semiconductor package unit pertaining to a second embodiment of the present invention, showing a state where the nickel layer on the opposite side has been selectively etched. Fig. 19 is a cross-sectional view showing a state in which a circuit pattern and a photoresist for forming a lead frame have been applied to a substrate in a method for explaining a method of manufacturing a semiconductor package unit according to a second embodiment of the present invention. Fig. 20 is a sectional view showing a state of a method for manufacturing a semiconductor package unit according to a second embodiment of the present invention, showing a state after a circuit pattern has been formed by etching. FIG. 21 is a cross-sectional view showing a state of a method for manufacturing a semiconductor package unit related to a second embodiment of the present invention after the substrate is covered with an insulating resin and is filled. FIG. 22 is a step description of a method for manufacturing a semiconductor package in an early position related to the second embodiment of the present invention. The figure does not show a state in which a semiconductor chip is placed on a substrate and a lead frame is processed at the end. Section view. & Figure 23 is a front view of a cladding metal plate manufacturing apparatus used in the present invention. Explanation of drawing number 1, 2 semiconductor wafer 3 solder bump 1 7, 1 8 columnar conductor 19 copper foil layer

91047-TYJP-1574TW.ptd 第18頁 522530 五、發明說明(15) 20 、21 鍍 鎳 或 鎳 箔 層 23 回 繞 捲 軸 24 銅 箔 材 25 回 繞 捲 軸 26 I虫 刻 室 27 >28 滾 動 電 極 29 真 空 槽 30 輥 軋 單 位 31 包 層 板 32 捲 取 輥 輪 33 銅 箔 材 34 印 刷 基 板 用 包 層 板 35 ^36 ^37 光 阻 膜 38 導 線 架 線 39 樹 脂 40 裝 配 基 板 41 晶 片 填 埋 絕 緣 樹 脂 42 導 線 架 端 部 50 印 刷 基 板91047-TYJP-1574TW.ptd Page 18 522530 5. Description of the invention (15) 20, 21 Nickel-plated or nickel foil layer 23 Rewinding reel 24 Copper foil 25 Rewinding reel 26 I Worm chamber 27 > 28 Rolling electrode 29 Vacuum tank 30 Rolling unit 31 Cladding board 32 Winding roller 33 Copper foil 34 Cladding board for printed circuit board 35 ^ 36 ^ 37 Photoresist film 38 Lead wire 39 Resin 40 Assembly substrate 41 Wafer insulation resin 42 Lead frame end 50 printed circuit board

91047-TOP-1574TW.ptd 第19頁91047-TOP-1574TW.ptd Page 19

Claims (1)

[]一種半導體封裝體單位,係選擇性的蝕刻由銅/鎳/銅/ 鎳/銅之五層而成的包層板並形成半導體晶片連接用隆起 物、佈線層,於前述包層板之兩面上已載置半導體晶片而 成0 .丰後是—fgrf#丨 89115381-1574-91047TYJP. ptc 第21頁 2002.06.06.021[] A semiconductor package unit, which selectively etches a cladding board made of five layers of copper / nickel / copper / nickel / copper and forms bumps and wiring layers for semiconductor wafer connection. 0 has been placed on both sides of the semiconductor wafer. Fgrf # 丨 89115381-1574-91047TYJP. Ptc Page 21 2002.06.06.021
TW89115381A 1999-08-02 2000-08-01 Semiconductor package unit TW522530B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21892999 1999-08-02

Publications (1)

Publication Number Publication Date
TW522530B true TW522530B (en) 2003-03-01

Family

ID=16727543

Family Applications (1)

Application Number Title Priority Date Filing Date
TW89115381A TW522530B (en) 1999-08-02 2000-08-01 Semiconductor package unit

Country Status (4)

Country Link
JP (1) JP5105625B2 (en)
AU (1) AU6317100A (en)
TW (1) TW522530B (en)
WO (1) WO2001009950A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5067107B2 (en) * 2007-10-12 2012-11-07 富士通株式会社 Circuit board and semiconductor device
JP7222564B2 (en) * 2019-05-31 2023-02-15 ウルトラメモリ株式会社 Semiconductor module and its manufacturing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03188660A (en) * 1989-12-19 1991-08-16 Toppan Printing Co Ltd Lead frame material for semiconductor device and manufacture of lead frame for semiconductor device
JPH05190764A (en) * 1992-01-17 1993-07-30 Hitachi Ltd Semiconductor device
JPH08241945A (en) * 1995-03-03 1996-09-17 Sony Corp Lead frame, semiconductor device and manufacture of semiconductor device
JP3988227B2 (en) * 1997-12-01 2007-10-10 日立化成工業株式会社 Manufacturing method of semiconductor chip mounting substrate and semiconductor device
JP3497774B2 (en) * 1999-08-13 2004-02-16 株式会社ノース Wiring board and its manufacturing method
JP3798597B2 (en) * 1999-11-30 2006-07-19 富士通株式会社 Semiconductor device

Also Published As

Publication number Publication date
WO2001009950A1 (en) 2001-02-08
JP2010004064A (en) 2010-01-07
JP5105625B2 (en) 2012-12-26
AU6317100A (en) 2001-02-19

Similar Documents

Publication Publication Date Title
TWI223419B (en) Semiconductor device and method of manufacturing the same
US7514636B2 (en) Circuit component module, electronic circuit device, and method for manufacturing the circuit component module
US7364941B2 (en) Circuit device manufacturing method
US6441314B2 (en) Multilayered substrate for semiconductor device
KR100615382B1 (en) Clad board for printed-circuit board, multilayered printed-circuit board, and method of manufacture thereof
KR100563177B1 (en) Lead frame, the manufacturing method, semiconductor device and the manufacturing method
EP1119048B1 (en) Lead frame having bumps thereon and manufacturing method thereof
US6951811B2 (en) Method of producing vias and other conductor parts on an electrode terminal forming surface of a semiconductor wafer
JP2004119726A (en) Method of manufacturing circuit device
US20230154857A1 (en) Two-sided interconnected embedded chip packaging structure and manufacturing method therefor
KR100658022B1 (en) Method of manufacturing circuit device
JP2004119727A (en) Method of manufacturing circuit device
JP2002043752A (en) Wiring board, multilayer wiring board, and their manufacturing method
TW495436B (en) Clad plate of interposer formation for semiconductor device, interposer for semiconductor device, and their manufacturing methods
TW522530B (en) Semiconductor package unit
JP2005317903A (en) Circuit component module, circuit component module stack, recording medium and manufacturing method of them
KR20040030301A (en) Method of manufacturing circuit device
JP2001110928A (en) Manufacturing method of semiconductor package
JP2004058578A (en) Laminated metal foil with carrier and method for manufacturing package using it
JP4642061B2 (en) Circuit device manufacturing method
JPH08340179A (en) Organic resin multilayer wiring board and manufacture thereof
JP4107951B2 (en) Circuit device and manufacturing method thereof
JP2008147237A (en) Metal laminated plate for qfn and its manufacturing method, and method of manufacturing qfn using the metal laminated plate for qfn
JP2002110900A (en) Semiconductor package unit and its manufacturing method
JP2002100853A (en) Method of manufacturing for wiring board

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees