JPH05190764A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the storage capacity of the title semiconductor device by a method wherein respective electrode terminals for at least two LSI chips which have been bonded to both faces of a mounting film are connected to wiring patterns on the mounting film. CONSTITUTION:A wiring layer 32 is formed on a wiring film 30 to which bumps 11, 21 for connection use on a first Si chip and a second Si chip 10, 20 are connected via connection wiring parts 31a, 31b. The bumps 11 for connection use on the first Si chip and the bumps 21 for connection use on the second Si chip are connected to the wiring layer 32 according to a prescribed wiring pattern. The bumps 11 for connection use are connected to bonding pads 35 on the wiring film 30. The bumps 21 for connection use on the second Si chip 20 and the bonding pads 35 on the wiring film 30 are connected electrically in a desired relationship. Thereby, one semiconductor device which is provided with the two Si chips 10, 20 can be constituted, and the storage capacity of the semiconductor device can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology and, more particularly, to a technology which is particularly effective when applied to a semiconductor device, and more particularly to a technology which is useful for forming wiring of a semiconductor device.

[0002]

2. Description of the Related Art Recently, there has been a demand for high speed / high integration of LSI. Regarding such high speed / high integration of LSI, for example, "A 23nS 1Mbit
BiCMOS DRAM ”. More recently, DR
Technologies for increasing the storage capacity of DRAM per package have been developed for higher integration of LSIs such as AM. However, such increase in storage capacity has hitherto been caused by miniaturization of elements and the like on LSI chips. It was achieved by high integration of itself.

[0003]

However, it is not possible to expect a dramatic increase in the storage capacity of a DRAM or the like housed in one package simply by increasing the degree of integration of the LSI chip by using the element miniaturization technology. ..

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device housed in one package, for example, a semiconductor device capable of dramatically increasing the storage capacity of a DRAM. .. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the semiconductor device of the present invention includes a bonding pad, a mounting film on which a wiring pattern continuous with the bonding pad is formed, and at least two or more LSI chips adhered to both surfaces of the mounting film. Each of the electrode terminals of the chip is connected to the wiring pattern of the mounting film.

[0006]

[Operation] At least two L's in one package
Since the SI chip is housed and these input / output terminals are connected to the wiring pattern of the mounting film and further to the bonding pad of the mounting film, there is one L
2 in a package the size of which the SI chip was stored
Since the above LSI chips are mounted and the bonding pad can be connected to the lead frame as usual, the package size is virtually the same as the conventional one and the lead frame connection structure is also the conventional one. In the same manner as described above, a semiconductor device with dramatically high integration is achieved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a semiconductor device 100 according to the present invention.
2 is an exploded perspective view of the semiconductor device 100 shown in FIG.

As shown in FIG. 1, the semiconductor device 100 has a wiring film (mounting film) 30 having bonding pads 35, 35 ... And a desired wiring pattern (see FIG. 3), and adheres to the upper surface of the film 30. First S
The i-chip 10 and the second Si chip 20 adhered to the lower surface of the wiring film 30 are provided (here, S
As the i-chips 10 and 20, for example, 8-bit DRAM
Is used). Then, the above-mentioned first Si chip 10
Also, in the second Si chip 20, the surface on which the elements are formed (the surface on which the connection bumps 11, 11, ... 12, 12, ... Are formed) 10A, 20A side is the upper surface 30 of the wiring film 30.
The A / lower surface 30B is arranged so as to face and abut.

By the way, as described above, the first and second Si
The chips 10 and 20 on the upper surface 30A of the wiring film 30,
When arranging each on the lower surface 30B, its surface 10
A and a plurality of connection bumps 1 provided on 20A, respectively
, 11 and 11, and 21, 21, 21 ... (FIG. 2) are provided on the upper surface 30A / lower surface 30B of the wiring film 30, respectively, and have a plurality of connection wiring portions 31a, 31a ... 31b, 31b.
Correspondingly (not shown in FIG. 2), ie, they are glued so as to electrically connect to each other. In this way, when electrically connecting the connection bumps 11, 11 ... And 21, 21 ... And the connection wiring portions 31a, 31a ... And 31b, 31b. , 11 ... and 21, 21 ... And the connection wiring portions 31a, 31a ... and 31b, 31b ... are arranged with solder balls 40, 40, 40 ... First and second Si chips 10, 20
Are connected to the wiring film 30 in a predetermined positional relationship. As a result, one semiconductor device 100 including the two Si chips 10 and 20 is configured.

In this way, the first and second Si chips 1
0, 20 connection bumps 11, 11, ..., 21, 21 ...
However, in the wiring film 30 connected via the connection wiring portions 31a, 31a ..., 31b, 31b.
(FIG. 3) is formed, and predetermined wiring patterns 32C, 32C ... Are formed on the wiring layer 32. Then, according to the wiring patterns 32C, 32C ...
The connection bumps 11, 11, ... Of the i chip and the connection bumps 21, 21, ... Of the second Si chip, and the connection bumps 11, 11 ... And the bonding pads 35, 35 of the wiring film 30 are , And the second Si chip 2
The connection bumps 21, 21 ... Of 0 and the bonding pads 35, 35 ... Of the wiring film 30 are electrically connected in a desired relationship. Therefore, by connecting the two Si chips 10 and 20 by using the wiring film 30, the signal line (wiring board on which the chip is mounted) necessary for exchanging signals between the two Si chips 10 and 20 is connected. (Provided in) is omitted.

FIG. 3 is an exploded perspective view of the wiring film (mounting film) 30 on which two Si chips 10 and 20 are provided on both sides. As shown in the figure, the wiring film 30 has a multi-layered structure (three-layered structure in the illustrated example), and a wiring layer (conductor wiring layer) 32 in the middle is provided with an upper surface 32 thereof.
Thin film wiring protection seals 33 and 34 are attached so as to cover A and the lower surface 32B (not shown in the figure), respectively. An insulating film (organic film) having excellent heat resistance is used as the protective seals 33 and 34.

Of the wiring layers 32, the bumps 11, 11, ... And the bonding pads 3 are formed on the wiring layer 32 as described above.
5, 35, ..., the bumps 21, 21 ... and the bonding pads 35, 35 ..., and further, a wiring pattern for electrically connecting the bumps 11, 11 ... and the bumps 21, 21 ... in a desired relationship. 32C is formed.

The first wiring pattern 32C is
So that the connection portions (connection wiring portions) 31a, 31a ... With the bumps 11, 11, ... Of the Si chip 10 are exposed on the surface 30A side of the wiring film 30 at the desired positions of the wiring protection seal 33. 33a ... Are provided.
Further, outside the area of the protective seal 33 where the first Si chip 10 abuts (the area indicated by the broken line in FIG. 3), the wiring pattern 32d forming the bonding pad 35 (the area indicated by the alternate long and short dash line in the figure) is provided. Connection holes 33b, 33b ... For bonding pads are provided at the positions. On the other hand, the bump 2 of the second Si chip 20 of the wiring pattern 32C
Connection parts (connection wiring parts) 32a, 32a with 1, 21, ...
The connection hole 3 is provided at a predetermined position of the protective seal 34 corresponding to.
4a, 34a ... Are provided.

In the wiring film 30 having the above structure, the first Si film is formed according to the wiring pattern 32C.
Signals are exchanged between the chip 10 and the second Si chip 20, and the wiring from the constant voltage power supply supplied to these two chips is shared. Significant reduction is possible. or,
LS of the first Si chip 10 and the second Si chip 20
I Signal exchange with the outside (lead frame) is shown in Fig. 1.
As shown in FIG. 3, since the bonding pads 35, 35 ... Are bonded via bonding wires, the package for accommodating the two chips 10, 20 and the wiring film 30 may be the conventional package.

When joining the wiring layer 32 and the protective seals 33 and 34, an adhesive having excellent heat resistance is used. Further, the connection holes 33a of the protective seals 33, 34,
When forming 33a ... 33b, 33b, ..., 34a, 34a ...
Alternatively, a protective seal having no connection hole is attached to the front surface of the wiring layer 32, and after the attachment, the wiring pattern 32 is formed.
Connection holes 33a, 33a ..., 34 according to C, 32C ...
a, 34a ... May be provided. Also, the first S
If the i-chip 10 and the second Si chip 20 are directly connected, a through hole may be provided in the wiring film 30 and these may be connected to each other through the through hole.

FIG. 4 is a sectional view showing a state in which the bumps 11 of the first Si chip 10 and the bumps 21 of the second Si chip 20 are connected via the wiring film 30. As shown in the figure, the bumps 11 of the first Si chip 10
In order to electrically connect the bumps 21 of the second Si chip 20, the bumps 11 and the wiring pattern 3 of the wiring layer 32 are connected.
2C is connected by the solder ball 40a, and the wiring pattern 32C and the bump 21 of the second Si chip are connected by the solder ball 40b. As described above, the welding using the solder balls 40 (40a, 40b) not only electrically connects the first Si chip 10 and the second Si chip 20 but also physically connects them. become. First joined together in this way
The Si chip 10, the second Si chip 20, and the wiring film 30 are housed in a package (not shown) as one semiconductor device 100. At this time, the semiconductor device 10
0 and the lead frame (not shown) are electrically connected by the bonding wire 41 shown in FIG.

As described in detail above, according to the semiconductor device of this embodiment, at least two Si chips 10 and 20 are housed in one package, and the bumps 1 are
, 11, 21 ... Are connected to the wiring pattern of the wiring film 30 and further to the bonding pads 35, 35 ...
Two Si chips are mounted in a package the size of which the chip was housed, and the bonding pad 3
Since the connection with the lead frames 5, 35, ... Can be made as usual, the semiconductor device 100 is
The size of the package is almost the same as the conventional one, and the connection structure with the lead frame is the same as the conventional one.

FIG. 5 is a perspective view showing another embodiment according to the present invention. In this embodiment, the first Si chip 50 and the second Si chip 60 support the supporting portion 71 of the lead frame 70. The back surface sides 50B (not shown in the drawing) and 60B in which the element regions are not formed are opposed to each other and are integrally joined. Two chips 5 like this
When 0 and 60 are bonded, the surfaces 50A and 60A (not shown in the figure) of the first and second Si chips both face outward, and bonding wires (not shown) are connected to these surfaces 50A and 60A. To be done. Even when the structure of this embodiment is adopted, two or more Si chips can be accommodated in one package, and high integration of the semiconductor device can be achieved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in bonding the wiring film and the Si chip,
Not only the solder balls but also other adhesive members such as Au balls may be used. Further, instead of the wiring film having a three-layer structure used in this example, a wiring film having a five-layer structure may be used, for example.

In the above description, the RAM, which is the field of application behind the invention made mainly by the present inventor, is the background.
I explained the technology of mounting semiconductor chips such as
For example, it can be applied to WSI (wafer scale integration).

[0021]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. LSI that can be stored in one package
Since the number of chips is increased, high integration of semiconductor devices housed in one package can be achieved.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor device 100 according to the present invention.

FIG. 2 is an exploded perspective view of the semiconductor device 100 shown in FIG.

FIG. 3 is an exploded perspective view of a wiring film 30 in which two Si chips are installed on both sides.

FIG. 4 is a cross-sectional view showing a state in which the bumps 11 of the first Si chip and the bumps 21 of the second Si chip are connected via the wiring film 30.

FIG. 5 is a perspective view showing a semiconductor device according to another embodiment of the present invention in which two Si chips are joined using a lead frame.

[Explanation of symbols]

 10 First Si Chip 20 Second Si Chip 32 Wiring Layer 32C Wiring Pattern 30 Wiring Film (Mounting Film) 35 Bonding Pad 40 Solder Ball (Metal Ball)

Claims (3)

[Claims] 1. A bonding pad, a mounting film on which a wiring pattern continuous with the bonding pad is formed, and at least two or more LSI chips bonded to both surfaces of the mounting film, each of the two or more LSI chips being provided. A semiconductor device, wherein electrode terminals are connected to a wiring pattern of the mounting film. 2. The semiconductor device according to claim 1, wherein the mounting film is a multi-layered film including a wiring layer on which the wiring pattern is formed and a protective film adhered to the surface of the wiring layer. .. 3. The semiconductor device according to claim 1, wherein the wiring pattern of the mounting film and the electrode terminal of the LSI chip are connected by a metal ball.