GB2117564A - Mounting one integrated circuit upon another - Google Patents

Mounting one integrated circuit upon another Download PDF

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Publication number
GB2117564A
GB2117564A GB8208967A GB8208967A GB2117564A GB 2117564 A GB2117564 A GB 2117564A GB 8208967 A GB8208967 A GB 8208967A GB 8208967 A GB8208967 A GB 8208967A GB 2117564 A GB2117564 A GB 2117564A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
chip
contact pads
chips
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8208967A
Other versions
GB2117564B (en
Inventor
William John Talbot
John William Richer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Priority to GB8208967A priority Critical patent/GB2117564B/en
Publication of GB2117564A publication Critical patent/GB2117564A/en
Application granted granted Critical
Publication of GB2117564B publication Critical patent/GB2117564B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

In an integrated circuit assembly a memory chip 3 is mounted on a logic chip 1. A first set of contact pads 2 on the logic chip 1 are electrically joined to corresponding contact pads 4 on the memory chip 3 to secure the chips to one another in face-to-face relationship and to provide interconnections between the chips. A further set of contact pads 5 on the logic chip 1 are provided for external connections to the integrated circuit assembly. The assembly may be contained in a protective package 7, 8 or may be mounted on an etched metal film using a tape assisted bonding technique. <IMAGE>

Description

SPECIFICATION Integrated circuit assemblies The present invention relates to integrated circuit assemblies and in particular to integrated circuit assemblies which include more than one integrated circuit chip.
In the field of data processing it is often required that two or more integrated circuits are functionally linked to one another, for example, an integrated circuit memory may be required to be functionally linked to an integrated circuit providing a logic function.
It has previously been proposed to provide logic and memory functions on a single chip.
This arrangement can be provided at a minimum cost and can result in a package which occupies a relatively low area on a printed circuit board, for example. However, such an arrangement provides only one combination of memory and logic functions and thus a different chip is required for every memory or logic variant. The necessity to stock a large number of different chips carrying all memory and logic variations required is a costly operation and hence is a significant disadvantage of this proposal.
It has also been proposed to provide memory and logic functions on separate chips mounted in the same package. This arrangement provides maximum flexibility in that any required combination of memory and logic chip may be included in the package. However, a disadvantage with this arrangement is that contact or bond pads, to which external connections to-the chip are made, are required to interconnect the two chips thus reducing the total number of pads available for external connections to the package. Further disadvantages with this arrangement lie in the necessity to provide a substrate to carry interconnections between the two chips and the necessity for an extra assembly operation joining the chips to the interconnections.Also, for example, if the chips are mounted in side by side relationship a larger package which occupies a larger area of a printed circuit board results.
According to the present invention an integrated circuit assembly includes; a first integrated circuit chip having first and second pluralities of contact pads; and a second integrated circuit chip having on one face a plurality of contact pads corresponding one with each of the first plurality of contact pads on the first integrated circuit chip when the first and second chips are in face-to-face relationship, the corresponding pairs of contact pads of each chip being bonded to one another to form electrical connections therebetween; the second plurality of contact pads forming external terminations for the assembly.
Preferably the contact pads on the first integrated circuit chip are on one face thereof, the second plurality of contact pads being positioned around the periphery of the chip and the first plurality of contact pads being positioned within the second plurality.
An integrated circuit assembly will now be described, by way of example, with reference to the accompanying drawing, in which: Figure 1 is a side view of an integrated circuit memory chip mounted on an integrated circuit logic chip, Figure 2 is a plan view of the integrated circuit logic chip of Fig. 1, and Figure 3 shows both integrated circuit chips enclosed in a package.
Referring to the drawings, an integrated circuit logic chip 1 carries a set of contact pads 2 arranged in the form of a square on one of its surfaces. The contact pads 2 are electrically joined to parts of the circuitry of the logic chip 1 which require to be electrically connected to an integrated circuit memory chip 3.
The memory chip 3 has a set of contact pads 4 corresponding in position with the pads 2 on the logic chip 1. The contact pads 4 are electrically joined to parts of the circuitry of the memory chip 3 which are required for electrical connection to the logic chip 1.
The memory chip 3 is mounted on the logic chip 1 in face-to-face relationship as shown in Fig. 1, corresponding pairs of the contacts pads 2 and 4 being electrically joined to one another to complete the required interconnections between the logic and memory chips.
The joins also serve to secure the memory chip 3 to the logic chip 1.
The logic chip 1 has a further set of contact pads 5 which are positioned around the periphery of the surface carrying the contact pads 2. The contact pads 5 are electrically joined to those parts of the logic chip circuitry which require to be electrically connected to external terminations 6 of a package 7. The package 7 supports the integrated circuit chips and provides a housing which physically protects the chips. A lid or cover 8 seals the package 7.
Conductors 9 electrically connect the contact pads 5 to the external terminations 6 of the package 7.
A method by which the package assembly may be produced will now be described. It will be appreciated that integrated circuit chips normally are provided with a single set of contact pads positioned around the periphery of one of their surfaces. In the case of the logic chip forming part of the present invention an additional set of contact pads are required to be positioned within the boundary of the normal set. A number of logic chips carrying a range of circuit variants may be provided, similarly, a range of memory chips, smaller in size than the logic chips, and with contact pads corresponding to the inner pads of the logic chip may be provided.
The inner contact pads 2 of the logic chip 1 and the contact pads 4 of the memory chip 3 are each provided with a coating of solder having a convex surface forming so called solder bumps.
After testing, the logic chip 1 is bonded to an inner surface of the package 7 by a conventional low temperature chip attachment process. The memory chip 3, after testing, is positioned in face-to-face relationship with the logic chip 1, the contact pads 2 of the logic chip abutting the contact pads 4 of the memory chip and the solder bumps are caused to reflow by the application of heat. When the solder is allowed to cool and solidify the corresponding pairs of contact pads 2 and 4 are electrically joined securing the memory chip to the logic chip.
The conductors 9 are bonded between the outer set of contact pads 5 on the logic chip and the external terminations 6 of the package 7 by the conventional means such as, for example, a thermocompression or ultrasonic wire bonding technique. Finally, the lid 8 of the package 7 is bonded in place by a conventional bonding technique.
It will be appreciated that the order of assembly described is by way of example only and may, if desired, be varied. For example, the logic and memory chips may be mounted in face-to-face relationship prior to bonding the logic chip to the package.
The structure described has advantages over other structures previously proposed to functionally link integrated circuits in that it provides a choice of different combinations of memory and logic chips, and which occupies little or no extra area on a printed circuit board than a single chip package, hence reducing printed circuit board and assembly costs.
A further advantage is that the electrical load on the memory chip is reduced due to the short interconnections between the chips attained by the face-to-face mounting and this reduced loading improves the operating speed of the device. The face-to-face mounting also minimises parasitic capacitance effects which are sometimes produced in integrated circuit structures.
While an assembly mounted in a package has been described, this idea also applies to an assembly using the TAB (Tape assisted Bonding) technique where chips are mounted on etched metal films. The TAB technique is described in an article entitled "VLSI Packaging" on pages 73 and 74 of "Electronics" December 29, 1981.
While an assembly comprising a memory chip and a logic has been described above, it will be appreciated that both chips may be of the same type, for example, both may be memory chips or both may be logic chips.

Claims (7)

1. An integrated circuit assembly including: a first integrated circuit chip having first and second pluralities of contact pads; and a second integrated circuit chip having on one face a plurality of contact pads corresponding one with each of the first plurality of contact pads on the first integrated circuit chip when the first and second chips are in face-to-face relationship, the corresponding pairs of contact pads of each chip being bonded to one another to form electrical connections therebetween and to secure the chips together; the second plurality of contact pads on the first chip forming terminations for external connections to the assembly.
2. An integrated circuit assembly as claimed in Claim 1, in which the first and second pluralities of contact pads on the first integrated circuit chip are located on one face thereof.
3. An integrated circuit assembly as claimed in Claim 2, in which the second plurality of contact pads are positioned around the periphery of said one face of the chip and the first plurality of contact pads are positioned within the second plurality.
4. An integrated circuit assembly as claimed in Claim 1, 2 or 3 mounted within a common protective package.
5. An integrated circuit assembly as claimed in any preceding claim, in which one of said circuit chips carries memory circuitry and the other of said circuit chips carries logic circuitry.
6. An integrated circuit assembly as claimed in Claim 5, in which said first circuit chip carries the logic circuitry and said second circuit chip carries the memory circuitry.
7. An integrated circuit assembly constructed substantially as hereinbefore described with reference to the accompanying drawing.
GB8208967A 1982-03-26 1982-03-26 Mounting one integrated circuit upon another Expired GB2117564B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8208967A GB2117564B (en) 1982-03-26 1982-03-26 Mounting one integrated circuit upon another

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8208967A GB2117564B (en) 1982-03-26 1982-03-26 Mounting one integrated circuit upon another

Publications (2)

Publication Number Publication Date
GB2117564A true GB2117564A (en) 1983-10-12
GB2117564B GB2117564B (en) 1985-11-06

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GB8208967A Expired GB2117564B (en) 1982-03-26 1982-03-26 Mounting one integrated circuit upon another

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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2160707A (en) * 1984-05-14 1985-12-24 Gigabit Logic Inc Integrated circuit package
GB2172429A (en) * 1985-03-15 1986-09-17 Smiths Industries Plc Electronic circuit assembly
EP0304263A2 (en) * 1987-08-17 1989-02-22 Lsi Logic Corporation Semiconductor chip assembly
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6630372B2 (en) 1997-02-14 2003-10-07 Micron Technology, Inc. Method for routing die interconnections using intermediate connection elements secured to the die face
US6712480B1 (en) 2002-09-27 2004-03-30 Silicon Light Machines Controlled curvature of stressed micro-structures
US6767751B2 (en) 2002-05-28 2004-07-27 Silicon Light Machines, Inc. Integrated driver process flow
US6782205B2 (en) 2001-06-25 2004-08-24 Silicon Light Machines Method and apparatus for dynamic equalization in wavelength division multiplexing
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6800238B1 (en) 2002-01-15 2004-10-05 Silicon Light Machines, Inc. Method for domain patterning in low coercive field ferroelectrics
US6801354B1 (en) 2002-08-20 2004-10-05 Silicon Light Machines, Inc. 2-D diffraction grating for substantially eliminating polarization dependent losses
US6806997B1 (en) 2003-02-28 2004-10-19 Silicon Light Machines, Inc. Patterned diffractive light modulator ribbon for PDL reduction
US6813059B2 (en) 2002-06-28 2004-11-02 Silicon Light Machines, Inc. Reduced formation of asperities in contact micro-structures
US6822797B1 (en) 2002-05-31 2004-11-23 Silicon Light Machines, Inc. Light modulator structure for producing high-contrast operation using zero-order light
US6829092B2 (en) 2001-08-15 2004-12-07 Silicon Light Machines, Inc. Blazed grating light valve
US6829077B1 (en) 2003-02-28 2004-12-07 Silicon Light Machines, Inc. Diffractive light modulator with dynamically rotatable diffraction plane
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1425283A (en) * 1973-06-04 1976-02-18 Ibm Multifunction wafers
EP0032068A1 (en) * 1979-12-07 1981-07-15 Le Silicium Semiconducteur Ssc Three terminal diode and mounting of a main semiconductor component and the diode in a single housing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1425283A (en) * 1973-06-04 1976-02-18 Ibm Multifunction wafers
EP0032068A1 (en) * 1979-12-07 1981-07-15 Le Silicium Semiconducteur Ssc Three terminal diode and mounting of a main semiconductor component and the diode in a single housing

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2160707A (en) * 1984-05-14 1985-12-24 Gigabit Logic Inc Integrated circuit package
GB2172429A (en) * 1985-03-15 1986-09-17 Smiths Industries Plc Electronic circuit assembly
US4974057A (en) * 1986-10-31 1990-11-27 Texas Instruments Incorporated Semiconductor device package with circuit board and resin
EP0304263A2 (en) * 1987-08-17 1989-02-22 Lsi Logic Corporation Semiconductor chip assembly
EP0304263A3 (en) * 1987-08-17 1990-09-12 Lsi Logic Corporation Semiconductor chip assembly
US6630372B2 (en) 1997-02-14 2003-10-07 Micron Technology, Inc. Method for routing die interconnections using intermediate connection elements secured to the die face
US6956294B2 (en) * 1997-02-14 2005-10-18 Micron Technology, Inc. Apparatus for routing die interconnections using intermediate connection elements secured to the die face
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6452260B1 (en) 1997-09-02 2002-09-17 Silicon Light Machines Electrical interface to integrated circuit device having high density I/O count
US6782205B2 (en) 2001-06-25 2004-08-24 Silicon Light Machines Method and apparatus for dynamic equalization in wavelength division multiplexing
US6829092B2 (en) 2001-08-15 2004-12-07 Silicon Light Machines, Inc. Blazed grating light valve
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6800238B1 (en) 2002-01-15 2004-10-05 Silicon Light Machines, Inc. Method for domain patterning in low coercive field ferroelectrics
US6767751B2 (en) 2002-05-28 2004-07-27 Silicon Light Machines, Inc. Integrated driver process flow
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
US6822797B1 (en) 2002-05-31 2004-11-23 Silicon Light Machines, Inc. Light modulator structure for producing high-contrast operation using zero-order light
US6813059B2 (en) 2002-06-28 2004-11-02 Silicon Light Machines, Inc. Reduced formation of asperities in contact micro-structures
US6801354B1 (en) 2002-08-20 2004-10-05 Silicon Light Machines, Inc. 2-D diffraction grating for substantially eliminating polarization dependent losses
US6712480B1 (en) 2002-09-27 2004-03-30 Silicon Light Machines Controlled curvature of stressed micro-structures
US6806997B1 (en) 2003-02-28 2004-10-19 Silicon Light Machines, Inc. Patterned diffractive light modulator ribbon for PDL reduction
US6829077B1 (en) 2003-02-28 2004-12-07 Silicon Light Machines, Inc. Diffractive light modulator with dynamically rotatable diffraction plane
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same

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Publication number Publication date
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PE20 Patent expired after termination of 20 years

Effective date: 20020325