WO1996004682A1 - Electronic circuit package - Google Patents

Electronic circuit package Download PDF

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Publication number
WO1996004682A1
WO1996004682A1 PCT/GB1995/001785 GB9501785W WO9604682A1 WO 1996004682 A1 WO1996004682 A1 WO 1996004682A1 GB 9501785 W GB9501785 W GB 9501785W WO 9604682 A1 WO9604682 A1 WO 9604682A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
device
electronic circuit
terminals
bonded
Prior art date
Application number
PCT/GB1995/001785
Other languages
French (fr)
Inventor
Katherine Margaret Medlock
Anthony Richard Cowburn
Clive Peter Savage
William Morris Morgan
Original Assignee
Havant International Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB9415297.2 priority Critical
Priority to GB9415297A priority patent/GB2292004A/en
Application filed by Havant International Limited filed Critical Havant International Limited
Publication of WO1996004682A1 publication Critical patent/WO1996004682A1/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15173Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

An electronic circuit package comprises a carrier substrate (20), e.g. in the form of a flexible circuit, having a plurality of electrical contacts (80) defined thereon, an integrated circuit device (10) mounted on the substrate including a plurality of terminals (30) located towards the periphery of the device, the plurality of terminals being individually connected by means of conductive wires (31) to a corresponding electrical contact (80, 82) on the substrate. The package further comprises a conductive path means acting as a conductive bridge between a selected device terminal (50) and an associated electrical contact (108) on the substrate, the conductive path means comprising a conductive region (172) defined in or on an outward facing surface of the device, the selected terminal connected by a first conductive wire (180) to the conductive region which is in turn connected by a second conductive wire (182) to the associated electrical contact.

Description

ELECTRONIC CIRCUIT PACKAGE

This Invention relates to electronic circuit packages and particularly to the electrical Interconnection of Integrated circuit devices to a carrier substrate.

One technique for mounting unpackaged Integrated circuit (IC) devices to a substrate or carrier Is called direct chip attach. This attachment technique Is well established for the attachment of IC devices directly to printed circuit boards and more recently it has been developed for use in attaching IC devices to flexible circuits. This latter application is known as chip-on-flex. In both applications, electrical connection between the IC device and the printed circuit on the substrate may be achieved by wlrebondlng connection pads on the chip to circuit lines defined on the substrate.

Another technique for mounting integrated circuit devices to' a substrate or carrier is tape automated bonding (TAB). In this technique a flexible carrier substrate carries fine electrically conducting circuit lines to the periphery of a chip. The substrate is in the form of a cinematographic film having perforations along the edge of the film for advancing the film during manufacture.

Cantilevered electrically conductive support leads or legs are bonded to peripheral terminals on an integrated circuit device, which is situated in an aperture in the TAB substrate. The TAB substrate and chip may both be supported on a heat sink. The connections between the support legs of the TAB support and the terminals of the chip are made automatically in a operation known as inner lead bonding, normally in a single operation, for example by thermo-compression welding. An example of such a TAB support for an integrated circuit is disclosed in EP-A-

0368741 (Bull), and includes provision of part of the TAB support to provide a bridge relative to the integrated circuit device. The technique differs substantially from the technique of mounting integrated circuit devices directly to substrates, for example flexible substrates, and wlrebondlng between terminal pads on the chip and terminal pads on the circuit lines of the substrate.

In a paper entitled "Overlooked Technology Offers Cost Savings" by Chris Haythornthwaite, New Electronics, 22nd November 1994, there is disclosed an electronic circuit package formed by direct chip attach and wlrebondlng. A carrier substrate has a plurality of electrical contacts defined thereon, and an integrated circuit device attached to the carrier substrate including a plurality of terminals located towards the periphery of the device. The plurality of terminals are individually connected to corresponding electrical contacts on the substrate by wirebonds.

The wireability of circuits using wirebonded direct chip attach IC devices is becoming more and more difficult due to the increasing complexity of the device. In order to accommodate the pin-out of a particular device it is often necessary to introduce extra circuit layers and shielding layers on the substrate onto which the IC device is mounted.

The problem is exemplified in Figure 1 which shows a schematic plan view of an IC chip 10 mounted on a printed circuit carrier 20. Around the periphery of the upper surface of the chip are a plurality of terminals (or pads) 30, 32 which are employed to connect the active semiconductor components (not shown) of the chip 10 to circuit lines 80 on the circuit carrier 20. The printed circuit carrier 20 also includes a row of connectors 40 to which terminals 30 of the chip are to be connected. Circuit lines 80 are defined on the carrier extending from a region adjacent the periphery of the chip to the connectors 40. The terminals 30 on the device are connected by wirebonds 31 to the circuit lines 80. Also included on the circuit carrier 20 is a second row of connectors 42 to which terminals 32 are connected via wirebonds 31 and circuit lines 82. Circuit lines 80 and 82 are provided in a single circuit layer on the substrate 20.

It can be seen that the pad configuration of the device requires that terminal 50 and terminal 51 on the chip 10 are connected to connector 43 on the substrate 20. This requirement necessitates the provision, in the circuit, of contact pads 60 and 61 to which terminals 50 and 51 are respectively connected by means of wirebonds 31. Connecting contact pads 60 and 61 to connector 43 is circuit line 102 (shown in phantom) which extends around the edge of the device. In a similar manner, terminals 53 and 54 are connected to connector 44 by means of contact pads 62 and 63 on circuit line 104. Similarly, terminal 52 is connected to connector 45 by means of contact pad 64 on circuit line 106.

It is clear from Figure 1 that provision of circuit lines 102, 104 and 106 necessitates the provision of an additional circuit layer. A shielding layer (not shown) may also be required to reduce interference between signals carried on, for example, circuit lines 80 and 102 or circuit lines 80 and 106.

It will be appreciated that for reasons of clarity,

Figure 1 demonstrates only a simple example of the problem which is solved by means of a relatively simple two layer circuit pattern on the carrier. In reality, the pad configuration of a particular IC device may require a significantly more complex circuit pattern comprising three or more circuit layers and possibly shield layers to reduce the amount of interference between circuit lines. The reduction of interference is especially critical where for example the signals on circuit lines 80 are extremely low in amplitude, such as signals produced when reading magnetically recorded data from a data storage disk.

Thus it can be seen that with the increase in complexity of today's integrated circuit devices, the electrical connection of an integrated circuit device to a carrier substrate is becoming more complex and often results in the need to employ multiple circuit layers in order to achieve the required interconnection while ensuring that electrical interference between the circuit lines is kept to a minimum.

The present invention seeks to address this problem and accordingly provides, in a first aspect, an electronic circuit package comprising: a carrier substrate having a plurality of electrical contacts defined thereon; and an integrated circuit device attached to the substrate including a plurality of terminals located towards the periphery of the device, said plurality of terminals being individually connected to corresponding electrical contacts on the substrate by conductive wires which are bonded at each end to respective terminals and contacts and which extend along paths raised from the surfaces to which they are bonded; in which the electronic circuit package includes conductive path means acting as a conductive bridge across at least part of the device, the conductive path means comprising a conductive region defined in or on an outward facing surface of the device and at least two conductive wires each of which is bonded at one end thereof to the conductive region and at the other end thereof to an associated terminal or contact and which extend along paths raised from the surfaces to which they are bonded. In one arrangement having particular utility, the conductive path means acts as a conductive bridge between a selected device terminal and an associated electrical contact on the substrate, said selected terminal being connected by a first conductive wire to said conductive region, and said region connected by a second conductive wire to said associated electrical contact.

Although it is possible that the conductive path means would comprise a single conductive region for bridging between a single terminal and a single electrical contact, the present invention finds especially advantageous use in bridging between multiple electrical contacts and terminals. Accordingly, a preferred circuit package comprises a plurality of conductive path means for connecting individual selected device terminals with associated electrical contacts on the substrate, said plurality of conductive path means including a plurality of conductive regions in the form of conductive lines defined in or on said substrate surface.

The present invention may be employed to connect a terminal at one edge of the device with an electrical contact adjacent the same edge of the device. However, it will be apparent that in the majority of applications, the conductive bridge is especially useful in connecting a terminal at one edge of the device to an electrical contact adjacent a second edge of the device.

In a preferred embodiment, the conductive regions are located in or on a central area of said device surface. In one embodiment, the conductive regions are formed into a circuit element which is attached to the device surface. The plurality of conductive regions may advantageously be disposed in multiple circuit layers of the IC device. The carrier substrate may take the form of a rigid printed circuit board, or in a preferred embodiment, a flexible circuit having a circuit, including said electrical contacts, defined thereon.

Although the conductive bridge may extend across, for example, a corner of the integrated circuit, the invention finds particular application where the said conductive bridge extends across an inner surface region of the device which is positioned inwardly of said peripheral terminals.

As has been mentioned, it is preferred that there is provided a plurality of conductive path means acting as a bridge across the device, said conductive path means comprising a plurality of conductive regions defined in or on an outward facing surface of the device. It may be arranged that at least parts of the conductive regions lie in substantially the same plane and are spaced apart in that plane. In some arrangements at least parts of the conductive regions lie in different planes with one conductive region passing over the other conductive region.

The invention finds particular utility where the conductive path means includes a conducting wire between a peripheral terminal of the device and the said conductive region, and/or where the conductive path means includes a conducting wire between the said conductive region and an electrical contact on the carrier substrate.

Preferably the or each of said conductive regions are located in or on a central area of said device surface. Conveniently the or each of said conductive regions comprises a pair of electrical wirebond contact pads interconnected by a circuit line. In a second aspect of the invention there is provided an integrated circuit device having such conductive regions defined thereon which, when the device is mounted on a substrate, are connectable to selected device terminals and electrical contacts to provide a conductive bridge therebetween. In this aspect there is also provided in accordance with the present invention an integrated circuit device having a plurality of terminals located towards the periphery of the device and adapted to be individually connected to corresponding electrical contacts on a carrier substrate to which the device is adapted to be attached when in use; in which said device has a conductive region defined in or on an outwardly facing surface of the device, connectable to selected device terminals and electrical contacts to provide a conductive bridge therebetween, the conductive region being connectable by at least two conductive wires each of which is bonded at one end thereof to the conductive region and at the other end thereof to an associated terminal or contact, and which extend along paths raised from the surfaces to which they are bonded.

It is particularly preferred that the conductive region comprises a passive conductive region on or in the surface of the device which, before any connection by way of bonded wires, is independent of any active component within the device. Also it is preferred that the conductive region is positioned inwardly of the peripheral terminals.

It is to be appreciated that where features of the invention are set out herein with regard to apparatus according to the invention, such features may also be provided with regard to a method according to the invention, and vice versa.

in particular, there is provided in accordance with the invention a method of making connections in an electronic circuit package comprising: providing a carrier substrate having a plurality of electrical contacts defined thereon, and an integrated circuit device attached to the carrier substrate and Including a plurality of terminals located towards the periphery of the device; connecting said plurality of terminals individually to corresponding electrical contacts on the substrate by conductive wires which are bonded at each end to respective terminals and contacts, and which extend along paths raised from the surfaces to which they are bonded; and providing conductive path means acting as a conductive bridge across at least part of the device by the steps of: providing a conductive region defined in or on an outward facing surface of the device; and connecting to the conductive region at least two conductive wires each of which is bonded at one end thereof to the conductive region and at the other end thereof to an associated terminal or contact, and which extend along paths raised from the surfaces to which they are bonded.

The invention has significant advantages over the prior art wiring technique. Firstly, the use of such a conductive bridge on or in said substrate allows for a reduction in the complexity of the circuitry on the carrier substrate and in particular provides a reduction in wiring density which results in the ability more efficiently to position chip interconnections with the circuit substrate in order to minimise copper conductor lengths.

Furthermore, a simplified wiring layout leads to the potential for reducing the number of wiring levels (i.e. circuit layers). This reduction in the number of circuit layers leads to a reduction in manufacturing costs of the circuit substrate. An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which :-

Figure 1 shows in schematic plan view an electronic circuit package comprising an integrated device mounted on a circuit carrier having a circuit pattern according to the prior art;

Figure 2 shows in schematic plan view an electronic circuit package according to one embodiment of the present invention;

Figure 3 is a diagrammatic section along the line III - III in Figure 2;

Figure 4 is a plan view of another embodiment of the invention, generally similar to that shown in Figures 2 and 3, but with more complex interconnections;

Figure 5 shows a diagrammatic cross section along the lines V - V in Figure 4; and

Figures 6a to 6k show diagrammatically a series of different wire arrangements which may be made in embodiments of the present invention.

As has been mentioned previously, for the purposes of clarity in the drawings, the schematics of Figures 1 and 2 are greatly simplified in comparison to actual electronic circuit packages. In particular it is to be noted that the total number of terminals shown on the integrated circuit device is smaller than will commonly be required on IC devices. For example a typical device may include upwards of twenty terminals along each peripheral edge with a resultant requirement for a greatly increased number of circuit lines on the carrier substrate.

Turning to a consideration of Figure 2, there is shown an electronic circuit package in which the integrated circuit device has the same pad configuration as that of the device in Figure 1. The carrier substrate 20 is formed from conventional flexible circuit comprising a flexible polyimide carrier to which is bonded a copper layer. The circuit pattern is defined in the copper layer by conventional techniques e.g, by etching. The flexible circuit is mounted on a metal layer e.g. of aluminium onto which the integrated circuit device is directly attached, through an aperture in the flex circuit, by means of thermally conductive adhesive. The aluminium layer acts as a heat sink for the device. As in the package of Figure 1, there is included a first row of connectors 40 and a second row of connectors including connectors 42. Connection of terminals 30 to connectors 40 is effected in the same manner as is employed in Figure 1 i.e. by means of circuit lines 80 leading from the connectors 40 towards the periphery of the device in position relative to the terminals 30 to allow wirebonding between an individual terminal and circuit line. Terminals 32 are connected to connectors 42 also in the same manner as described above in relation to Figure 1. As is known in the art, one common wirebonding technique involves aluminium or gold wires which are ultrasonically or thermosonically bonded to the terminal and to the circuit line on the flexible circuit. Layers of nickel and gold are placed on the circuit line to form a robust bonding pad for the bond.

In contrast to the electronic package of Figure 1, the package of Figure 2 further includes a circuit coupon 150 comprising a flexible carrier layer e.g. of polyimide on which are defined copper pads 160 to 167. Also defined on the polyimide layer are copper connecting lines 170, 172 and 174. The coupon is bonded to the upper surface of the device by means of a suitable adhesive.

As in Figure 1, terminals 50 and 51 are required to be connected to connector 43. This connection is achieved as follows: terminal 50 is connected by wirebond 180 to pad 162. Terminal 51 is connected by wirebond 181, over the IC device, to pad 163. Pad 166 is connected by wirebond 182 to an additional circuit line 108 which extends from the periphery of the chip to connector 43.

It will be appreciated that circuit line 108 is fabricated in the same circuit layer as circuit lines 80 and 82. Thus connection of a terminal at one edge of chip to a carrier circuit connector beyond the opposite side of the chip is effected by wirebonding across the chip, in contrast to the known wiring technique as exemplified in Figure 1 in which it is necessary to take a circuit line around the edge of the chip.

Connection of terminals 53 and 54 to connector 44 is achieved in a similar manner by means of wirebond 183 to pad 160 and wirebond 184 to pad 161. Wirebond 185 is connected between pad 167 and circuit line 109 extending from the periphery of the chip to connector 44. In a similar manner, terminal 52 is connected to connector 45 by means of wirebond 186, contact pad 164, circuit line 174, pad 165, wirebond 187 and circuit line 110. As for circuit line 108, circuit lines 109 and 110 are fabricated in the same circuit layer as lines 80 and 82.

It will be readily appreciated from a comparison of the figures that the printed circuit layout of Figure 2 is greatly simplified over that of Figure 1. Furthermore, all circuit lines are provided in a single circuit layer thus leading to a reduction in manufacturing complexity and cost. In addition, the fact that there is no 'crossing' of circuit lines in different layers (e.g. lines 80 and line 106 in Figure 1), the scope for interference between signals on the circuit lines is much reduced.

Figure 3 is a diagrammatic cross section along the line III - III in Figure 2, and illustrates in detail the construction described hereinbefore. In Figure 3, the two wirebonds 180 and 31 are shown, attached respectively to terminal 50 and gold plated pad 162, and to terminal 32 and a similar contact pad (not shown in Figure 2) which is indicated in Figure 3 at 83, connected to the circuit line 82. The aluminium heat sink on which the substrate 20 and the device 10 are mounted, is indicated at 25.

Although the coupon of the described embodiment comprises only a single circuit layer, it will be apparent that depending on the particular pad configuration of the IC device and configuration of the circuit pattern it may be advantageous or necessary to employ a multi circuit layer coupon.

Furthermore although in the above described embodiment a coupon or patch is employed to provide the inter- connection across the IC device, the present invention may alternatively be implemented by means of contact pads and wires introduced directly into the IC device during its construction. This alternative implementation may, in many circumstances, be the preferred implementation as it avoids the need to manufacture a separate coupon for attachment to the device.

In Figure 4, there is shown another embodiment of the invention which includes a number of modifications from the embodiment shown in Figure 2. Figure 5 shows a diagrammatic cross section along the lines V - V in Figure 4. In Figures 4 and 5, components corresponding to components in Figures 2 and 3 are indicated by like reference numerals.

Figure 4 shows connections to the chip 10 from two layers of flexible substrate 20, but this is not relevant to the features of the invention. The embodiment of Figure 4 differs from that of Figure 2 firstly in that the conductive regions are formed directly in the surface and on the surface of the chip, and not on a separate coupon.

Secondly, the conductive regions in the central part of the chip are provided on two different levels, with various conductive regions passing over and under each other.

Figure 4 shows that there are positioned in the central region 11 of the chip 10 a plurality of conductive regions indicated generally at 175 and 176. As shown in particular in Figure 5, a first conductive region 175 passes from left to right in Figure 5 at an upper level on the left hand side of the figure, and then passes beneath two conductive regions 176, before rising again to the surface of the chip on the right hand side. The conductive region 175 is coupled to a first selected terminal 56 on the left hand side of the chip in Figure 5, and is connected to a second terminal 57 on the right hand side, by wirebonds 188 and 189 respectively. Other interconnections by wirebonds will be apparent from Figure 4 and 5.

Figures 6a to 6k show a number of alternative and combined wiring patterns which may be achieved in embodiments of the invention. Components corresponding to components in previous Figures will be indicated by like reference numerals. In Figures 6a to 6k, the various components are as described in the previous description, but with various alternative interconnections made. In the arrangements of 6a to 6k, peripheral terminals of the chip are indicated by reference numerals 200 to 215. Wirebonds interconnecting various of the terminals and the contact pads, are indicated by 300 to 329. Contact pads on the chip are indicated by the reference numerals 400 to 422. Electrical contacts on the substrate 20 are indicated by reference numerals 500 to 514. Conductive lines on the chip 10 are indicated by reference numerals 600 to 607. Thus the conductive regions formed on or in the surface of the chip are provided by various combinations of contact pads 400 etc and conductive lines 600 etc or the wirebond 316 in Figure 6h. Various patterns 600 etc shown of the conductive regions on the chip surface are all in one plane, except for Figure 61, where one conductive line 605 overlies another conductive line 606, and in Figures 6h and 6k where raised wirebonds 316 and 327 are provided.

It is a feature of the conductive regions represented by elements 600 etc. and 400 etc. that they are preferably passive components on or in the surface of the device, which do not in themselves have contact with active components within the integrated circuit device. That is to say that, although various of the conductive regions may be connected to active semi-conductor functions within the integrated circuit device by way of wirebonds, it is preferred that there is no direct electrical connection between the conductive regions on or in the surface of the device, and the internal active components of the device, before interconnections are made by wirebonds.

Claims

1. An electronic circuit package comprising: a carrier substrate (20) having a plurality of electrical contacts (80, 82, 108) defined thereon; and an integrated circuit device (10) attached to the substrate (20) including a plurality of terminals (30, 32) located towards the periphery of the device, said plurality of terminals (30, 32) being individually connected to corresponding electrical contacts (80, 82) on the substrate (20) by conductive wires (31) which are bonded at each end to respective terminals (30, 32) and contacts (80, 82), and which extend along paths raised from the surfaces to which they are bonded; characterised in that the electronic circuit package includes conductive path means acting as a conductive bridge across at least part of the device, the conductive path means comprising a conductive region (172) defined in or on an outward facing surface of the device (10) and at least two conductive wires (180, 181, or 182) each of which is bonded at one end thereof to the conductive region (172) and at the other end thereof to an associated terminal (50, 51) or contact (108), and which extend along paths raised from the surfaces to which they are bonded.
2. An electronic circuit package according to any preceding claim in which the said conductive bridge extends across an inner surface region of the device (10) which is positioned inwardly of said peripheral terminals (30, 32).
3. An electronic circuit package according to claim 1 or 2 in which there is provided a plurality of conductive path means acting as a bridge across the device, said conductive path means comprising a plurality of conductive regions (172, 170) defined in or on an outward facing surface of the device.
4. An electronic circuit package according to claim 3 in which at least parts of the conductive regions (172, 170) lie in substantially the same plane and are spaced apart in that plane.
5. An electronic circuit package according to claim 3 or 4 in which at least parts of the conductive regions (172, 170) lie in different planes with one conductive region passing over the other conductive region.
6. An electronic circuit package according to any preceding claim in which the conductive path means includes a conducting wire (180) between a peripheral terminal (50) of the device, and the said conductive region (172).
7. An electronic circuit package according to any preceding claim in which the conductive path means includes a conducting wire (182) between the said conductive region (172) and an electrical contact (108) on the carrier substrate (20).
8. An electronic circuit package according to any preceding claim in which the conductive path means acts as a conductive bridge between a selected device terminal (50) and an associated electrical contact (108) on the substrate (20), said selected terminal (50) being connected by a first conductive wire (180) to said conductive region (172), and said region (172) being connected by a second conductive wire (182) to said associated electrical contact (108).
9. An electronic circuit package according to any preceding claim in which the conductive path means acts as a conductive bridge between a device terminal (50) located at a first edge of said device (10) and an associated electrical contact (108) located adjacent a second edge of said device.
10. An electronic circuit package according to any preceding claim in which the or each of said conductive regions (172) are located in or on a central area of said substrate surface.
11. An electronic circuit package according to any preceding claim in which the or each of said conductive regions comprises a pair of electrical wirebond contact pads (162, 163) interconnected by a circuit line (172).
12. An electronic package according to any preceding claim, wherein the carrier substrate (20) comprises a flexible circuit including said electrical contacts (80), defined thereon.
13. An electronic circuit package according to any preceding claim, further including an encapsulant layer encapsulating said integrated circuit device and said conductive wires.
14. A method of making connections in an electronic circuit package comprising: providing a carrier substrate (20) having a plurality of electrical contacts (80, 82, 108) defined thereon, and an integrated circuit device (10) attached to the carrier substrate (20) and including a plurality of terminals (30, 32), located towards the periphery of the device, connecting said plurality of terminals (30, 32) individually to corresponding electrical contacts (80, 82) on the substrate (20) by conductive wires (31) which are bonded at each end to respective terminals (30, 32) and contacts (80, 82), and which extend along paths raised from the surfaces to which they are bonded; and characterised by providing conductive path means acting as a conductive bridge across at least part of the device (10) by the steps of: providing a conductive region (172) defined in or on an outward facing surface of the device (10); and connecting to the conductive region (172) at least two conductive wires (180, 181, or 182) each of which Is bonded at one end thereof to the conductive region (172) and at the other end thereof to an associated terminal (50, 51) or contact (108), and which extend along paths raised from the surfaces to which they are bonded.
15. An integrated circuit device having a plurality of terminals (30, 32) located towards the periphery of the device and adapted to be individually connected to corresponding electrical contacts (80, 82) on a carrier substrate (20) to which the device (10) is adapted to be attached when in use, characterised in that said device (10) has a conductive region (172) defined in or on an outwardly facing surface of the device (10), connectable to selected device terminals and electrical contacts to provide a conductive bridge therebetween, the conductive region (172) being connectable by at least two conductive wires (180, 181, 182) each of which is bonded at one end thereof to the conductive region and at the other end thereof to an associated terminal (50, 51) or contact (108), and which extend along paths raised from the surfaces to which they are bonded.
16. An integrated circuit device according to claim 15 in which the conductive region (172) comprises a passive conductive region on or in the surface of the device which, before any connection by way of bonded wires, is independent of any active component within the device (10).
17. An integrated circuit according to claim 15 or 16 in which the or each of said conductive regions comprises a pair of electrical wirebond contact pads (162, 163) interconnected by a circuit line (172).
18. An integrated circuit according to claim 15, 16 or 17 in which the conductive region (172) is positioned inwardly of the peripheral terminals.
PCT/GB1995/001785 1994-07-29 1995-07-27 Electronic circuit package WO1996004682A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB9415297.2 1994-07-29
GB9415297A GB2292004A (en) 1994-07-29 1994-07-29 Electronic circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AU31193/95A AU3119395A (en) 1994-07-29 1995-07-27 Electronic circuit package

Publications (1)

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WO1996004682A1 true WO1996004682A1 (en) 1996-02-15

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Application Number Title Priority Date Filing Date
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Country Status (3)

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AU (1) AU3119395A (en)
GB (1) GB2292004A (en)
WO (1) WO1996004682A1 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999017368A1 (en) * 1997-09-29 1999-04-08 Raytheon Company Three-dimensional component stacking using high density multichip interconnect decals
EP1351299A2 (en) * 2002-04-04 2003-10-08 Diehl Munitionssysteme GmbH & Co. KG Fexible and thin circuit construction
US8716932B2 (en) 2011-02-28 2014-05-06 Apple Inc. Displays with minimized borders
US8804347B2 (en) 2011-09-09 2014-08-12 Apple Inc. Reducing the border area of a device
US9110320B2 (en) 2012-08-14 2015-08-18 Apple Inc. Display with bent inactive edge regions
US9195108B2 (en) 2012-08-21 2015-11-24 Apple Inc. Displays with bent signal lines
US9209207B2 (en) 2013-04-09 2015-12-08 Apple Inc. Flexible display with bent edge regions
US9601557B2 (en) 2012-11-16 2017-03-21 Apple Inc. Flexible display
US9600112B2 (en) 2014-10-10 2017-03-21 Apple Inc. Signal trace patterns for flexible substrates
US10411084B2 (en) 2016-12-26 2019-09-10 Lg Display Co., Ltd. Flexible display device providing structures to minimize failure generated in bent portion

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5636147A (en) * 1979-08-31 1981-04-09 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
US5016082A (en) * 1988-09-16 1991-05-14 Delco Electronics Corporation Integrated circuit interconnect design
US5055907A (en) * 1989-01-25 1991-10-08 Mosaic, Inc. Extended integration semiconductor structure with wiring layers
US5060052A (en) * 1990-09-04 1991-10-22 Motorola, Inc. TAB bonded semiconductor device having off-chip power and ground distribution
US5231305A (en) * 1990-03-19 1993-07-27 Texas Instruments Incorporated Ceramic bonding bridge

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2218847B (en) * 1988-05-16 1991-04-24 Gen Electric Co Plc Carrier for semiconductor devices
FR2638895A1 (en) * 1988-11-08 1990-05-11 Bull Sa Integrated circuit carrier and process for its manufacturing, integrated circuit adapted to support and housing resulting in

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5636147A (en) * 1979-08-31 1981-04-09 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
US5016082A (en) * 1988-09-16 1991-05-14 Delco Electronics Corporation Integrated circuit interconnect design
US5055907A (en) * 1989-01-25 1991-10-08 Mosaic, Inc. Extended integration semiconductor structure with wiring layers
US5231305A (en) * 1990-03-19 1993-07-27 Texas Instruments Incorporated Ceramic bonding bridge
US5060052A (en) * 1990-09-04 1991-10-22 Motorola, Inc. TAB bonded semiconductor device having off-chip power and ground distribution

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 005, no. 091 (E - 061) 13 June 1981 (1981-06-13) *

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999017368A1 (en) * 1997-09-29 1999-04-08 Raytheon Company Three-dimensional component stacking using high density multichip interconnect decals
EP1351299A2 (en) * 2002-04-04 2003-10-08 Diehl Munitionssysteme GmbH & Co. KG Fexible and thin circuit construction
EP1351299A3 (en) * 2002-04-04 2006-03-01 Diehl BGT Defence GmbH & Co.KG Fexible and thin circuit construction
US8716932B2 (en) 2011-02-28 2014-05-06 Apple Inc. Displays with minimized borders
US8804347B2 (en) 2011-09-09 2014-08-12 Apple Inc. Reducing the border area of a device
US9933875B2 (en) 2011-09-09 2018-04-03 Apple Inc. Reducing the border area of a device
US9652096B2 (en) 2011-09-09 2017-05-16 Apple Inc. Reducing the border area of a device
US10474268B2 (en) 2011-09-09 2019-11-12 Apple Inc. Reducing the border area of a device
US9110320B2 (en) 2012-08-14 2015-08-18 Apple Inc. Display with bent inactive edge regions
US9195108B2 (en) 2012-08-21 2015-11-24 Apple Inc. Displays with bent signal lines
US9939699B2 (en) 2012-08-21 2018-04-10 Apple Inc. Displays with bent signal lines
US9601557B2 (en) 2012-11-16 2017-03-21 Apple Inc. Flexible display
US9209207B2 (en) 2013-04-09 2015-12-08 Apple Inc. Flexible display with bent edge regions
US9640561B2 (en) 2013-04-09 2017-05-02 Apple Inc. Flexible display with bent edge regions
US9600112B2 (en) 2014-10-10 2017-03-21 Apple Inc. Signal trace patterns for flexible substrates
US10411084B2 (en) 2016-12-26 2019-09-10 Lg Display Co., Ltd. Flexible display device providing structures to minimize failure generated in bent portion

Also Published As

Publication number Publication date
GB9415297D0 (en) 1994-09-21
GB2292004A (en) 1996-02-07
AU3119395A (en) 1996-03-04

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