GB2160707A - Integrated circuit package - Google Patents

Integrated circuit package Download PDF

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Publication number
GB2160707A
GB2160707A GB8512092A GB8512092A GB2160707A GB 2160707 A GB2160707 A GB 2160707A GB 8512092 A GB8512092 A GB 8512092A GB 8512092 A GB8512092 A GB 8512092A GB 2160707 A GB2160707 A GB 2160707A
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United Kingdom
Prior art keywords
semiconductor substrate
integrated circuit
high speed
package
lines
Prior art date
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Granted
Application number
GB8512092A
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GB2160707B (en
GB8512092D0 (en
Inventor
Tushar R Gheewala
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Gigabit Logic Inc
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Gigabit Logic Inc
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Publication of GB8512092D0 publication Critical patent/GB8512092D0/en
Publication of GB2160707A publication Critical patent/GB2160707A/en
Application granted granted Critical
Publication of GB2160707B publication Critical patent/GB2160707B/en
Expired legal-status Critical Current

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Microwave Amplifiers (AREA)

Abstract

A package contains a semiconductor substrate 34 having a high speed, e.g. gallium arsenide, integrated circuit 29 mounted thereon, and the substrate may be adapted to provide controlled impedance transmission lines, ground lines, electronic components, by-pass capacitors 14, impedance- matching capacitors 26, terminating resistors, diodes, voltage regulators 16, and the like. The package may be ceramic or metal, and provides protection against mechanical or chemical damage. Multiple GaAs or other high speed IC's as well as conventional silicon IC's can be mounted on the semiconductor substrate. The semiconductor substrate carrier is made from silicon and a GaAs IC mounted on the semiconductor substrate may be directly used in hybrid circuits without the need for a ceramic or metal package around the individual semiconductor substrate carriers. <IMAGE>

Description

SPECIFICATION High speed package for integrated circuits BACKGROUND OF THE INVENTION The present invention relates to the packaging of a high speed integrated circuit so that there is precise control of the transmission lines connecting the high speed integrated circuit, such as a GaAs IC, with other components such as resistors and capacitors that are closely associated with the high speed IC. It is also desirable to precisely control the transmission lines connecting the high speed IC to input/output terminals of a ceramic package. Fine linewidth control permits precise control of transmission line impedance and also permits a high density of signal lines and input/output lines. Fine linewidth creates additional room so that ground lines or a ground plane can be inserted between the signal transmission lines which causes a reduction in cross talk.Comparable fine lines in ceramic packages are limited to 100 micrometers in linewidth whereas metal lines as small as 2 to 3 micrometers can be routinely defined on a smooth semiconductor substrate.
It is also desirable to provide very low impedance transmission lines for by-passing power supply disturbances. Transmission lines of extremely low impedance are routinely fabricated during semiconductor processing by depositing insulators such as SiO2 and Si3N4 on the semiconductor substrate. These insulators are deposited on semiconductor material with a thickness in the order of 1,000 angstroms. Such thin dielectrics permit the fabrication of very low impedance transmission lines. In a standard manner, diodes can be formed on the semiconductor substrate, in close proximity to the high speed GaAs IC, for protection against static discharge. Transistors, formed in the same way, can be used in close proximity to the GaAs IC as off-chip drivers.The silicon semiconductor substrate also allows the use of nonlinear impedance devices and clamping devices in close proximity to the GaAs or other high speed IC.
It has been the objective of workers in this field to provide a package for high speed integrated circuits so that support components and the transmission lines of the carrier package do not inhibit the high speed characteristics of the integrated circuit. The considerations in the design of any high speed IC package are a combination of mechanical, electrical and physical considerations.
SUMMARY OF THE INVENTION According to the present invention and exemplary embodiments thereof described herein, an improved form of packaging high speed GaAs ICs is provided. In preferred form, a GaAs IC is attached to a semiconductor substrate by either epoxy, solder or eutectic bond and the electrical connections are made by wire bonds between the semiconductor substrate and the GaAs IC. The GaAs IC can also be "flip-mounted" where multiple solder balls (also known as C4s) are used. In this case the input, output, power and ground lines from the GaAs IC are directly soldered to signal lines on the semiconductor substrate carrier. The signal transmission lines are fabricated on the semiconductor substrate carrier which also contains low impedance capacitors that are used to bypass power supply disturbances that may be present on the power supply lines.The semiconductor substrate can also carry resistors, filters, impedance-matching networks, impedance transformers, and active semiconductor devices such as diodes, bipolar and field effect transistors and voltage regulators. Methods of fabricating such devices or semiconductor substrates is well known in the art. The semiconductor substrate is then mounted within a ceramic package which provides input and output connections from the high speed IC and semiconductor substrate to a printed circuit card. The ceramic package provides protection from environmental hazards such as shock, moisture, corrosive chemicals and the like. Also, multiple semiconductor substrate carriers can be packaged on a single ceramic package or a printed circuit board which method of packaging provides a convenient means for the construction of hybrid circuits.Use of a semiconductor substrate allows fine control over transmission linewidth and impedance and permits the inclusion of active and passive electrical devices on the substrate carrier.
Accordingly, it is the object of the present invention to provide an improved package for high speed ICs.
Another object of this invention is to provide a substrate carrier package in which the transmission line width can be precisely controlled and wherein the carrier package complements the characteristics of the high speed IC.
Another object of the present invention is to provide an IC carrier package in which passive electronic components such as resistors and capacitors are a part of the carrier package.
A further object of the present invention is to include active semiconductor devices in a substrate carrier package that complement the characteristics of the high speed IC that it carries.
BRIEF DESCRIPTION OF THE DRAWINGS The objects and features of the present invention will become better understood after consideration of the following description taken in conjunction with the drawings in which: Figure 1 shows a perspective view of a high speed integrated circuit and its connection to a semiconductor substrate carrier which con tains transmission lines and related support devices such as resistors, by-pass capacitors, impedance-matching capacitors, transistors and voltage regulators, Figure 2 shows GaAs IC's mounted on semiconductor carrier chips which in turn are mounted on a multilayer printed circuit board, Figure 3 shows a respective view of a high speed integrated circuit and its connection to a semiconductor substrate carrier which contains transmission lines surrounded by a ground plane, and Figure 4 shows a micro-strip signal line on top of an insulator which in turn rests on a ground plane.
DESCRIPTION OF THE PREFERRED EMBODI MENTS Turning now to Fig. 1, a GaAs IC 28 is shown bonded by a conducting epoxy such as polyimide based epoxy or silver epoxy to a semiconductor substrate 34 which is in turn mounted on a ceramic carrier 10. There are many ways of bonding GaAs IC 28 to semiconductor substrate 34. In one method a drop of epoxy (or polyimide) is put on the substrate and the GaAs IC is placed on it and then rubbed gently and baked at 200-300'C. In another method at higher temperatures, 300-500 C, the GaAs IC and the substrate carrier are soldered together in a standard manner. Electrical connection between the GaAs integrated circuit 28 and the semiconductor substrate 34 is accomplished by a wire-bond connection 30.It can also be accomplished by soldering, beams or different shaped wires such as those used in tape automated bonding where the cross-section of the wire is rectangular. Signal transmission line 20 is used to connect an input or output line of the GaAs integrated circuit 28 to such things as a matching capacitor 26 which, in a standard manner, is physically deposited on and is a part of the semiconductor substrate 34. Wire 46, which can also be a solder joint, weld, tape or beams, then connects the matching capacitor 26 on semiconductor substrate 34 to an input or output terminal 24 located on the ceramic chip carrier 10. Input output line 24 is also physically connected to input/output line 22 which electrically con nects the entire package to other electronic circuitry in a system.The GaAs chip 28 is also shown connected to by-pass capacitor 14 which has been deposited on semiconductor substrate 34. By-pass capacitor 14 is in turn connected through wife 18 to input/output line 12 located on ceramic chip carrier 10.
In a standard manner, resistor 32 is deposited on semi-conductor substrate 34 and is connected to a transmission line 36 and to the GaAs integrated circuit 28 by wires 40.
Resistor 32 is also connected to the ceramic carrier chip 10 by wire 38.
Active electrical devices such as a voltage regulator 16 can be physically deposited on semiconductor substrate 34 as shown.
Transmission lines 42 connect the voltage regulator 16 to the GaAs chip 28 through wires 43. The wires 44 are used to connect the voltage regulator 16 to the ceramic chip carrier 10.
Fig. 3 shows a ground plane 50 on the semiconductor substrate 34 which surrounds the signal lines 52 and minimizes cross-talk between signals. Transmission line impedance can be controlled by varying the distance between the ground plane and the transmission line. The signal lines 52 can be the socalled coplanar transmission lines as shown in Fig. 3 or the so-called micro-strip lines 54 as shown in Fig. 4. Fig. 4 shows a signal line 54 mounted on an insulator 56 which is in turn mounted on a ground plane 50. The dimensions of the signal lines 52 and 54 and the dielectric 56 are so chosen as to yield the desired impedance. The ground plane 50 on the semiconductor substrate 34 is electrically connected to ground planes (not shown) on the GaAs IC 28.
Fig. 2 shows several GaAs IC's 28 connected to their semiconductor substrates 34 which are in turn bonded to a multi-layer printed circuit card 48. The GaAs IC's 28 and their semiconductor substrates 34 are connected to one another by wires 50 which are standard printed circuit card traces. Multilayer printed circuit card 48 has several circuit layers that electrically connect the semiconductor substrates 34.
While the preferred embodiments of the present invention have been described and illustrated, various modifications will be apparent to those skilled in the art and it is intended to include all such modifications and variations within the scope of the appended

Claims (9)

claims. CLAIMS
1. A high speed integrated circuit contained in a package comprising a semiconductor substrate means having an integrated circuit mounted thereon wherein said semiconductor substrate means is adapted to provide controlled impedance transmission lines, ground lines and electronic components connected to said integrated cir cuit.
2. A system as in claim 1 wherein said integrated circuit is a high speed GaAs integrated circuit and said semiconductor sub strate means is a silicon-based semiconductor.
3. A system as in claim 1 wherein said semiconductor substrate means is mounted on a plastic chip carrier means which is adapted to provide electrical connec tions and protection from contamination.
4. A high speed integrated circuit con tained in a package comprising plural semiconductor substrates containing integrated circuits which are mounted on a circuit means and wherein said semiconductor substrates are adapted to provide controlled impedance transmission lines, ground lines and electronic components connected to said integrated circuits.
5. A high speed integrated circuit contained in a package comprising passive components on a semiconductor substrate carrying a high speed integrated circuit wherein said passive components capacitively bypass power supply lines located on said semiconductor substrate and wherein said passive components are reverse-biased diode junctions.
6. A high speed integrated circuit contained in a package comprising a semiconductor substrate carrier having an integrated circuit mounted thereon and wherein high speed signal lines of said semiconductor substrate carrier are terminated with matching resistors that are part of said semiconductor substrate carrier.
7. A high speed integrated circuit contained in a package comprising constant impedance coplanar microstrip lines placed on an insulator which is on a semiconductor substrate carrier and wherein said microstrip lines are connected to an integrated circuit located on said semiconductor substrate carrier.
8. A high speed integrated circuit contained in a package comprising a semiconductor substrate means having an integrated circuit mounted theron wherein said semiconductor substrate means is adapted to provide controlled impedance transmission lines.
9. A high speed integrated circuit contained in a package and constructed and arranged substantially as hereinbefore described with reference to and as illustrated in the accompanying drawing.
GB8512092A 1984-05-14 1985-05-13 Ga as integrated circuit package Expired GB2160707B (en)

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US60972884A 1984-05-14 1984-05-14

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GB2160707A true GB2160707A (en) 1985-12-24
GB2160707B GB2160707B (en) 1988-10-19

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DE (1) DE3516954A1 (en)
FR (1) FR2564244B1 (en)
GB (1) GB2160707B (en)

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GB2248517A (en) * 1990-10-04 1992-04-08 Communications Satellite Corp Method of packaging microwave semiconductor components and integrated circuits

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US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
FR2623662B1 (en) * 1987-11-20 1990-03-09 Labo Electronique Physique CONNECTION DEVICE FOR ULTRA-FAST DIGITAL INTEGRATED CIRCUITS
JPH0226243U (en) * 1988-08-08 1990-02-21
US20030089998A1 (en) * 2001-11-09 2003-05-15 Chan Vincent K. Direct interconnect multi-chip module, method for making the same and electronic package comprising same

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GB2117564A (en) * 1982-03-26 1983-10-12 Int Computers Ltd Mounting one integrated circuit upon another
GB2136203A (en) * 1983-03-02 1984-09-12 Standard Telephones Cables Ltd Through-wafer integrated circuit connections

Cited By (2)

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Publication number Priority date Publication date Assignee Title
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
GB2248517A (en) * 1990-10-04 1992-04-08 Communications Satellite Corp Method of packaging microwave semiconductor components and integrated circuits

Also Published As

Publication number Publication date
JPS6116539A (en) 1986-01-24
FR2564244A1 (en) 1985-11-15
FR2564244B1 (en) 1988-12-02
DE3516954A1 (en) 1985-11-14
GB2160707B (en) 1988-10-19
GB8512092D0 (en) 1985-06-19

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