JPS58210650A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58210650A JPS58210650A JP57093888A JP9388882A JPS58210650A JP S58210650 A JPS58210650 A JP S58210650A JP 57093888 A JP57093888 A JP 57093888A JP 9388882 A JP9388882 A JP 9388882A JP S58210650 A JPS58210650 A JP S58210650A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- wire
- bonding pad
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置のパッケージに係シ、特に半導体チ
ップからのリード線の取り出し構造に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a package for a semiconductor device, and more particularly to a structure for taking out lead wires from a semiconductor chip.
（２）従来技術と問題点
第１図は従来のセラミックパッケージの断面図を示して
いる。半導体チップ１はセラミックパッケージ２のキャ
ビティ３内に配置され、半導体チップのボンデングパッ
ド４とセラミックパッケージのボンデングパッド５との
間がワイヤーボンデングされている。この鴇合半専体チ
ップのボンデングパッド４とセラミックパッケージのボ
ンデングパッド５とが離れているとワイヤーが長くなり
、短絡事故や耐衝撃性の低下を招くため、半導体チップ
の大きさに合せたパッケージを使用しなければカーらな
かった。(2) Prior Art and Problems FIG. 1 shows a sectional view of a conventional ceramic package. A semiconductor chip 1 is placed in a cavity 3 of a ceramic package 2, and bonding pads 4 of the semiconductor chip and bonding pads 5 of the ceramic package are wire-bonded. If the bonding pads 4 of this half-dedicated chip and the bonding pads 5 of the ceramic package are separated, the wires will become long, leading to short-circuit accidents and reduced impact resistance. It didn't work unless I used the same package.
最近のＬＳＩは多機能化、大容量化され、リード端子数
も増大しているが、微細加工技術の進歩によってチップ
サイズは小形化出来るようＫなった。このような小形、
多端子チップに対して、従来のように半導体チップのサ
イズに合せたセラミックパッケージを使うと、そのボン
デングパッドの間隔が秋くなｐ１生セラミックシート（
グリーンシート）上に導電路パターンを形成し、これを
積み重ねて焼成するラミネートセラミックパッケージの
製法ではボンデングパッドの位置積度や微細パターンの
製作が困難であるなど大きな藺題が生ずる。また、最近
のり、ＳＩは用途の拡大に伴い多種多様となっているが
、これらＫそれぞれ合せたパッケージを製作することは
コストの点で問題があり、各棹サイズのチップに対応で
きる大きなキャビティを持つパッケージにｉｌ＞、 ＄
化することが望ましい。特にリピート・インライン・タ
イプ等の多ビンｔラミックパッケージでは構造が比較的
被雑で製造コストも大きいのでＳ準化が強く望まれる。Recent LSIs have become more multi-functional, have larger capacities, and have an increased number of lead terminals, but advances in microfabrication technology have made it possible to reduce the chip size. Such a small size,
For multi-terminal chips, if you use a ceramic package that matches the size of the semiconductor chip as in the past, the gap between the bonding pads will not be large.P1 raw ceramic sheet (
The manufacturing method of laminated ceramic packages, in which a conductive path pattern is formed on a green sheet and then stacked and fired, poses major problems such as the positional density of bonding pads and the difficulty in manufacturing fine patterns. In addition, glue and SI have recently become more diverse as their uses have expanded, but manufacturing a package that combines each of these K is problematic in terms of cost, and a large cavity that can accommodate chips of each rod size is required. In the package you have>, $
It is desirable to In particular, in multi-bin tramic packages such as repeat in-line type packages, the structure is relatively complex and the manufacturing cost is high, so S quasi-sizing is strongly desired.
（３）発明の目的
本発明の目的は各独サイズの半導体チップを一種類のパ
ッケージに搭載可能とし、パッケージの標準化を達成し
、併せて、前述の小型、多端子テップに対する問題を解
決するととＫある０（４）発明の構成
本発明はパッケージのキャビティ内に絶縁物枠体が配置
され、該キャビティ上で、且つ、該絶縁物枠体の内部に
半導体チップが配置され、該絶縁物枠体の表面には複数
の導電路が形成され、骸導電路の一端と核半導体チップ
のボンデングパッドとがワイヤーボンデンされ、駄導を
路の他端と該パッケージのボンデングパッドとがワイヤ
ーボンデングされている半導体装置である。(3) Purpose of the Invention The purpose of the present invention is to enable semiconductor chips of different sizes to be mounted in one type of package, to achieve package standardization, and to solve the aforementioned problems with small, multi-terminal chips. K0(4) Structure of the Invention The present invention includes an insulating frame disposed within a cavity of a package, a semiconductor chip disposed on the cavity and inside the insulating frame, and a semiconductor chip disposed within the insulating frame. A plurality of conductive paths are formed on the surface of the body, one end of the conductive path and the bonding pad of the nuclear semiconductor chip are wire bonded, and the other end of the conductive path and the bonding pad of the package are wire bonded. This is a semiconductor device that has been damaged.
（５）扼明の実施例
、第２図（ａ）は本発明の一実施例を示す平面囚であり
、（ｂ）は同実施例のＡ−１１１面図である。セラミッ
クパッケージ２のキャビティ３の中央部に半導体テップ
ｌが通常の技術で＃ＬＪｉ、固定され、該半導体チップ
と前記キャビティの外側端との間に絶ｌ／ＪＬ′ＪＩｌ
ｌＪ枠体６が配置されている。本実施例の絶縁物枠体は
粉末整形と焼成によって形成されたセラミック枠体であ
り、パッケージへの固定は低融点ガラスによって加熱接
着されている。但し、このセラミック枠体の製法および
パッケージへの固定方法は前述の方法に限定するもので
はなく、生セラミ、クシート（グリーンシート）をプレ
ス加工で整形し、焼成しても良く、固定方法としてはエ
ポキシ系の接Ｎ剤のような耐熱性の樹脂で接着してもよ
く、また、セラミック枠体とパッケージの両面をメタラ
イズし、Ａｕ−８ｉの共晶合金によって加３−
熱接着してもよい。(5) Embodiment of the present invention, FIG. 2(a) is a plan view showing an embodiment of the present invention, and FIG. 2(b) is a view on A-111 of the same embodiment. A semiconductor chip l is fixed #LJi in the center of the cavity 3 of the ceramic package 2 by a conventional technique, and there is no gap l/JL'JIl between the semiconductor chip and the outer edge of the cavity.
An lJ frame body 6 is arranged. The insulator frame of this embodiment is a ceramic frame formed by powder shaping and firing, and is fixed to the package by heat bonding with low melting point glass. However, the manufacturing method of this ceramic frame and the method of fixing it to the package are not limited to the above-mentioned method; raw ceramic or kusheet (green sheet) may be shaped by press processing and fired; It may be bonded with a heat-resistant resin such as an epoxy N-contact agent, or it may be bonded by metallizing both sides of the ceramic frame and the package and heat bonding with a eutectic alloy of Au-8i. .
セラミック枠体の上面には放射状に複数の導電路７が形
成されているが、これは通常のアルミニウムの真空蒸着
とフォトエツチング技術によって形成される。この場合
、セラミック枠体の内側の導電路の間隔は一般に狭くな
るが、フォトエツチング技術を使っているので充分な＊
ｉの導電路パターンが形成可能である。A plurality of conductive paths 7 are formed radially on the upper surface of the ceramic frame, and these are formed by conventional aluminum vacuum deposition and photoetching techniques. In this case, the spacing between the conductive paths inside the ceramic frame is generally narrower, but since photo-etching technology is used, sufficient *
i conductive path pattern can be formed.
更に前記導電路７の一端と半導体チップのボンデングパ
ッド４とがＡｔワイヤーによってボンデングされ、導電
路７の他端とパッケージのボンデングパッド５とがＡｔ
ワイヤーまたはＡｕワイヤーによってボンデングされて
いる。Further, one end of the conductive path 7 and the bonding pad 4 of the semiconductor chip are bonded with an At wire, and the other end of the conductive path 7 and the bonding pad 5 of the package are bonded with an At wire.
Bonded with wire or Au wire.
第３図は前述（第２図）の実施例を一部変更した実施例
を示す部分的断面図である。絶縁物枠体６（セラミック
枠体）の上にＴ１またはＷまたはＮｉの真空蒸着膜８が
形成され、その上に、一方はＡｔの真空蒸着膜９が、ま
た、他方はＡｕの真空蒸着膜またはＡｕのメッキ膜４０
が形成されている。使用するボンデングワイヤーは、半
導体チップの４−
ボンデングパッド４との間がＭでアシ、パッケージのボ
ンデングパッド５との間がＡｕである。一般に半導体チ
ップのボンデングパッド４は紅で形成され、パッケージ
のボンデングパッド５はＡｕメッキで形成されているの
で上記の構成によれば、ＡｕパッドとＡｔワイヤーまた
はＡｔバッドとＡｕワイヤーのようなＡｔとＡｕのボン
デング部はなく、両者の金属の合金化によるオープン障
害や、導電性劣化の障害は起らず、高信頼性のボンデン
グが形成される。FIG. 3 is a partial sectional view showing an embodiment that is a partial modification of the embodiment described above (FIG. 2). A vacuum-deposited film 8 of T1, W, or Ni is formed on the insulator frame 6 (ceramic frame), and on top of that, a vacuum-deposited film 9 of At on one side and a vacuum-deposited film of Au on the other. Or Au plating film 40
is formed. The bonding wire used is M reed between the 4-bonding pad 4 of the semiconductor chip, and Au between the bonding pad 5 of the package. Generally, the bonding pad 4 of a semiconductor chip is formed of red, and the bonding pad 5 of a package is formed of Au plating. There is no bonding part between At and Au, and there is no open failure due to alloying of the two metals or failure due to conductivity deterioration, and a highly reliable bond is formed.
第４図は他の実施例を示す部分的断面図である。FIG. 4 is a partial sectional view showing another embodiment.
本実施例は絶縁物枠体としてポリイミドフィルム枠体１
１を使用し、金メッキを施こした銅箔をパターンニング
して導電路１２としている。この場合にはポリイミドフ
ィルムが一般に薄いのでボンデング位置に段差を生じ、
また、接着には樹脂系接着剤を使用するので後工程での
加熱に制限が加えられるが、低コストで本発明の主旨を
実施することが可能である。In this example, a polyimide film frame 1 is used as an insulator frame.
1 is used, and a conductive path 12 is formed by patterning a gold-plated copper foil. In this case, since the polyimide film is generally thin, there will be a step at the bonding position.
Furthermore, since a resin adhesive is used for bonding, heating in subsequent steps is limited, but the gist of the present invention can be carried out at low cost.
（６）発明の効果
本発明によれば各種サイズの半導体チップを同一のパッ
ケージに搭載することが出来、パッケージの標準化によ
る半導体装置のコストダウンが可能である。また、小形
、多端子チップに対して、通常のセラミ、クパククージ
の製法を用いても、ボンデングパッド間隔の狭ますぎに
よるｈ度の問題を回避することが可能である。(6) Effects of the Invention According to the present invention, semiconductor chips of various sizes can be mounted in the same package, and the cost of semiconductor devices can be reduced by standardizing the package. In addition, even if a normal ceramic or Kupakuji manufacturing method is used for a small, multi-terminal chip, it is possible to avoid the problem of h degree due to too narrow bonding pad spacing.
第１図は従来例を示し、第２図は本発明の一実施例を示
し、第３図は第２図の実施例の一部を変更した実施例を
示し、第４図は他の実施例を示している。ここで１は半
導体チップ、２はセラミックパッケージ、３はパッケー
ジのキャビティ、４は半導体チップのボンデングパッド
、５Ｆｉパツケージのボンデングパッド、６は絶縁物枠
体、７は導電路、８は導電路下層のＴ１また／ｌ′ｉＷ
またはＮｉの真空蒸着膜、９は導電路上層のＡｔ真空蒸
着膜、１０は導電路上層のＡｕ真空蒸着またはメッキ膜
、１１はポリイミドフィルム枠体、１２はＡｕメッキ銅
箔４″ｆｔ路である。
７−
第 １ 図
第 ２ 閃Fig. 1 shows a conventional example, Fig. 2 shows an embodiment of the present invention, Fig. 3 shows an embodiment in which a part of the embodiment of Fig. 2 is changed, and Fig. 4 shows another embodiment. An example is shown. Here, 1 is a semiconductor chip, 2 is a ceramic package, 3 is a cavity of the package, 4 is a bonding pad of the semiconductor chip, 5 is a bonding pad of the Fi package, 6 is an insulator frame, 7 is a conductive path, and 8 is a conductive path Lower layer T1 or /l'iW
or a Ni vacuum-deposited film, 9 is an At vacuum-deposited film on the conductive upper layer, 10 is an Au vacuum-deposited or plated film on the conductive upper layer, 11 is a polyimide film frame, and 12 is an Au-plated copper foil 4″ foot path. 7- Figure 1, 2nd Flash
Claims (1)
キャビティ上で、且つ、該絶縁物枠体の内部に半導体チ
ップが配置され、該絶縁物枠体の表面には複数の導電路
が形成され、該導電路の一端と該半導体チップのボンデ
ングパッドとがワイヤーボンデンされ、該導電路の他端
と該パッケージのボンデングパッドとがワイヤーボンデ
ングされていることを特徴とする半導体装置。An insulator frame is disposed within a cavity of the package, a semiconductor chip is disposed on the cavity and inside the insulator frame, and a plurality of conductive paths are formed on the surface of the insulator frame. A semiconductor device, wherein one end of the conductive path and a bonding pad of the semiconductor chip are wire-bonded, and the other end of the conductive path and a bonding pad of the package are wire-bonded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57093888A JPS58210650A (en) | 1982-06-01 | 1982-06-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57093888A JPS58210650A (en) | 1982-06-01 | 1982-06-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58210650A true JPS58210650A (en) | 1983-12-07 |
Family
ID=14095014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57093888A Pending JPS58210650A (en) | 1982-06-01 | 1982-06-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58210650A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2564244A1 (en) * | 1984-05-14 | 1985-11-15 | Gigabit Logic Inc | MOUNTING STRUCTURE FOR FAST INTEGRATED CIRCUITS |
| US4754317A (en) * | 1986-04-28 | 1988-06-28 | Monolithic Memories, Inc. | Integrated circuit die-to-lead frame interconnection assembly and method |
| US4796080A (en) * | 1987-07-23 | 1989-01-03 | Fairchild Camera And Instrument Corporation | Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate |
| US4903114A (en) * | 1985-10-01 | 1990-02-20 | Fujitsu Limited | Resin-molded semiconductor |
| JPH03105935A (en) * | 1989-09-19 | 1991-05-02 | Nec Kyushu Ltd | Ceramic package for semiconductor device |
| US5365409A (en) * | 1993-02-20 | 1994-11-15 | Vlsi Technology, Inc. | Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe |
| US6232561B1 (en) * | 1997-01-31 | 2001-05-15 | Robert Bosch Gmbh | Process for producing wire connections on an electronic component assembly carrier made by the process |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108369A (en) * | 1977-03-04 | 1978-09-21 | Hitachi Ltd | Electronic components |
| JPS56120138A (en) * | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Semiconductor device and its manufacture |
-
1982
- 1982-06-01 JP JP57093888A patent/JPS58210650A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108369A (en) * | 1977-03-04 | 1978-09-21 | Hitachi Ltd | Electronic components |
| JPS56120138A (en) * | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Semiconductor device and its manufacture |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2564244A1 (en) * | 1984-05-14 | 1985-11-15 | Gigabit Logic Inc | MOUNTING STRUCTURE FOR FAST INTEGRATED CIRCUITS |
| US4903114A (en) * | 1985-10-01 | 1990-02-20 | Fujitsu Limited | Resin-molded semiconductor |
| US4754317A (en) * | 1986-04-28 | 1988-06-28 | Monolithic Memories, Inc. | Integrated circuit die-to-lead frame interconnection assembly and method |
| US4796080A (en) * | 1987-07-23 | 1989-01-03 | Fairchild Camera And Instrument Corporation | Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate |
| JPH03105935A (en) * | 1989-09-19 | 1991-05-02 | Nec Kyushu Ltd | Ceramic package for semiconductor device |
| US5365409A (en) * | 1993-02-20 | 1994-11-15 | Vlsi Technology, Inc. | Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe |
| US6232561B1 (en) * | 1997-01-31 | 2001-05-15 | Robert Bosch Gmbh | Process for producing wire connections on an electronic component assembly carrier made by the process |
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