JPS6215850A - Multi-chip package substrate - Google Patents

Abstract

PURPOSE:To provide low impedance of 50-100OMEGA as the characteristic impedance of the microstrip lines of a multi-chip package substrate even if the width of the line is miniaturized, by providing a very thin silicon oxide film (or silicon nitride film) on a silicon substrate, whose impurity concentration is very high, and using the silicon oxide film as a dielectric material. CONSTITUTION:On a silicon substrate 13, a silicon oxide film 15, whose thickness is, e.g., 1-5mum, is provided. A wiring pattern 21 including microstrip lines 17 and wirings 19 are provided on the silicon oxide film 15. The microstrip lines 17 comprise suitable metal material. The wiring 19 is wider than the microstrip line 17 for external terminals, power source lines and the like. A part of the silicon oxide film 15 is removed in order to reduce grounding inductance, and a through hole 13 reaching the silicon substrate 13 is provided, in a package substrate 11. The desired circuit part can be grounded to the silicon substrate through said through hole 23 are required.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a multi-chip package substrate for mounting ultra-high-speed devices (semiconductor chips) made of silicon or compound semiconductors.

(Prior Art) Multi-chip package substrates (hereinafter sometimes referred to as package substrates) of various structures have been proposed. Such package substrates are described, for example, in the literature (Proceedings of the Custom Ingredients).
Circuits Con7 x L'ance (Praceedi
ng af the GuStom Integrat
ed C1rcuits Conference)
, 1983, p.

142-146).

Such conventional package substrates are well known, but as follows:
11JtFi will explain.

First, as a substrate, a ceramic substrate with a thickness of 0.6 to 1.0 mm, a Teflon (trade name of DuPont, USA) resin substrate with a thickness of 0.8 to 1.6 mm, or a resin substrate with a thickness of 0.8 to 1.6 mm are used. Using a glass epoxy substrate, the substrate 1 is coated with Cr,
A wiring button including external connection terminals, a power supply line, and a microstrip line for transmitting high-speed signals is formed using a desired material such as NiCr, Au, or Cu. Further, if necessary, a through hole is provided in this substrate to reach the opposite side (referred to as the back surface) from the substrate surface on which the wiring pattern is formed. Further, on this back surface, generally, an earth line made of a metal thin film as described above is formed.

A package substrate having such a structure is usually fixed to a support for the purpose of reinforcing the substrate and dissipating heat from the device.

The characteristic impedance Zo of a microstrip line (hereinafter sometimes referred to as F line) can be found in the literature (edited by the Japan Microelectronics Association, "IC Mounting Technology J (19)
84-2-20) According to the formula described in Kogyo Kenkyukai p, 202), ZO=377/(W/h) G r
[Dl, 735 εr 001'X (W/h) 0.
It is given by 8361 (Ω). Here, h is the thickness of the dielectric substrate (m), W is the width of the microstrip line (ffi), and (r is the dielectric constant of the dielectric substrate. Therefore, the characteristic impedance Zo is the thickness of the dielectric The thicker the dielectric, and the smaller the permittivity of the dielectric, the higher the resistance becomes.Also, the narrower the line width of the microstrip line provided on the dielectric, the greater the characteristic impedance of this line. In package substrates, the substrate used is a dielectric material, which is very thick, and the line width formed on the substrate cannot be made very wide due to restrictions on mounting density, so the characteristics of the microstrip line are The impedance becomes 200Ω or more.

(Problem to be solved by the invention) When ultra-high-speed devices such as gallium arsenide ICs that handle ultra-high-speed signals and silicon bipolar elements are mounted on such conventional multi-chip package substrates, microstrip The characteristic impedance of the line becomes a load. In order to faithfully transmit high-speed signals, the characteristic impedance of the line used for signal transmission must be between 50 and 10.
It needs to be 0Ω. Therefore, if the characteristic impedance of a conventional line is 200Ω or more, an impedance mismatch occurs between the device and the line. For this reason, there is a problem in that the signal cannot be accurately transmitted due to loss due to signal reflection at the mismatched portion and distortion of the signal waveform.

For example, in the case of gallium arsenide ICs and silicon bipolar devices, when these ICs and devices are used for ultra-high speeds, the design rules are less than IJLm, and the line widths of high-speed signal lines inside the ICs and devices are as fine as 2 to 4 gm. Become. Therefore, in order to construct a microstrip line with a characteristic impedance of 50Ω, it is necessary to create a microstrip line with a line width on the order of gm, similar to the line width of a high-speed signal line of 2 to 4 pm, depending on the permittivity of the dielectric material. need to be formed. By forming such fine lines on a conventional package substrate, it was impossible to realize a microstrip line with a characteristic impedance of 50Ω.

An object of the present invention is to provide a multi-chip package substrate that can maintain a low characteristic impedance of 50 to 100 Ω even if the line width of the microstrip line on the multi-chip package substrate is made fine. .

(Means for Solving the Problems) In order to achieve this object, according to the present invention, in a multi-chip package substrate for ultra-high-speed device mounting, the multi-chip package is highly doped to have conductivity. A silicon substrate doped with impurities, a silicon oxide film or silicon nitride film formed on the surface of this silicon substrate, a through hole formed in this silicon oxide film or silicon nitride film, and a through hole formed in this silicon oxide film or silicon nitride film. and a wiring pattern having a microstrip line.

(Function) According to such a configuration, the conductive silicon substrate functions as the substrate of the multi-chip package substrate, and the silicon oxide film or silicon nitride film functions as the dielectric. Furthermore, since this silicon oxide film or silicon nitride film can be formed with a very thin film thickness, the thickness of the dielectric material underlying the wiring pattern can be made very thin.

(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2. It should be noted that these drawings are merely schematic illustrations to facilitate understanding of the present invention, and the shapes, dimensions, and arrangement relationships are not limited to the illustrated examples.

FIG. 1 is a sectional view showing an embodiment of the multi-chip package substrate ti of the present invention. The structure of this package substrate 11 will be explained with reference to this figure.

In the figure, reference numeral 13 indicates a p-type silicon substrate with a high carrier concentration (of course, an n-type silicon substrate is also acceptable). Impurities are added so that the resistivity is 0.1Ω or less. This silicon substrate 1
3): For example, silicon oxide 71415 with a thickness of 1 to 5 μm is provided by a suitable means. On this silicon oxide M15, a microstrip line is formed using a suitable metal material as before! 7, and a wiring pattern 21 including wiring 18 wider than the microstrip line such as an external connection terminal or a power supply line. Furthermore, this package substrate 11 has a through hole 23 that reaches the silicon substrate 13 by removing a portion of the silicon oxide film 15 in order to reduce grounding inductance.
A desired circuit portion can be grounded to the silicon substrate 13 through this through hole 23.

In the package substrate 11 having such a structure, silicon oxide II! Since 15 is a dielectric material, the thickness of the dielectric material made of silicon oxide film 15 is extremely thin compared to the thickness of dielectric materials such as ceramics used in conventional package substrates.

Below, a method for manufacturing the multi-chip package substrate 11 of the present invention will be explained.

First, regarding the method of forming the silicon oxide film 15,
1 silicon substrate! A silicon oxide film 15 is formed on the surface of the silicon oxide film 3 by, for example, vapor phase growth, which is a semiconductor manufacturing technique. Alternatively, a silicon dioxide layer may be formed on the silicon substrate 13 by performing thermal oxidation treatment on the surface of the silicon substrate.

The thickness of this silicon oxide film 15 is such that this film has good characteristics as an insulating film.

Further, the wiring pattern 21 to be formed on the silicon oxide film 15, in particular, the line width of the microstrip line required from the viewpoint of packaging density and the characteristic impedance required for this line, are taken into consideration to select an appropriate film. Form it so that it is thick.

Next, using photoetching technology, the second silicon oxide I+! A through hole 23 is formed at a desired location of the silicon oxide film 15 to reach the silicon substrate 13 from the surface of the silicon oxide film 15 .

Next, on the silicon oxide film 15 and the portion of the silicon substrate 13 exposed by the through hole 23, a thin metal film of NiCr, Au, etc., similar to the conventional method, is formed by vacuum evaporation or other suitable method. Subsequently, this metal thin film is processed by a suitable method such as photoetching technique to form a wiring pattern 21.

At this time, the line width of the microstrip line 17 that transmits high-speed signals is such that the characteristic impedance of this line 17 is 5.
The line width is formed to have a value of 0-100Ω. Also, the width is wide! The line width of the ff119 is determined in consideration of the current capacity and voltage drop required in each portion, and the size of the external connection terminal portion is determined based on the restrictions of the bonding conditions, and is formed according to the respective dimensions.

Note that the effects of the present invention can also be achieved by using a silicon nitride film instead of the silicon oxide film formed in this embodiment. In this case, the silicon nitride film may be formed by a suitable method such as a vapor phase growth method.

FIG. 2 is a plan view showing an example of a state in which a semiconductor chip 25 is mounted on the multi-chip package board 11 of the present invention in order to better understand the multi-chip package board 11 of the present invention.

The method for mounting the semiconductor chip 25 on the multi-chip package substrate 11 is, for example, the conventional Fouri method.
This may be done by the bump pounding method.

It goes without saying that one or more ultra-high-speed devices can be mounted on this multi-chip package substrate 11. This multi-chip package substrate is also suitable for use as a mounting substrate for ordinary semiconductor devices.

FIG. 3 shows a support 2 made of alumina or the like for the purpose of reinforcing the board and dissipating heat generated by the device.
7 is shown. In this case, after the multi-chip package substrate 11 is die-bonded to the support body 27, wire bonding is performed using a gold wire 29 between the external connection terminal portion provided on the package substrate 11 and the support body 27. In addition to this example, for example, after fixing this multi-chip pan cage board 11 to a frame having terminals,
A method of supporting by resin molding is also considered.

(Effects of the Invention) I As is clear from the above description, according to the multi-chip package substrate of the present invention, a very thin silicon oxide film (or silicon nitride film) is coated on a silicon substrate with a high impurity concentration. This silicon oxide film is used as a dielectric. Therefore, while the thickness of the dielectric in the conventional package substrate is 0.6 to 1.6 mm, the thickness of the dielectric in the package substrate of the present invention is extremely thin, at 1 to 5 μm, even if we quote the values of the embodiments. For this reason,
&1@ of the microstrip line formed on this silicon oxide film is connected to the fine wiring line @11- inside the semiconductor chip.
Even if it is about the same as 1 OJL, the characteristic impedance of this microstrip line can be set to 50 to 100 Ω.

Furthermore, forming a silicon oxide film or a silicon nitride film on a silicon substrate, and forming through holes and wiring patterns in a silicon oxide film or a silicon nitride film can be easily performed using conventional methods. In addition, since the reliability of the surface processing of the silicon substrate used as the substrate has been proven by semiconductor technology, it is possible to form a fine circuit pattern on the surface of the silicon substrate.

Because of this, it has a low characteristic impedance.

Moreover, a multi-chip package substrate with high packaging density can be easily provided.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing an embodiment of the multi-chip package board of the present invention, Fig. 2 is a plan view showing a state in which semiconductor chips are mounted on the multi-chip package board of the invention, and Fig. 3 is a cross-sectional view showing an embodiment of the multi-chip package board of the present invention. FIG. 3 is a cross-sectional view showing a multi-chip package substrate mounted on a support body. 11...Multi-chip package substrate 13...Conductive silicon substrate 15...Silicon oxide film 17...Microstrip line 19...Wide wiring 21...Wiring button 23...Thru -Hall 25...Ultra high speed device (semiconductor chip) 27...
Support body 29...gold wire.

Claims (1)

[Claims] (1) A multi-chip package substrate for semiconductor chip mounting includes a silicon substrate doped with impurities at a high concentration so as to have conductivity, a silicon oxide film or silicon nitride film formed on the surface of the silicon substrate, and the silicon substrate. A multi-chip package substrate comprising a through hole provided in an oxide film or a silicon nitride film, and a wiring pattern formed in the silicon oxide film or silicon nitride film and having a microstrip line.