JPH0464467B2 - - Google Patents

Abstract

PURPOSE:To provide low impedance of 50-100OMEGA as the characteristic impedance of the microstrip lines of a multi-chip package substrate even if the width of the line is miniaturized, by providing a very thin silicon oxide film (or silicon nitride film) on a silicon substrate, whose impurity concentration is very high, and using the silicon oxide film as a dielectric material. CONSTITUTION:On a silicon substrate 13, a silicon oxide film 15, whose thickness is, e.g., 1-5mum, is provided. A wiring pattern 21 including microstrip lines 17 and wirings 19 are provided on the silicon oxide film 15. The microstrip lines 17 comprise suitable metal material. The wiring 19 is wider than the microstrip line 17 for external terminals, power source lines and the like. A part of the silicon oxide film 15 is removed in order to reduce grounding inductance, and a through hole 13 reaching the silicon substrate 13 is provided, in a package substrate 11. The desired circuit part can be grounded to the silicon substrate through said through hole 23 are required.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a multi-chip package substrate for mounting ultra-high-speed devices (semiconductor chips) made of silicon or compound semiconductors.

(Prior Art) Multi-chip package substrates (hereinafter sometimes referred to as package substrates) of various structures have been proposed. Such package boards are described, for example, in the literature (Procedures of the
Proceeding of the Custom
Integrated Circuits Conference), 1983, p.142
~146).

Such conventional package substrates are well known and will be briefly described below.

First, as a substrate, a ceramic substrate with a thickness of 0.6 to 1.0 mm, a Teflon (trade name of DuPont, USA) resin substrate with a thickness of 0.8 to 1.6 mm, or a substrate with a thickness of 0.8 to 1.6 mm.
A glass epoxy substrate with a thickness of A wiring pattern including a pull line is formed. In addition, if necessary, from the substrate surface on which the wiring pattern is formed, to the surface opposite to this substrate surface (referred to as the back surface).
A through hole is provided to reach the Further, on this back surface, generally, an earth line made of a metal thin film as described above is formed.

A package board with this type of structure usually has a built-in material for the purpose of reinforcing the board and dissipating heat from the device.
fixed to a support.

The characteristic impedance Z ₀ of a microstrip line (hereinafter sometimes referred to as a line) is given in the literature (edited by the Japan Microelectronics Association, "IC Mounting Technology" (February 20, 1984), Industrial Research Committee, p. 202). According to the stated formula, Z ₀ =377/(w/h)ε _r [1+1.735 ε _r ^-0.074 ×
(w/h) ^-0.836 ] (Ω). Here, h is the thickness m of the dielectric substrate, w is the width m of the microstrip line, and ε _r is the dielectric constant of the dielectric substrate. Therefore, the characteristic impedance Z ₀ increases as the thickness of the dielectric increases.
Further, the smaller the dielectric constant of the dielectric, the larger it becomes.
Furthermore, the narrower the line width of the microstrip line provided on the dielectric, the greater the characteristic impedance of this line. In conventional package boards, the board used is a dielectric material, which is very thick, and the line width formed on the board cannot be made very wide due to restrictions on packaging density.
The characteristic impedance of the microstrip line is
It becomes over 200Ω.

(Problems to be Solved by the Invention) When ultra-high-speed devices such as gallium arsenide ICs that handle ultra-high-speed signals and silicon bipolar elements are mounted on such conventional multi-chip package substrates, micro-stroll The characteristic impedance of the lip line becomes a load. In order to faithfully transmit high-speed signals, the characteristic impedance of the line used for signal transmission must be 50 to 100Ω. Therefore, when a conventional line has a characteristic impedance of 200Ω or more, impedance mismatch occurs between the device and the line. For this reason, there is a problem in that signals cannot be transmitted accurately due to loss due to reflection of signals at mismatched portions and distortion of signal waveforms.

For example, in the case of gallium arsenide ICs and silicon bipolar devices, when these ICs and devices are used for ultra-high speed applications, the design rule is 1 μm or less, and
The line width of the high-speed signal line inside the IC and element is also 2~
It becomes as fine as 4μm. Therefore, in order to construct a microstrip line with a characteristic impedance of 50Ω, it is necessary to have a line width on the μm order, similar to the line width of high-speed signal lines of 2 to 4 μm, depending on the permittivity of the dielectric material. It is necessary to form a microstrip line.
By forming such fine lines on a conventional package substrate, it was impossible to realize a microstrip line with a characteristic impedance of 50Ω.

An object of the present invention is to provide a multichip package board that can maintain a low characteristic impedance of 50 to 100Ω even if the line width of the microstrip line on the multichip package board is made fine. It is in.

(Means for Solving the Problems) In order to achieve this object, according to the present invention, in a multi-chip package substrate for ultra-high-speed device mounting, the multi-chip package is highly concentrated to have conductivity. a silicon substrate doped with impurities,
It has a silicon oxide film or silicon nitride film formed on the surface of this silicon substrate, a through hole provided in this silicon oxide film or silicon nitride film, and a microstrip line formed in this silicon oxide film or silicon nitride film. It is characterized by including a wiring pattern.

(Function) According to this configuration, the conductive silicon substrate functions as the substrate of the multi-chip package substrate, and the silicon oxide film or silicon nitride film functions as the dielectric. Furthermore, since this silicon oxide film or silicon nitride film can be formed with a very thin film thickness, the thickness of the dielectric material underlying the wiring pattern can be made very thin.

(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2. Note that these drawings are merely shown schematically to the extent that the present invention can be understood, and the shapes, dimensions, and arrangement relationships are not limited to the illustrated examples.

FIG. 1 is a sectional view showing an embodiment of a multi-chip package substrate 11 of the present invention. The structure of this package substrate 11 will be explained with reference to this figure.

In the figure, reference numeral 13 indicates a p-type silicon substrate with a high carrier concentration (of course, an n-type silicon substrate may also be used). Impurities are added so that the resistivity is 0.1Ω or less. A silicon oxide film 15 having a thickness of, for example, 1 to 5 μm is provided on this silicon substrate 13 by suitable means. On this silicon oxide film 15, a microstrip line 17 and wiring lines 1 wider than the microstrip line such as external connection terminals and power lines are formed using a suitable metal material as in the past.
A wiring pattern 21 including 9 is provided. Furthermore, in order to reduce grounding inductance, this package substrate 11 has a through hole 23 that reaches the silicon substrate 13 by removing a portion of the silicon oxide film 15. If necessary, a desired circuit portion can be inserted into this through hole 23. It can be grounded to the silicon substrate 13 via the through hole 23.

In the package substrate 11 having such a structure, since the silicon oxide film 15 is used as a dielectric, the silicon oxide film 15 is thicker than the dielectric material such as ceramic used in conventional package substrates.
The thickness of the dielectric material made of is very thin.

The method for manufacturing the multi-chip package substrate 11 of the present invention will be explained below.

First, regarding the method of forming the silicon oxide film 15, the silicon oxide film 15 is formed on the surface of the silicon substrate 13 by, for example, vapor phase growth, which is a semiconductor manufacturing technology.
form 5. Alternatively, thermal oxidation treatment is performed on the silicon substrate surface to form a silicon dioxide layer on the silicon substrate 1.
3 may be formed.

The thickness of this silicon oxide film 15 is such that this film has good characteristics as an insulating film. Furthermore, the wiring pattern 21 to be formed on the silicon oxide film 15 is appropriately designed, taking into account the line width of the microstrip line required from the viewpoint of packaging density and the characteristic impedance required for this line. The film is formed to have a film thickness of

Next, a through hole 23 reaching from the surface of the silicon oxide film 15 to the silicon substrate 13 is formed at a desired location of the silicon oxide film 15 by photo-etching technology.

Next, on the silicon oxide film 15 and the portion of the silicon substrate 13 exposed through the through hole 23, a thin metal film of NiCr, Au, etc., similar to the conventional method, is formed by vacuum evaporation or other suitable method. Subsequently, this metal thin film is processed by a suitable method such as photoetching technique to form a wiring pattern 21. At this time, the line width of the microstrip line 17 for transmitting high-speed signals is formed to such a line width that the characteristic impedance of this line 17 becomes a value of 50 to 100 Ω. In addition, the line width of the wide wiring 19 is determined by considering the current capacity and voltage drop required in each part, and the size of the external connection terminal part is determined based on the restrictions of bonding conditions, and is determined according to each dimension. Form.

Note that the effects of the present invention can also be achieved by using a silicon nitride film instead of the silicon oxide film formed in this embodiment. In this case, the silicon nitride film may be formed by a suitable method such as a vapor phase growth method.

FIG. 2 is a plan view showing an example of a state in which a semiconductor chip 25 is mounted on the multi-chip package board 11 of the present invention in order to better understand the multi-chip package board 11 of the present invention.

The semiconductor chip 25 may be mounted on the multi-chip package substrate 11 by, for example, the conventional flip-chip bonding method.

It goes without saying that one or more ultra-high speed devices can be mounted on this multi-chip package substrate 11. This multi-chip package substrate is also suitable for use as a mounting substrate for ordinary semiconductor devices.

FIG. 3 shows a state in which a multi-chip package board 11 on which ultra-high-speed devices are mounted is fixed to a support body 27 made of alumina or the like for the purpose of reinforcing the board and dissipating heat generated by the devices.
In this case, after die bonding the multi-chip package board 11 to the support 27, wire bonding is performed using a gold wire 29 between the external connection terminal portion provided on the package board 11 and the support 27. In addition to this example, for example, a method may be considered in which the multi-chip package board 11 is fixed to a frame having terminals and then supported by resin molding.

(Effects of the Invention) As is clear from the above description, the multi-chip package substrate of the present invention has a very thin silicon oxide film (or silicon nitride film) on a silicon substrate with a high impurity concentration. This silicon oxide film is used as a dielectric. Therefore, while the thickness of the dielectric in the conventional package substrate is 0.6 to 1.6 mm, the thickness of the dielectric in the package substrate of this invention is 1.
Very thin at ~5 μm. For this reason, the line width of the microstrip line formed on this silicon oxide film is reduced to 1 to 10 μm, which is the line width of the fine wiring inside the semiconductor chip.
The characteristic impedance of this microstrip line can be made to be 50 to 100 Ω even if the impedance is the same as that of 50 to 100 Ω.

Furthermore, forming a silicon oxide film or a silicon nitride film on a silicon substrate, and forming through holes and wiring patterns in a silicon oxide film or a silicon nitride film can be easily performed using conventional methods. In addition, since the reliability of the surface processing of the silicon substrate used as the substrate has been proven by semiconductor technology, it is possible to form a fine circuit pattern on the surface of the silicon substrate.

Because of this, it has a low characteristic impedance,
Moreover, a multi-chip package board with high packaging density can be easily provided.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the multi-chip package board of the present invention, FIG. 2 is a plan view showing a state in which semiconductor chips are mounted on the multi-chip package board of the present invention, and FIG. FIG. 3 is a cross-sectional view showing a multi-chip package board mounted on a support. 11...Multi-chip package board, 13...
... conductive silicon substrate, 15 ... silicon oxide film, 17 ... microstrip line, 1
9...Wide wiring, 21...Wiring pattern, 23...
...Through hole, 25...Ultra high-speed device (semiconductor chip), 27...Support, 29...Gold wire.

Claims (1)

[Scope of Claims] 1. A multi-chip package substrate for mounting semiconductor chips, comprising: a silicon substrate doped with impurities at a high concentration so as to have conductivity; and a silicon oxide film or silicon nitride film formed on the surface of the silicon substrate. A multi-chip package substrate comprising: a through hole provided in the silicon oxide film or silicon nitride film; and a wiring pattern formed in the silicon oxide film or silicon nitride film and having a microstrip line.