GB2144907A - Mounting integrated circuit devices - Google Patents

Mounting integrated circuit devices Download PDF

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Publication number
GB2144907A
GB2144907A GB8321392A GB8321392A GB2144907A GB 2144907 A GB2144907 A GB 2144907A GB 8321392 A GB8321392 A GB 8321392A GB 8321392 A GB8321392 A GB 8321392A GB 2144907 A GB2144907 A GB 2144907A
Authority
GB
United Kingdom
Prior art keywords
substrate
circuits
integrated circuits
connection areas
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB8321392A
Other versions
GB8321392D0 (en
Inventor
Francis Brian Robinson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB8321392A priority Critical patent/GB2144907A/en
Publication of GB8321392D0 publication Critical patent/GB8321392D0/en
Publication of GB2144907A publication Critical patent/GB2144907A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A method of mounting and interconnecting electronic integrated circuits 4 comprises the steps of preparing a substrate 10 of substantially insulating semiconductor material eg Si, forming metallised interconnection conductor patterns 11 on said substrate, said patterns having surface connection areas 11b, attaching one or more electronic integrated circuits 4 to the substrate whereby the circuits make electrical contacts with certain of said connection areas, mounting the semiconductor substrate on a printed circuit structure or carrier 12 and forming electrical connections between other surface connection areas 11b and the printed circuit or carrier. <IMAGE>

Description

SPECIFICATION Mounting integrated circuit devices This invention relates to the mounting and interconnection of integrated circuits.
Integrated circuits, either packaged or unpackaged (bare) "chips" are usually mounted on and interconncted by a printed circuit, e.g.
a metallised conductor pattern formed on an insulating substrate, a ceramic or porcelain coated metal. However, it is clear that the printed circuit and the integrated circuit are, in the electronics field at least, at almost opposite ends of the interconnection spectrum.
The chip on the one hand is an extremely advanced and well developed piece of technology which has evolved rapidly both with respect to its electrical capabilities and its physical state, i.e. reliability, cost etc. On the other hand the printed circuit, although recently of substantially higher quality and improved technology generally, remains only a moderately advanced extension of its former self. Certainly the materials available have improved and a wider range of board materials and track characteristics are now available.
Conceptually, however, the technology is the same. Efforts to bring the chip into a working relationship with the printed board (PCB) have resulted in a variety of holding, packaging and clamping devices among which are the dual in-line package, the flat pack, the quad in-line package, the automatically bonded tape and the ceramic and plastic carriers, to name a few.
A common feature of most of the known devices of this type lies in the fact that they serve primarily as a "size" interface between the chips and the PCB. In other words, the carrier, packaged chip, etc. all effectively increase the size of the chip to a level compatible with current PCB handling and production technology.
This approach is very convenient for established production facilities. It does not, however, advance the technology of integrated circuit handling and interconnection nor does it allow for a solution which might have an even greater reliability and cost advantage.
According to the present invention there is provided a method of mounting and interconnecting electronic integrated circuits comprising the steps of preparing a substrate of substantially insulating semiconductor material, forming metallised interconnection conductor patterns on said substrate, said patterns having surface connection areas and attaching electronic integrated circuits to the substrate, whereby the circuits make electrical contacts with certain of said connection areas and other connection areas are available for electrical connections to external circuitry.
According to one aspect of the invention there is provided an interconnection substrate for electronic circuits comprising a body of substantially insulating semiconductor material on which are formed metallised interconnection conductor patterns having connection areas whereby electronic circuits can be attached to the substrate with electrical connections to certain of the connection areas whilst others of the connection areas are available for electrical connections to external circuitry.
Embodiments of the invention will now be described with reference to the accompanying drawings, in which:~ Figure 1 illustrates a number of electronic integrated circuits mounted on and interconnected by a semiconductor substrate, Figure 2 illustrates an assembly of integrated circuits on a semiconductor substrate packaged in a carrier frame, and Figure 3 illustrates packaging of an assembly of electronic circuits on a substrate within a conformal coating of an embedding compound.
In the arrangement shown in Fig. 1 a number of integrated electronic circuit 'chips' 1-6 are shown soldered to an interconnecting substrate of semiconductor material 10. The term 'chip' is used to denote a single body of semiconductor material, e.g. silicon, in which there are formed so-called 'integrated' circuits.
Such circuits are formed by various wellknown techniques, such as diffusion, expitaxial growth, ion implantation etc. The chip usually has metallised conductor patterns on the surface by means of which various interconnections between circuits in the chip are made and to which connections with external circuitry can be made. Hitherto, as explained above, chips are commonly mounted on and connected to printed circuits.
To promote higher packaging densities and reduce stress, the chips in Fig. 1 are mounted on and interconnected by the substrate 10 which is made of a semiconductor material, e.g. silicon, having the same or similar physical characteristics as the semiconductor material of the chips. The substrate semiconductor material may be either high-resisitivity ptype or n-type material, or may even be intrinsically insulating pure material. Interconnecting conductor patterns 11 are formed on the surface of the substrate 10 using conventional integrared circuit technology, e.g. the deposition of aluminium conductive tracks.
The pattern 11 includes pad areas 1 lea which are aligned to allow connection with corresponding connection pad areas on the chips.
Further connection pad areas 1 1 b are provided to allow interconnection between the substrate 10 and a printed circuit board (not shown). The absence of electronic circuit elements formed in the substrate provides extra possibilities for improved deposition criteria and/or thicker connection pad areas. Such a structure also allows the integrated circuit designer to place input/output connection pad areas to suit more important criteria than those required by conventional wire bonding techniques.
Fig. 2 illustrates an assembly of chips 4, 5 etc on a silicon substrate 10 packaged into a carrier 12, which may itself be leaded or leadless. Connections between the substrate pad areas 11 b and the carrier are illustrated as wire bonds 13 but could equally well be by other conventional methods, such as lead frame. Additional pad areas can be incorporated to permit probe testing of the circuits once mounted.
Attachment of the integrated circuit chips is possible, using known technology. Solder 'bumps' may be provided on both the chips and the substrate so that when the solder is melted by the application of reflow heat surface tension in the molten solder accurately aligns the chips on the substrate. The use of either a tin/lead solder or an aluminium solder can be considered, the latter having the advantage of a lower melting point due to the small amount of silver included. Such an arrangement also improves the heat flow from the chips into the substrate to facilitate heat dissipation. Due to the fact that the integrated circuit chips and the substrate are of the same or similar materials the problems of differential expansion and contraction, as experienced in other chip mounting systems, are substantially eliminated.
The module thus formed is a fairly rugged entity and can be sealed into a package with a conformal coating of a suitable potting compound, as shown in Fig. 3. In this example the substrate 10 with its chips 4 etc is provided with leads 14 for subsequent attachment to a printed circuit board. The whole is then potted in a resin compound 15. The invention has the advantage that it uses proven technology and can be implemented using existing plant. Using the same materials and techniques as those used in chip production the substrates can be manufactured in sizes compatible with chip dimensions, thus achieving increases in circuit densities with a corresponding reduction in track density and/ or layer count.

Claims (13)

1. A method of mounting and interconnecting electronic integrated circuits comprising the steps of preparing a substrate of substantially insulating semiconductor material, forming metallised interconnection conductor patterns on said substrate, said patterns having surface connection areas and attaching electronic integrated circuits to the substrate, whereby the circuits make electrical contacts with certain of said connection areas and other connection areas are available for electrical connections to external circuitry.
2. A method according to claim 1 wherein the integrated circuits are attached to the substrate by soldering.
3. A method according to claim 2 wherein the integrated circuits or the substrate are provided with solder bumps so that when the solder is melted by the application of reflow heat surface tension in the molten solder automatically aligns the circuits on the substrate.
4. A method according to claim 1, 2 or 3 wherein the substrate is a silicon slice with aluminium conductive tracks.
5. A method according to claim 4 wherein the conductor patterns on the substrate include additional contact areas to permit probe testing of the circuits once mounted.
6. A method according to any preceding claim wherein the substrate is packaged into a carrier with interconnection between the substrate and the carrier being effected by wire bonds.
7. A method according to any one of claim 1-5 wherein the substrate is packaged into a lead frame carrier.
8. A method according to any one of claim 1-5 wherein the substrate is mounted on and electrically connected to a printed circuit structure.
9. A method according to any preceding claims wherein the substrate carrying the integrated circuits is sealed in a potting compound.
10. A method of mounting and interconnecting electronic integrated circuits substantially as described with reference to the accompanying drawings.
11. An interconnection substrate for electronic circuits comprising a body of substantially insulating semiconductor material on which are formed metallised interconnection conductor patterns having connection areas whereby electronic circuits can be attached to the substrate with electrical connections to certain of the connection areas whilst others of the connection areas are available for electrical connections to external circuitry.
12. A substrate for electronic circuits substantially as described with reference to the accompanying drawings.
13. An assembly of electronic integrated circuits mounted on a substrate of substantially insulating semiconductor material, the substrate having formed thereon metallised conductor patterns, whereby the integrated circuits are interconnected, and connection areas whereby it can be electrically connected to a printed circuit or other structure carrying the substrate.
GB8321392A 1983-08-09 1983-08-09 Mounting integrated circuit devices Withdrawn GB2144907A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8321392A GB2144907A (en) 1983-08-09 1983-08-09 Mounting integrated circuit devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8321392A GB2144907A (en) 1983-08-09 1983-08-09 Mounting integrated circuit devices

Publications (2)

Publication Number Publication Date
GB8321392D0 GB8321392D0 (en) 1983-09-07
GB2144907A true GB2144907A (en) 1985-03-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB8321392A Withdrawn GB2144907A (en) 1983-08-09 1983-08-09 Mounting integrated circuit devices

Country Status (1)

Country Link
GB (1) GB2144907A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987004010A1 (en) * 1985-12-20 1987-07-02 Hughes Aircraft Company Chip interface mesa
WO1987006062A1 (en) * 1986-03-27 1987-10-08 Hughes Aircraft Company Inverted chip carrier
WO1988001437A1 (en) * 1986-08-20 1988-02-25 Plessey Overseas Limited Integrated circuit devices
GB2195825A (en) * 1986-09-22 1988-04-13 Motorola Inc Integrated circuit package
FR2618255A1 (en) * 1987-07-14 1989-01-20 Gen Electric PACKAGING BLOCK FOR MOUNTING AND INTERCONNECTING SEMICONDUCTOR CHIPS.
EP0381383A2 (en) * 1989-01-30 1990-08-08 Kabushiki Kaisha Toshiba Semiconductor device having insulating substrate adhered to conductive substrate
FR2647961A1 (en) * 1989-05-30 1990-12-07 Thomson Composants Militaires Multichip electronic circuit, in ceramic housing with interconnection chip
US5075253A (en) * 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
GB2253308A (en) * 1986-09-26 1992-09-02 Gen Electric Co Plc Semiconductor circuit arrangements
DE4222402A1 (en) * 1992-07-08 1994-01-13 Daimler Benz Ag Arrangement for the multiple wiring of multi-chip modules
EP0720232A1 (en) * 1993-09-14 1996-07-03 Kabushiki Kaisha Toshiba Multi-chip module
US7727804B2 (en) 1993-12-17 2010-06-01 The Regents Of The University Of California Method and apparatus for fabricating self-assembling microstructures
CN104952833A (en) * 2014-03-24 2015-09-30 恩智浦有限公司 Integrated circuit arrangement

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1477544A (en) * 1974-08-19 1977-06-22 Ibm Semiconductor assemblies
GB1553065A (en) * 1978-01-28 1979-09-19 Int Computers Ltd Circuit structures including integrated circuits
GB2047466A (en) * 1979-02-24 1980-11-26 Int Computers Ltd Multi level connection networks

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1477544A (en) * 1974-08-19 1977-06-22 Ibm Semiconductor assemblies
GB1553065A (en) * 1978-01-28 1979-09-19 Int Computers Ltd Circuit structures including integrated circuits
GB2047466A (en) * 1979-02-24 1980-11-26 Int Computers Ltd Multi level connection networks

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987004010A1 (en) * 1985-12-20 1987-07-02 Hughes Aircraft Company Chip interface mesa
WO1987006062A1 (en) * 1986-03-27 1987-10-08 Hughes Aircraft Company Inverted chip carrier
WO1988001437A1 (en) * 1986-08-20 1988-02-25 Plessey Overseas Limited Integrated circuit devices
GB2195825A (en) * 1986-09-22 1988-04-13 Motorola Inc Integrated circuit package
GB2195825B (en) * 1986-09-22 1990-01-10 Motorola Inc Integrated circuit package
GB2253308A (en) * 1986-09-26 1992-09-02 Gen Electric Co Plc Semiconductor circuit arrangements
GB2253308B (en) * 1986-09-26 1993-01-20 Gen Electric Co Plc Semiconductor circuit arrangements
FR2618255A1 (en) * 1987-07-14 1989-01-20 Gen Electric PACKAGING BLOCK FOR MOUNTING AND INTERCONNECTING SEMICONDUCTOR CHIPS.
EP0381383A3 (en) * 1989-01-30 1991-04-03 Kabushiki Kaisha Toshiba Semiconductor device having insulating substrate adhered to conductive substrate
US5124783A (en) * 1989-01-30 1992-06-23 Kabushiki Kaisha Toshiba Semiconductor device having insulating substrate adhered to conductive substrate
EP0381383A2 (en) * 1989-01-30 1990-08-08 Kabushiki Kaisha Toshiba Semiconductor device having insulating substrate adhered to conductive substrate
US5075253A (en) * 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
FR2647961A1 (en) * 1989-05-30 1990-12-07 Thomson Composants Militaires Multichip electronic circuit, in ceramic housing with interconnection chip
DE4222402A1 (en) * 1992-07-08 1994-01-13 Daimler Benz Ag Arrangement for the multiple wiring of multi-chip modules
EP0720232A1 (en) * 1993-09-14 1996-07-03 Kabushiki Kaisha Toshiba Multi-chip module
EP0720232A4 (en) * 1993-09-14 1996-11-13 Toshiba Kk Multi-chip module
US7727804B2 (en) 1993-12-17 2010-06-01 The Regents Of The University Of California Method and apparatus for fabricating self-assembling microstructures
CN104952833A (en) * 2014-03-24 2015-09-30 恩智浦有限公司 Integrated circuit arrangement
CN104952833B (en) * 2014-03-24 2018-02-02 安普林荷兰有限公司 IC apparatus

Also Published As

Publication number Publication date
GB8321392D0 (en) 1983-09-07

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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)