GB2195825A - Integrated circuit package - Google Patents

Integrated circuit package Download PDF

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Publication number
GB2195825A
GB2195825A GB08721345A GB8721345A GB2195825A GB 2195825 A GB2195825 A GB 2195825A GB 08721345 A GB08721345 A GB 08721345A GB 8721345 A GB8721345 A GB 8721345A GB 2195825 A GB2195825 A GB 2195825A
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GB
United Kingdom
Prior art keywords
die
die attach
integrated circuit
area
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08721345A
Other versions
GB2195825B (en
GB8721345D0 (en
Inventor
Norman Lee Owens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of GB8721345D0 publication Critical patent/GB8721345D0/en
Publication of GB2195825A publication Critical patent/GB2195825A/en
Application granted granted Critical
Publication of GB2195825B publication Critical patent/GB2195825B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15157—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

Damage caused by excess die attach material 23 is prevented by providing a channel 24 for the excess to flow into. Channel 24 is located about at least a portion of an area 21 where a die 22 is to be attached. <IMAGE>

Description

SPECIFICATION Integrated circuit package Background of the Invention The present invention relates, in general, to integrated circuit (IC) packages and, more particularly, to integrated circuit packages having a channel disposed about a portion of a die attach area.
In typical manufacturing, a die attach material, such as a paste, is first deposited on a package substrate. Next, a die is pressed onto the paste. When this is done, the excess die attach material is forced out from under the die as can be seen in U.S. Patent 4,401,767 issued to Dietz et al. Because of the high viscosity of the die attach material the excess tends to remain near the sides of the die and can run up on top of the die causing damage from shorting and corrosion.
Summary of the Invention Accordingly, it is an object of the present invention to provide an integrated circuit package the overcomes the above deficiencies.
A further object of the present invention is to provide an integrated circuit package that eliminates the problem of excess die attach material accumulating on top of a die.
A particular embodiment of the present invention consists of an integrated circuit package having a channel disposed at least about a portion of the area where the die will be attached. The channel being used to receive any excess die attach material.
Brief Description of the Drawings Figure 1 and 2 are views, cross sectional and top planar, of a prior art integrated circuit package; Figures 3 and 4 are views, cross sectional and top planar, of an integrated circuit package embodying the present invention; Figure 5 is a top planar view of a second embodiment of the present invention; and Figure 6 is a top planar view of a third embodiment of the present invention.
Detailed Description of the Drawings Referring first to the Figs. 1 and 2, views in cross section and top planar, respectively, of a prior art integrated circuit package are shown. Figs. 1 and 2 show a package 10 having a recessed portion 11. In manufacturing, a die bonding material 13 is placed in recessed area 11 and then a die 12 is deposited on material 13. In pressing die 12 onto material 13, an excess portion of material 13 is pushed out from under die 12. As shown in Fig. 2 most of excess material 13 is pushed out along the sides of die 12 as opposed to the corners.
Material 13 is generally made of a paste having a high viscosity because of the bonding requirements. This causes material 13 to have a tendency to remain along the edge of die 12 and, if enough exists, to extend onto the top surface of die 12. This can cause damage to the die thereby destroying a die that the manufacturer has already paid to produce.
Referring now to Figs. 3 and 4, cross sectional and top planar views, respectively, of an integrated circuit package, generally designated 20, embodying the present invention are illustrated. Package 20 consists of a recessed area 21 having a series of channels, or moats, 24 disposed about the periphery of recess 21, in what is sometimes referred to as the dead zone. Channels 24 are placed so as to allow an alternate place for any excess die bonding material to flow. As shown here, an excess die bonding material 23 has been pushed out from under a die 22. Because die bonding material 23 has a lower place to flow, gravity and surface tension will cause material 23 to flow down into channels 24 rather than up the side and on top of die 22.
As shown in Fig. 4, channels 24 are placed in the dead zone along where the sides of die 22 will be disposed. The location of channels 24 was selected because of the location of bonding material build up on the prior art. See Fig. 2.
Also, as shown in Fig. 3, channels 24 are tapered with the top opening being wider than the bottom. In one particular embodiment, the depth of channel 24 would be 0.010 inches with a top width of 0.010 inches and a bottom width of 0.006 inches. The actual dimensions of channel 24 are not critical but are dictated by several variables. First, channel 24 should be large enough to contain any excess material 23. Second, channel 24 should not be so large as to effect the structural integrity of package 20.
The location and size of channels 24 are generally compatible with existing dimensions of packages 20. In packaging an IC, there is a minimum amount of spacing, dead zone, required between the sides of die 22 and walls 25 of package 20. This is usually required to allow access by the bonding tools that place wires from bonding pads on die 22 to bbnding posts on package 20. Therefore, the present invention does not require any additional spacing and is compatible with existing package designs.
Referring now to Fig. 5, a second embodiment of the present invention is illustrated.
Fig. 5 shows a package 20 having a single channel 24. By properly placing die 22 during the die placement procedure, only one channel 24 may be required. By placing side 26 of die 22 at the appropriate height and then rolling die 22 until side 27 is at the desired height, the excess die attach material 23 can be directed out one side of die 22. This allows the problem to be resolved using only one chan new 24.
Referring now to Fig. 6, a third embodiment of the present invention is illustrated. This shows package 20 having a single channel 24 disposed about the periphery of die 22. This would eliminate any problems caused if the flow of die attach material 23 changed such that some of material 23 flowed out at a corner of die 22.
While the invention has been described in conjunction with specific embodiments thereof, it is evident that many alterations, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alterations, modifications and variations in the appended claims.

Claims (5)

1. An integrated circuit package comprising: a die attach area for attaching a die to; and said integrated circuit package defining a channel therein disposed about a portion of said die attach area.
2. The integrated circuit package of claim 1 wherein the channel defined by said integrated circuit package is disposed about the periphery of said die attach area.
3. The integrated circuit package of claim 1 wherein the channel defined by said integrated circuit package is tapered such that a top width is wider than a bottom width.
4. An integrated circuit package comprising: a first recessed area defining a die attach area; a second recessed area defining a dead zone, said dead zone being disposed about said die attach area; and said integrated ciruit packaged defining a channel in said dead zone about a portion of sad die attach area.
5. A method of attaching a die to a package substrate comprising the steps of: providing a package substrate having a die attach area; placing a die attach material on said package substrate in said die attach area; placing a die on said die attach material; presing said die onto said die attach material causing an excess of said die attach material to flow from under said die; and providing a channel in said package substrate for a portion of said excess die attach material to flow into.
5. A method of attaching a die to a package comprising the steps of: providing a package having a die attach area; placing a die attach material on said package in said die attach area; placing a die on said die attach material; pressing said die onto said die attach material causing an excess of said die attach material to flow from under said die; and providing a channel in said package for a portion of said excess die attach material to flow into.
CLAIMS Amendments to the claims have been filed, and have the following effect: Claims 1 to 5 above have been deleted or textually amended.
New or textually amended claims have been filed as follows:
1. An integrated circuit package substrate comprising: a die attach area for attaching a die to; and a channel disposed about a portion of said die attach area for the receipt of an excess of a die attach material.
2. The integrated circuit package substrate of claim 1 wherein the channel is disposed about the periphery of said die attach area.
3. The integrated circuit package substrate of claim 1 wherein the channel is tapered such that a top width is wider than a bottom width.
4. An integrated circuit package substrate comprising: a recessed area having a first portion defining a die attach area, and a second portion defining a dead zone, said dead zone being disposed about said die attach area; and a channel in said dead zone about a portion of said die attach area for the receipt of an excess of a die attach material.
GB8721345A 1986-09-22 1987-09-10 Integrated circuit package Expired - Lifetime GB2195825B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US90953286A 1986-09-22 1986-09-22

Publications (3)

Publication Number Publication Date
GB8721345D0 GB8721345D0 (en) 1987-10-14
GB2195825A true GB2195825A (en) 1988-04-13
GB2195825B GB2195825B (en) 1990-01-10

Family

ID=25427393

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8721345A Expired - Lifetime GB2195825B (en) 1986-09-22 1987-09-10 Integrated circuit package

Country Status (4)

Country Link
KR (1) KR880004563A (en)
GB (1) GB2195825B (en)
HK (1) HK26692A (en)
SG (1) SG21192G (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0375217A1 (en) * 1988-12-19 1990-06-27 Motorola, Inc. Semiconductor package having an outwardly arced die cavity
EP0457260A1 (en) * 1990-05-18 1991-11-21 Fujitsu Limited Semiconductor device having a ceramic package
EP0650658A1 (en) * 1992-07-13 1995-05-03 Olin Corporation Electronic package having controlled epoxy flow
US5543363A (en) * 1992-04-28 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Process for adhesively attaching a semiconductor device to an electrode plate
GB2334375A (en) * 1998-02-17 1999-08-18 Nec Corp Mounting electronic devices on substrates
GB2344690A (en) * 1998-12-09 2000-06-14 Ibm Cavity down ball grid array module
US6235556B1 (en) * 1998-07-06 2001-05-22 Clear Logic, Inc. Method of improving parallelism of a die to package using a modified lead frame
WO2009019091A1 (en) * 2007-08-09 2009-02-12 Robert Bosch Gmbh Unit and production of a unit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB863587A (en) * 1958-03-11 1961-03-22 Pye Ltd Improvements in or relating to junction transistor devices
GB1230620A (en) * 1968-07-26 1971-05-05
GB1376940A (en) * 1970-12-10 1974-12-11 Texas Instruments Inc Panel board circuit systems
GB2144907A (en) * 1983-08-09 1985-03-13 Standard Telephones Cables Ltd Mounting integrated circuit devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB863587A (en) * 1958-03-11 1961-03-22 Pye Ltd Improvements in or relating to junction transistor devices
GB1230620A (en) * 1968-07-26 1971-05-05
GB1376940A (en) * 1970-12-10 1974-12-11 Texas Instruments Inc Panel board circuit systems
GB2144907A (en) * 1983-08-09 1985-03-13 Standard Telephones Cables Ltd Mounting integrated circuit devices

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0375217A1 (en) * 1988-12-19 1990-06-27 Motorola, Inc. Semiconductor package having an outwardly arced die cavity
EP0457260A1 (en) * 1990-05-18 1991-11-21 Fujitsu Limited Semiconductor device having a ceramic package
US5543363A (en) * 1992-04-28 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Process for adhesively attaching a semiconductor device to an electrode plate
EP0650658A1 (en) * 1992-07-13 1995-05-03 Olin Corporation Electronic package having controlled epoxy flow
EP0650658A4 (en) * 1992-07-13 1996-03-13 Olin Corp Electronic package having controlled epoxy flow.
US6101098A (en) * 1998-02-17 2000-08-08 Nec Corporation Structure and method for mounting an electric part
GB2334375A (en) * 1998-02-17 1999-08-18 Nec Corp Mounting electronic devices on substrates
US6239480B1 (en) * 1998-07-06 2001-05-29 Clear Logic, Inc. Modified lead frame for improved parallelism of a die to package
US6235556B1 (en) * 1998-07-06 2001-05-22 Clear Logic, Inc. Method of improving parallelism of a die to package using a modified lead frame
GB2344690A (en) * 1998-12-09 2000-06-14 Ibm Cavity down ball grid array module
US6266251B1 (en) 1998-12-09 2001-07-24 International Business Machines Corporation Cavity-down ball grid array module
WO2009019091A1 (en) * 2007-08-09 2009-02-12 Robert Bosch Gmbh Unit and production of a unit
US8552306B2 (en) 2007-08-09 2013-10-08 Robert Bosch Gmbh Assembly and production of an assembly
US9233436B2 (en) 2007-08-09 2016-01-12 Robert Bosch Gmbh Assembly and production of an assembly

Also Published As

Publication number Publication date
HK26692A (en) 1992-04-16
GB2195825B (en) 1990-01-10
KR880004563A (en) 1988-06-04
GB8721345D0 (en) 1987-10-14
SG21192G (en) 1992-04-16

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PCNP Patent ceased through non-payment of renewal fee

Effective date: 19960910