JP2510708B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2510708B2 JP2510708B2 JP63306336A JP30633688A JP2510708B2 JP 2510708 B2 JP2510708 B2 JP 2510708B2 JP 63306336 A JP63306336 A JP 63306336A JP 30633688 A JP30633688 A JP 30633688A JP 2510708 B2 JP2510708 B2 JP 2510708B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- semiconductor chip
- brazing material
- piece
- terminal piece
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
- H01L2224/37011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、非発光性のダイオード等のように、一つの
非発光性半導体チップに対して二本の外部端子を接続し
たいわゆる二端子型の半導体装置に関するものである。The present invention relates to a so-called two-terminal type in which two external terminals are connected to one non-luminous semiconductor chip, such as a non-luminous diode. The present invention relates to a semiconductor device.
従来における非発光性のダイオード等のような二端子
型半導体装置は、第20図乃至第22図に示すように、一つ
の非発光性半導体チップ１を、金属板に形成された二枚
の外部端子2,3における端子片2a,3aの間に挿入したの
ち、該半導体チップ１におけるＮ極1aの下面に、一方の
外部端子２における端子片2aを、半田等の金属製ろう材
４にて接合する一方、半導体チップ１におけるＰ極1bの
上面に、他方の外部端子３における端子片3aを、同じく
半田等の金属製ろう材５にて接合したのち、その全体を
合成樹脂のモールド部６により密封するように構成して
いることは周知の通りである。A conventional two-terminal type semiconductor device such as a non-emissive diode or the like, as shown in FIGS. 20 to 22, has one non-emissive semiconductor chip 1 and two external parts formed on a metal plate. After being inserted between the terminal pieces 2a and 3a of the terminals 2 and 3, the terminal piece 2a of one of the external terminals 2 is attached to the lower surface of the N pole 1a of the semiconductor chip 1 with a metal brazing material 4 such as solder. On the other hand, while joining, the terminal piece 3a of the other external terminal 3 is joined to the upper surface of the P pole 1b of the semiconductor chip 1 with a brazing material 5 made of metal such as solder, and the whole is molded with a synthetic resin 6a. It is well known that it is configured to be sealed by.
しかし、従来の非発光性の二端子型半導体装置では、
他方の外部端子３における端子片3aを、半導体チップ１
よりも大きい寸法にし、該端子片3aを、半導体チップ１
におけるＰ極1bの上面に対して、半田等の金属製ろう材
５にて接合する構成にしている。However, in the conventional non-emissive two-terminal semiconductor device,
Connect the terminal piece 3a of the other external terminal 3 to the semiconductor chip 1
Larger than that of the semiconductor chip 1
The upper surface of the P electrode 1b is joined with a brazing material 5 made of metal such as solder.
このため、半導体チップ１におけるＰ極1bの上面に対
して端子片3aを、その間に供給したろう材６によって接
合する場合において、溶融したろう材５のうち余剰のろ
う材5aが、前記端子片3aの下面に沿ってＰ極1bの外側の
部位まで広がったのち、半導体チップ１の外側面に沿っ
て垂れ下がる傾向を呈するものであるから、前記の接合
工程中において、溶融ろう材５のうち余剰のろう材5a
が、半導体チップ１においてＰ極1bとＮ極1aとの接合周
囲を被覆する保護膜1cを越えて大きく垂れ下がって、半
導体チップ１におけるＮ極1aに接合すると云う事態が発
生するのであり、前記ろう材５に垂れ下がりによる不良
品の発生率が高いのであった。Therefore, when the terminal piece 3a is joined to the upper surface of the P pole 1b of the semiconductor chip 1 by the brazing material 6 supplied in between, the surplus brazing material 5a of the molten brazing material 5 is Since it spreads along the lower surface of 3a up to the portion outside the P pole 1b and then hangs down along the outer surface of the semiconductor chip 1, the excess of the molten brazing filler metal 5 is present during the joining process. Brazing material 5a
However, there is a situation in which the semiconductor chip 1 droops largely beyond the protective film 1c that covers the periphery of the junction between the P pole 1b and the N pole 1a, and the semiconductor chip 1 is joined to the N pole 1a. The occurrence rate of defective products due to sagging on the material 5 was high.
本発明は、この問題を解消した非発光性半導体装置の
構造を提供するものである。The present invention provides a structure of a non-luminous semiconductor device that solves this problem.
この目的を達成するため「請求項１」は、 「非発光性の半導体チップを、金属板で形成された二
枚の外部端子における端子片の間に挿入し、該半導体チ
ップにおける一方の極の下面に、一方の外部端子におけ
る端子片を、半導体チップにおける他方の極の上面に、
他方の外部端子における端子片を、各々ろう材にて接合
して成る半導体装置において、前記他方の外部端子にお
ける端子片に、この端子片の半導体チップに対する接合
用ろう材を端子片の上面側に盛り上げるための切欠部を
設ける。」 と言う構成にした。To achieve this object, "claim 1" states that "a non-luminous semiconductor chip is inserted between terminal pieces of two external terminals formed of a metal plate, and one of the poles of the semiconductor chip is On the lower surface, the terminal piece of one external terminal, on the upper surface of the other pole of the semiconductor chip,
In a semiconductor device in which the terminal pieces of the other external terminal are respectively joined with a brazing material, the brazing material for joining the semiconductor chip of the terminal piece to the terminal piece of the other external terminal is provided on the upper surface side of the terminal piece. Provide a notch for raising. "
また、「請求項２」は、 「非発光性の半導体チップを、金属板で形成された二
枚の外部端子における端子片の間に挿入し、該半導体チ
ップにおける一方の極の下面に、一方の外部端子におけ
る端子片を、半導体チップにおける他方の極の上面に、
他方の外部端子における端子片を、各々ろう材にて接合
して成る半導体装置において、前記他方の外部端子にお
ける端子片に、この端子片の半導体チップに対する接合
用ろう材を端子片の上面側に盛り上げるための抜き孔を
設ける。」 と言う構成にした。Further, "claim 2" states that "a non-luminous semiconductor chip is inserted between the terminal pieces of two external terminals formed of a metal plate, and one of the poles of the semiconductor chip has a lower surface on one side. The terminal piece of the external terminal of, on the upper surface of the other pole of the semiconductor chip,
In a semiconductor device in which the terminal pieces of the other external terminal are respectively joined with a brazing material, the brazing material for joining the semiconductor chip of the terminal piece to the terminal piece of the other external terminal is provided on the upper surface side of the terminal piece. Provide a hole for raising. "
更にまた、「請求項３」は、 「非発光性の半導体チップを、金属板で形成された二
枚の外部端子における端子片の間に挿入し、該半導体チ
ップにおける一方の極の下面に、一方の外部端子におけ
る端子片を、半導体チップにおける他方の極の上面に、
他方の外部端子における端子片を、各々ろう材にて接合
して成る半導体装置において、前記他方の外部端子にお
ける端子片の幅寸法及び長さ寸法のうちいずれか一方又
は両方を、この端子片の半導体チップに対する接合用ろ
う材を端子片の上面側に盛り上げるように、半導体チッ
プの他方の極における幅寸法及び長さ寸法のうちいずれ
か一方又は両方よりも小さくする。」 と言う構成にした。Still further, "claim 3" states that "a non-luminous semiconductor chip is inserted between terminal pieces of two external terminals formed of a metal plate, and the bottom surface of one pole of the semiconductor chip is The terminal piece in one of the external terminals, on the upper surface of the other pole of the semiconductor chip,
In a semiconductor device in which the terminal pieces of the other external terminal are respectively joined by a brazing material, one or both of the width dimension and the length dimension of the terminal piece of the other external terminal are The brazing material for bonding to the semiconductor chip is made smaller than either one or both of the width dimension and the length dimension at the other pole of the semiconductor chip so that the brazing material is raised on the upper surface side of the terminal piece. "
前記「請求項１」のように構成すると、半導体チップ
における他方の極の上面に対して、他方の外部端子にお
ける端子片を、その間に供給した溶融ろう材によって接
合するに際して、前記溶融ろう材の一部が、他方の外部
端子における端子片に設けた切欠部内の箇所に集まり、
この切欠部より端子片の上面側に盛り上がると言うよう
に、前記溶融ろう材のうち余剰のものを吸収することが
できるから、余剰の溶融ろう材が、半導体チップの外側
面に向って大きく垂れ下がることを、確実に防止でき、
ろう材の垂れ下がりによる不良品の発生率を低減できる
のである。According to the above configuration, when the terminal piece of the other external terminal is joined to the upper surface of the other pole of the semiconductor chip by the molten brazing material supplied in between, the molten brazing material A part gathers in the place in the notch provided in the terminal piece in the other external terminal,
Since the surplus of the molten brazing material can be absorbed, as if it rises from the notch to the upper surface side of the terminal piece, the excessive melting brazing material droops largely toward the outer surface of the semiconductor chip. Can be reliably prevented,
It is possible to reduce the incidence of defective products due to the dropping of the brazing material.
また、前記「請求項２」のように構成した場合にも、
溶融ろう材の一部が、他方の外部端子における端子片に
設けた抜き孔内に集まり、この抜き孔より端子片の上面
側に盛り上がると言うように、前記溶融ろう材のうち余
剰のものを吸収することができるから、余剰の溶融ろう
材が、半導体チップの外側面に向って大きく垂れ下がる
ことを、確実に防止でき、ろう材の垂れ下がりによる不
良品の発生率を低減できるのである。Also, in the case of the configuration as described in "Claim 2",
A part of the molten brazing filler metal gathers in a hole formed in the terminal piece of the other external terminal and rises to the upper surface side of the terminal piece through the hole. Since it can be absorbed, it is possible to reliably prevent the excessive molten brazing material from drooping toward the outer surface of the semiconductor chip, and it is possible to reduce the incidence of defective products due to the drooping of the brazing material.
更にまた、前記「請求項３」のように構成した場合に
も、溶融ろう材の一部が、他方の外部端子における端子
片の上面側に盛り上がると言うように、前記溶融ろう材
のうち余剰のものを吸収することができるから、余剰の
溶融ろう材が、半導体チップの外側面に向って大きく垂
れ下がることを、確実に防止でき、ろう材の垂れ下がり
による不良品の発生率を低減できるのである。Furthermore, even in the case of the construction as in the "claim 3", a part of the molten brazing material rises to the upper surface side of the terminal piece in the other external terminal, so that the surplus of the molten brazing material is generated. Since it is possible to absorb the solder, it is possible to reliably prevent the excess molten brazing material from drooping toward the outer surface of the semiconductor chip, and it is possible to reduce the incidence of defective products due to the sagging of the brazing material. .
以下、本発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図乃至第３図は、前記「請求項１」に対する第１
の実施例を示し、この図において符号１は、Ｎ極1aと、
Ｐ極1bとを有する非発光性の半導体チップを、符号２
は、金属板製の一方の外部端子を、符号３は、同じく金
属板製の他方の外部端子を各々示し、前記一方の外部端
子２には、幅寸法S1及び長さ寸法L1を、前記半導体チッ
プ１における幅寸法Ｓ及び長さ寸法Ｌよりも大きくした
端子片2aが形成され、また、前記他方の外部端子３に
も、幅寸法S2及び長さ寸法L2を、前記半導体チップ１に
おける幅寸法Ｓ及び長さ寸法Ｌよりも大きくした端子片
3aが形成されている。FIG. 1 to FIG. 3 are the first with respect to the “claim 1”.
In this figure, reference numeral 1 is an N pole 1a,
A non-luminous semiconductor chip having a P pole 1b is denoted by reference numeral 2
Is one external terminal made of a metal plate, and reference numeral 3 is the other external terminal also made of a metal plate. The one external terminal 2 has a width dimension S1 and a length dimension L1. A terminal piece 2a larger than the width dimension S and the length dimension L of the chip 1 is formed, and the width dimension S2 and the length dimension L2 of the other external terminal 3 are set to the width dimension of the semiconductor chip 1. Terminal pieces larger than S and length L
3a is formed.
前記半導体チップ１におけるＮ極1aの下面に、前記一
方の外部端子２における端子片2aを、半田等のろう材４
によって接合する。On the lower surface of the N pole 1a of the semiconductor chip 1, the terminal piece 2a of the one external terminal 2 is provided with a brazing material 4 such as solder.
By joining.
一方、前記半導体チップ１におけるＰ極1bの上面に、
前記他方の外部端子３における端子片3aの、同じく半田
等のろう材４によって接合するに際して、前記他方の外
部端子３における端子片3aに、長溝状の切欠部７を設け
る。On the other hand, on the upper surface of the P pole 1b of the semiconductor chip 1,
When the terminal piece 3a of the other external terminal 3 is joined by the brazing material 4 such as solder, the terminal piece 3a of the other external terminal 3 is provided with a long groove-shaped notch 7.
すると、半導体チップ１におけるＰ極1bの上面に対し
て、他方の外部端子３における端子片3aを、その間に供
給した溶融ろう材５によって接合するに際して、前記溶
融ろう材５のうち余剰のろう材5aは、他方の外部端子３
における端子片3aに設けた切欠部７内の箇所に集まり、
この切欠部より端子片3aの上面側に盛り上がると言うよ
うに、余剰の溶融ろう材5aを吸収することができるか
ら、この余剰の溶融ろう材5aが半導体チップ１の外側面
に向って大きく垂て下がることを、確実に防止できる。Then, when the terminal piece 3a of the other external terminal 3 is joined to the upper surface of the P electrode 1b of the semiconductor chip 1 by the molten brazing material 5 supplied therebetween, the excess brazing material of the molten brazing material 5 is used. 5a is the other external terminal 3
Gathered in the notch 7 provided in the terminal piece 3a at
Since the surplus molten brazing material 5a can be absorbed as if it rises from the notch to the upper surface side of the terminal piece 3a, the surplus molten brazing material 5a drastically drops toward the outer surface of the semiconductor chip 1. Can be reliably prevented from falling.
この場合において、他方の外部端子３における端子片
3aに対して設ける切欠部としては、前記実施例のように
長溝状にする場合に限らず、第４図に示すように、端子
片3aのの隅部に対して設けた切欠部7aにしたり、或い
は、第５図に示すように、Ｖ型の切欠部7bに形成する
等、他の形状にしても良いのである。In this case, the terminal piece in the other external terminal 3
The notch provided in 3a is not limited to the long groove shape as in the above-mentioned embodiment, and as shown in FIG. 4, it may be a notch 7a provided in a corner of the terminal piece 3a. Alternatively, as shown in FIG. 5, another shape such as a V-shaped notch 7b may be formed.
次に、第６図及び第７図は、前記「請求項２」に対す
る第１の実施例を示すものであり、この実施例は、前記
非発光性の半導体チップ１におけるＰ極1bの上面に、前
記他方の外部端子３における端子片3aを、半田等のろう
材５によって接合するに際して、前記他方の外部端子３
における端子片3aに、円形の抜き孔８を設けた構成にす
る。Next, FIG. 6 and FIG. 7 show a first embodiment with respect to the “claim 2”, which is formed on the upper surface of the P pole 1 b of the non-emissive semiconductor chip 1. When joining the terminal piece 3a of the other external terminal 3 with the brazing material 5 such as solder, the other external terminal 3
The terminal piece 3a in FIG. 2 is provided with a circular hole 8.
このように、他方の外部端子３における端子片3aに抜
き孔８を設けると、溶融ろう材５のうち余剰のろう材5a
は、前記抜き孔８内に集まり、この抜き孔８より端子片
3aの上面側に盛り上がると言うように、余剰の溶融ろう
材5aを吸収することができるから、この余剰の溶融ろう
材5aが半導体チップ１の外側面に向って大きく垂れ下が
ることを、確実に防止できる。In this way, when the hole 8 is provided in the terminal piece 3a of the other external terminal 3, the surplus brazing material 5a of the molten brazing material 5 is formed.
Are gathered in the hole 8 and the terminal pieces are inserted through the hole 8.
Since the surplus molten brazing material 5a can be absorbed like rising on the upper surface side of 3a, it is possible to reliably prevent the excessive melting brazing material 5a from drooping largely toward the outer surface of the semiconductor chip 1. it can.
この場合において、他方の外部端子３における端子片
3aに対して設ける抜き孔としては、前記実施例のように
円形にする場合に限らず、第８図に示すように矩形の抜
き孔8a、第９図に示すように楕円形の抜き孔8b又は第10
図に示すように十字形の抜き孔8c等、適宜形状の抜き孔
に形成しても良く、また、第11図に示すように複数個の
抜き孔8dに構成しても良いのである。In this case, the terminal piece in the other external terminal 3
The holes provided for 3a are not limited to the circular holes as in the above-described embodiment, but rectangular holes 8a as shown in FIG. 8 and elliptical holes 8b as shown in FIG. Or tenth
As shown in the figure, it may be formed into an appropriately shaped hole such as a cross-shaped hole 8c, or as shown in FIG. 11, it may be formed into a plurality of holes 8d.
更に、第12図及び第13図は、前記「請求項３」に対す
る第１の実施例を示すものであり、この実施例は、前記
非発光性の半導体チップ１におけるＰ極1bの上面に、前
記他方の外部端子３における端子片3aを、半田等のろう
材５によって接合するに際して、前記他方の外部端子３
における端子片3aの長さ寸法S2を、半導体チップ１の長
さよりも小さくする構成にする。Furthermore, FIGS. 12 and 13 show a first embodiment with respect to the “claim 3”, which is arranged on the upper surface of the P pole 1 b in the non-emissive semiconductor chip 1. When the terminal piece 3a of the other external terminal 3 is joined by the brazing material 5 such as solder, the other external terminal 3
The length dimension S2 of the terminal piece 3a at is smaller than the length of the semiconductor chip 1.
このように、他方の外部端子３における端子片3aの長
さ寸法S2を、半導体チップ１の長さよりも小さくする、
溶融ろう材５のうち余剰のろう材5aは、端子片3aは上面
側に盛り上がると言うように、余剰の溶融ろう材5aを余
剰の溶融ろう材5aを吸収することができるから、この余
剰の溶融ろう材5aが、半導体チップ１の外側面に向って
大きく垂れ下がることを、確実に防止できる。Thus, the length dimension S2 of the terminal piece 3a in the other external terminal 3 is made smaller than the length of the semiconductor chip 1,
Since the surplus brazing material 5a of the molten brazing material 5 can absorb the surplus melting brazing material 5a, as the terminal piece 3a rises to the upper surface side, this surplus brazing material 5a can be absorbed. It is possible to reliably prevent the molten brazing material 5a from drooping largely toward the outer surface of the semiconductor chip 1.
この実施例としては、前記第12図及び第13図のよう
に、端子片3aにおける長さ寸法L2を半導体チップ１の長
さよりも小さくすることに代えて、第14図に示すよう
に、端子片3aにおける幅寸法S2を半導体チップ１の幅寸
法よりも小さくしたり、或いは、第15図に示すように、
端子片3aにおける長さ寸法L2を半導体チップ１の長さよ
りも小さくすると共に、端子片3aにおける幅寸法S2を半
導体チップ１の幅寸法よりも小さくするように構成して
も良いのである。In this embodiment, as shown in FIG. 12 and FIG. 13, instead of making the length dimension L2 of the terminal piece 3a smaller than the length of the semiconductor chip 1, as shown in FIG. The width dimension S2 of the piece 3a is made smaller than the width dimension of the semiconductor chip 1, or, as shown in FIG.
The length dimension L2 of the terminal piece 3a may be smaller than the length of the semiconductor chip 1, and the width dimension S2 of the terminal piece 3a may be smaller than the width dimension of the semiconductor chip 1.
なお、これら第12図〜第15図に示す実施例において、
端子片3aにおける長さ寸法L2を短くした場合には、当該
端子片3aにおける先端面3a′に、第16図に示すように切
欠部９を設けたり、又は、端子片3aにおける先端面3a′
を、第17図に示すように波型状に構成することにより、
また、端子片3aにおける幅寸法S2を狭くした場合には、
当該端子片3aにおける側端面3a″に、第18図に示すよう
に切欠部10を設けたり、又は、端子片3aにおける側端面
3a″を、第19図に示すように波型状に構成することによ
り、端子片3aに対するろう材５の接合面積の増大、延い
ては、端子片3aの半導体チップ１に対する接合力の増大
を図ることができる。In the examples shown in FIGS. 12 to 15,
When the length L2 of the terminal piece 3a is shortened, the tip surface 3a 'of the terminal piece 3a is provided with a notch 9 as shown in FIG. 16, or the tip surface 3a' of the terminal piece 3a is formed.
By configuring the wave shape as shown in FIG.
When the width S2 of the terminal piece 3a is narrowed,
The side end surface 3a ″ of the terminal piece 3a is provided with a notch 10 as shown in FIG. 18, or the side end surface of the terminal piece 3a is formed.
By constructing 3a ″ in a corrugated shape as shown in FIG. 19, it is possible to increase the bonding area of the brazing material 5 to the terminal piece 3a, and thus increase the bonding force of the terminal piece 3a to the semiconductor chip 1. Can be planned.
第１図〜第３図は請求項１に対する実施例を示し、第１
図は縦断正面図、第２図は第１図の底面図、第３図は第
１図の平面図、第４図及び第５図は請求項１に対する他
の実施例を示す平面図、第６図は請求項２に対する実施
例を示す縦断正面図、第７図は第６図の平面図、第８
図，第９図，第10図及び第11図は請求項２に対する他の
実施例を示す平面図、第12図は請求項３に対する実施例
をを示す縦断正面図、第13図は第12図の平面図、第14
図，第15図，第16図，第17図，第18図及び第19図は請求
項３に対する他の実施例を示す平面図、第20図は従来の
ダイオードの縦断正面図、第21図は第20図の底面図、第
22図は第20図の平面図である。 １……半導体チップ、1a……半導体チップにおけるＮ
極、1b……半導体チップにおけるＰ極、２……一方の外
部端子、2a……一方の外部端子における端子片、３……
他方の外部端子、3a……他方の外部端子における端子
片、4,5……ろう材、６……モールド部、7,7a,7b……切
欠部、8,8a,8b,8c,8d……抜き孔、 L2……他方の外部端子における端子片の長さ寸法、S2…
…他方の外部端子における端子片の幅寸法。1 to 3 show an embodiment for claim 1 and
FIG. 2 is a vertical front view, FIG. 2 is a bottom view of FIG. 1, FIG. 3 is a plan view of FIG. 1, and FIGS. 4 and 5 are plan views showing another embodiment for claim 1. 6 is a vertical sectional front view showing an embodiment for claim 2, FIG. 7 is a plan view of FIG. 6, and FIG.
FIG. 9, FIG. 10, FIG. 10 and FIG. 11 are plan views showing another embodiment for claim 2, FIG. 12 is a vertical sectional front view showing an embodiment for claim 3, and FIG. Figure top view, 14th
FIG. 15, FIG. 16, FIG. 16, FIG. 17, FIG. 18 and FIG. 19 are plan views showing another embodiment for claim 3, and FIG. 20 is a vertical sectional front view of a conventional diode. Is the bottom view of Fig. 20,
FIG. 22 is a plan view of FIG. 1 ... Semiconductor chip, 1a ... N in semiconductor chip
Pole, 1b ... P pole on semiconductor chip, 2 ... one external terminal, 2a ... terminal piece on one external terminal, 3 ...
Other external terminal, 3a ... Terminal piece in the other external terminal, 4,5 ... Brazed material, 6 ... Molded portion, 7,7a, 7b ... Notched portion, 8,8a, 8b, 8c, 8d ... … Drilling hole, L2 …… Length of terminal piece on the other external terminal, S2…
... Width dimension of the terminal piece on the other external terminal.
Claims (3)
された二枚の外部端子における端子片の間に挿入し、該
半導体チップにおける一方の極の下面に、一方の外部端
子における端子片を、半導体チップにおける他方の極の
上面に、他方の外部端子における端子片を、各々ろう材
にて接合して成る半導体装置において、前記他方の外部
端子における端子片に、この端子片の半導体チップに対
する接合用ろう材を端子片の上面側に盛り上げるための
切欠部を設けたことを特徴とする半導体装置。1. A non-luminous semiconductor chip is inserted between terminal pieces of two external terminals formed of a metal plate, and a terminal of one external terminal is provided on the lower surface of one pole of the semiconductor chip. In a semiconductor device in which a piece is joined to the upper surface of the other pole of the semiconductor chip and the terminal piece of the other external terminal by a brazing material, the semiconductor of this terminal piece is connected to the terminal piece of the other external terminal. A semiconductor device having a notch for raising a brazing filler metal for a chip to the upper surface side of a terminal piece.
された二枚の外部端子における端子片の間に挿入し、該
半導体チップにおける一方の極の下面に、一方の外部端
子における端子片を、半導体チップにおける他方の極の
上面に、他方の外部端子における端子片を、各々ろう材
にて接合して成る半導体装置において、前記他方の外部
端子における端子片に、この端子片の半導体チップに対
する接合用ろう材を端子片の上面側に盛り上げるための
抜き孔を設けたことを特徴とする半導体装置。2. A non-luminous semiconductor chip is inserted between terminal pieces of two external terminals formed of a metal plate, and a terminal of one external terminal is placed on the lower surface of one pole of the semiconductor chip. In a semiconductor device in which a piece is joined to the upper surface of the other pole of the semiconductor chip and the terminal piece of the other external terminal by a brazing material, the semiconductor of this terminal piece is connected to the terminal piece of the other external terminal. A semiconductor device having a hole for raising a brazing filler metal for a chip to the upper surface side of a terminal piece.
された二枚の外部端子における端子片の間に挿入し、該
半導体チップにおける一方の極の下面に、一方の外部端
子における端子片を、半導体チップにおける他方の極の
上面に、他方の外部端子における端子片を、各々ろう材
にて接合して成る半導体装置において、前記他方の外部
端子における端子片の幅寸法及び長さ寸法のうちいずれ
か一方又は両方を、この端子片の半導体チップに対する
接合用ろう材を端子片の上面側に盛り上げるように、半
導体チップの他方の極における幅寸法及び長さ寸法のう
ちいずれか一方又は両方よりも小さくしたことを特徴と
する半導体装置。3. A non-light emitting semiconductor chip is inserted between terminal pieces of two external terminals formed of a metal plate, and a terminal of one external terminal is placed on the lower surface of one pole of the semiconductor chip. In a semiconductor device in which a terminal piece of the other external terminal is joined to the upper surface of the other pole of the semiconductor chip with a brazing material, the width dimension and the length dimension of the terminal piece of the other external terminal are provided. Either one or both of them, one of the width dimension and the length dimension at the other pole of the semiconductor chip or so that the brazing material for bonding to the semiconductor chip of this terminal piece is raised on the upper surface side of the terminal piece. A semiconductor device characterized by being made smaller than both.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63306336A JP2510708B2 (en) | 1988-12-02 | 1988-12-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63306336A JP2510708B2 (en) | 1988-12-02 | 1988-12-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02152243A JPH02152243A (en) | 1990-06-12 |
| JP2510708B2 true JP2510708B2 (en) | 1996-06-26 |
Family
ID=17955878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63306336A Expired - Fee Related JP2510708B2 (en) | 1988-12-02 | 1988-12-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2510708B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2743876B2 (en) * | 1995-07-18 | 1998-04-22 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP5653974B2 (en) * | 2012-08-01 | 2015-01-14 | ローム株式会社 | Package type two-terminal semiconductor device |
| JP6448418B2 (en) * | 2015-03-09 | 2019-01-09 | 三菱電機株式会社 | Power semiconductor device |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5442019Y2 (en) * | 1974-07-24 | 1979-12-07 | ||
| JPS5130467U (en) * | 1974-08-28 | 1976-03-05 | ||
| JPS5678386U (en) * | 1979-11-13 | 1981-06-25 | ||
| JPS5727167A (en) * | 1980-07-23 | 1982-02-13 | Chuo Hatsumei Kenkyusho:Kk | Painting equipment which has stable discharging amount of slurry |
| JPS58187156U (en) * | 1982-06-08 | 1983-12-12 | 日本電気株式会社 | integrated circuit container |
| JPS5939055A (en) * | 1982-08-26 | 1984-03-03 | Sanken Electric Co Ltd | Manufacture of semiconductor device |
| JPS59158336U (en) * | 1983-04-11 | 1984-10-24 | 日本電気株式会社 | semiconductor equipment |
| JPS6159355U (en) * | 1984-09-21 | 1986-04-21 | ||
| JPS6175553A (en) * | 1984-09-21 | 1986-04-17 | Hitachi Tobu Semiconductor Ltd | Electronic part |
| JPS61102794A (en) * | 1984-10-26 | 1986-05-21 | 三菱電機株式会社 | Terminal unit |
| JPS61115343A (en) * | 1984-11-09 | 1986-06-02 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| JPS61177472U (en) * | 1985-04-24 | 1986-11-05 | ||
| JPS6217176U (en) * | 1985-07-12 | 1987-02-02 |
-
1988
- 1988-12-02 JP JP63306336A patent/JP2510708B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02152243A (en) | 1990-06-12 |
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