JPS59158336U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS59158336U
JPS59158336U JP5371683U JP5371683U JPS59158336U JP S59158336 U JPS59158336 U JP S59158336U JP 5371683 U JP5371683 U JP 5371683U JP 5371683 U JP5371683 U JP 5371683U JP S59158336 U JPS59158336 U JP S59158336U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor device
external lead
bonded
bonded portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5371683U
Other languages
Japanese (ja)
Inventor
野田 利雄
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP5371683U priority Critical patent/JPS59158336U/en
Publication of JPS59158336U publication Critical patent/JPS59158336U/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図aは従来の半導体装置の実装時の斜視図、第1図
すは第1図aの1−1′線における断面図であり、第2
図は本考案実施例による半導体装置を実装した時の斜視
図、第2図すは第2図aのm−m′線における断面図で
ある。 なお図において、1.11・・・・・・外部リード、2
゜12・・・・・・基板の金属配線、3,13・・曲ろ
う材、4.14・・・・・・ICパッケージ、5.15
・・・・・・基板1.16・・・・・・貫通孔、を各々
示す。
FIG. 1a is a perspective view of a conventional semiconductor device when it is mounted, and FIG. 1a is a sectional view taken along line 1-1' of FIG.
The figure is a perspective view of a mounted semiconductor device according to an embodiment of the present invention, and a sectional view taken along the line m-m' in FIG. 2a. In the figure, 1.11...external lead, 2
゜12...Metal wiring on board, 3,13...Bending brazing material, 4.14...IC package, 5.15
. . . Substrate 1.16 . . . Through holes are shown respectively.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部リードを有する半導体装置において、該半導体装置
の実装時に、ろう材により接着される該外部リードと回
斑基板またはICパッケージとの接着部に於いて、該外
部リードの接着部に貫通孔を設けたことを特徴とする半
導体装置。
In a semiconductor device having an external lead, a through hole is provided in the bonded portion of the external lead at the bonded portion of the external lead and the blemish board or IC package that is bonded with a brazing material when the semiconductor device is mounted. A semiconductor device characterized by:
JP5371683U 1983-04-11 1983-04-11 semiconductor equipment Pending JPS59158336U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5371683U JPS59158336U (en) 1983-04-11 1983-04-11 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5371683U JPS59158336U (en) 1983-04-11 1983-04-11 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS59158336U true JPS59158336U (en) 1984-10-24

Family

ID=30184060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5371683U Pending JPS59158336U (en) 1983-04-11 1983-04-11 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS59158336U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02152243A (en) * 1988-12-02 1990-06-12 Rohm Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02152243A (en) * 1988-12-02 1990-06-12 Rohm Co Ltd Semiconductor device

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