JPH02244661A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02244661A
JPH02244661A JP1066573A JP6657389A JPH02244661A JP H02244661 A JPH02244661 A JP H02244661A JP 1066573 A JP1066573 A JP 1066573A JP 6657389 A JP6657389 A JP 6657389A JP H02244661 A JPH02244661 A JP H02244661A
Authority
JP
Japan
Prior art keywords
cap
chip
heat dissipation
semiconductor chip
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1066573A
Other languages
Japanese (ja)
Inventor
Yukinori Sumi
幸典 角
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1066573A priority Critical patent/JPH02244661A/en
Publication of JPH02244661A publication Critical patent/JPH02244661A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To make a semiconductor device of this design uniform in heat dissipation and to reduce it in heat resistance so as to improve it in reliability by a method wherein two or more holes are provided to a cap, the protrusions of a heat dissipating member are fitted to the holes and fusion-welded together, and the heat dissipating member is soldered to the rear of a semiconductor chip. CONSTITUTION:Two or more L-shaped protrusions 16 are provided to a heat dissipating member 15 and fitted to the same L-shaped holes 18 provided to a cap 11, and a soldering material is soldered to the whole face of the protrusions 16, the rear of a semiconductor chip 2, and both the sides of the cap 11 to bond them together. By this process, the member 15 and the chip 2 are bonded together by soldering and soldered faces 18 are coincident with the holes 18 of the cap 11. Therefore, an air layer or oxide is prevented from penetrating into the rear part of the chip 2, so that heat is uniformly dissipated from the rear of the chip 2. The chip 2 and the member 15 are formed into an integral structure pinching the cap 11 between the chip 2 and the member 15, so that the cap 11 is increased in heat dissipation. By this setup, a semiconductor device of this design can be improved in reliability by making it uniform in heat dissipation and low in heat resistance.

Description

【発明の詳細な説明】 [概 要] 表面実装型パッケージにおける放熱部材の取付構造に関
し、 半導体チップからの熱放散を均一にし、熱抵抗を一層低
減させることを目的とし、 表面を下向きにして、パッケージ基板に電気的に接続さ
れた少なくとも1つの半導体チップを有し、該半導体チ
ップの背面に所定形状からなる複数の空孔を設けたキャ
ップを介在させ、該空孔に嵌合する複数の突起部を設け
た放熱部材を前記キャップを挟持して前記半導体チップ
に溶着した構造を具備してなることを特徴とする。
[Detailed Description of the Invention] [Summary] Regarding the mounting structure of a heat dissipation member in a surface mount type package, the purpose is to uniformly dissipate heat from a semiconductor chip and further reduce thermal resistance. A cap including at least one semiconductor chip electrically connected to a package substrate, a cap provided with a plurality of holes having a predetermined shape on the back surface of the semiconductor chip, and a plurality of protrusions fitting into the holes. The present invention is characterized in that it has a structure in which a heat dissipating member provided with a portion is welded to the semiconductor chip with the cap sandwiched therebetween.

(産業上の利用分野〕 本発明は半導体装置のうち、特に表面実装型パッケージ
の放熱部材の取付構造に関する。
(Industrial Field of Application) The present invention relates to a mounting structure for a heat dissipation member of a surface mount type package among semiconductor devices, particularly.

半導体装置が高集積化され、LSIの消費電力が増大す
るに伴って、放熱部材を取付けた表面実装型パッケージ
が増加しており、このような表面実装型パッケージでは
一層の熱抵抗の低下が要望されている。
As semiconductor devices become more highly integrated and the power consumption of LSIs increases, the number of surface mount packages equipped with heat dissipation members is increasing, and there is a demand for further reduction in thermal resistance in such surface mount packages. has been done.

〔従来の技術] 高密度実装するICパッケージにはDIP(Dual 
In1ine Package)タイプ、  P GA
 (Piri Grtd Array)タイプなどのビ
ン挿入タイプ、5OP(SLIIall 0utlin
e Package)タイプ、QFP(口uad Fl
at Package)タイプ、  L CC(Lea
dtess Chip Carri、er)タイプなど
の表面実装タイプが知られているが、これらの高密度実
装パッケージに搭載する半導体チップは主としてフリッ
プチップ、あるいは、タブ方式などのフェースダウン型
半導体チップを収容しており、その際、半導体チップか
らの熱放散を良くする目的で放熱部材を配設し、半導体
チップに発生した熱をチップ背面より放熱部材に伝達し
て、その表面から放熱する構成が採られている。。
[Conventional technology] DIP (Dual
In1ine Package) type, PGA
(Piri Grotd Array) type, etc., 5OP (SLIIall 0utlin)
e Package) type, QFP (mouth uad Fl
at Package) type, L CC (Lea
Although surface mount types such as dtess Chip Carri, er) types are known, the semiconductor chips mounted in these high-density packaging packages are mainly flip chips or face-down type semiconductor chips such as tab type. At that time, a heat dissipation member is provided for the purpose of improving heat dissipation from the semiconductor chip, and a configuration is adopted in which the heat generated in the semiconductor chip is transferred from the back of the chip to the heat dissipation member, and the heat is radiated from the surface. There is. .

このような放熱部材を設けた高密度実装置Cパッケージ
の従来例として、第3図(a)〜(C)にPGAタイプ
の半導体装置を示しており、第3図(a)は断面図、第
3図(b)は放熱部材の斜視図、第3図(C)は同図(
a)のCC断面図である。図中の記号1はキャップ、2
は半導体チップ、3は基板、4はリードビン、5は放熱
部材、6は溶着材である。本図に示す半導体チップ2表
面には多数のバンブ電極7が設けられて、このバンブ電
極7から基板3面に配置した配線に接続し、基板内に作
製した多層配線やビヤホールを通してリードビン4に導
出している。
As a conventional example of a high-density actual device C package provided with such a heat dissipation member, a PGA type semiconductor device is shown in FIGS. FIG. 3(b) is a perspective view of the heat dissipation member, and FIG. 3(C) is the same figure (
It is a CC sectional view of a). Symbol 1 in the diagram is a cap, 2
3 is a semiconductor chip, 3 is a substrate, 4 is a lead bin, 5 is a heat dissipation member, and 6 is a welding material. A large number of bump electrodes 7 are provided on the surface of the semiconductor chip 2 shown in this figure, and these bump electrodes 7 are connected to wiring arranged on the surface of the substrate 3, and are led out to the lead bin 4 through multilayer wiring and via holes made in the substrate. are doing.

放熱部材5は熱伝導性の良いアルミニュムや銅が用いら
れるが、第3図(C)に放熱部材5と半導体チップ2と
の溶着面8を図示しており、図中の中央部分が半導体チ
ップ2の背面で、この全面に溶着材6を溶かして放熱部
材5を接合している。溶着材6は、例えば組成Pb:5
n=9 : 1のPb/Sn合金半田やAu/Sr+共
晶合金半田が用いられ、これら溶着材6の溶融点は約3
00°Cである。
The heat dissipation member 5 is made of aluminum or copper, which has good thermal conductivity. FIG. 2, a heat dissipating member 5 is bonded to the entire surface by melting a welding material 6. The welding material 6 has a composition of Pb:5, for example.
Pb/Sn alloy solder with n=9:1 and Au/Sr+eutectic alloy solder are used, and the melting point of these welding materials 6 is about 3
It is 00°C.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、上記した第3図(C)に示すように、従来の
半導体装置は放熱部材を半導体チップの背面全面に溶着
材6によって溶着させており、接着面が広いために熱伝
導性が良くなる筈であるが、接着面全面を均一に接着さ
せることが困難であって、溶着材の中に空気層が挟まれ
たり、溶着材の溶融時に生じた酸化物が混入したりして
、接着面が広いのが災いして空気層や酸化物の逃げ場が
なく、そのために接着面が不均一になって、半導体装置
の熱抵抗が増加するという問題がある。
By the way, as shown in FIG. 3(C) above, in the conventional semiconductor device, a heat dissipating member is welded to the entire back surface of the semiconductor chip using a welding material 6, and the large bonding surface improves thermal conductivity. However, it is difficult to uniformly bond the entire surface to be bonded, and air spaces may become trapped in the welding material, or oxides generated when the welding material is melted may cause the bonding surface to deteriorate. Unfortunately, the large area leaves no space for air and oxides to escape, resulting in an uneven bonding surface and an increase in the thermal resistance of the semiconductor device.

本発明はこのような重大な問題点を解消させて、半導体
チップから均一な熱放散をおこない、熱抵抗を一層減少
させることを目的とした半導体装置を提案するものであ
る。
The present invention solves these serious problems and proposes a semiconductor device that uniformly dissipates heat from a semiconductor chip and further reduces thermal resistance.

〔課題を解決するための手段〕[Means to solve the problem]

その課題は、第1図および第2図に示す実施例のように
、表面を下向きにして、パッケージ基板に電気的に接続
された少なくとも1つの半導体チップ2を有し、該半導
体チップの背面に所定形状からなる複数の空孔18.2
8を設けたキャップ11゜21を介在させ、該空孔に嵌
合する複数の突起部16゜26を設けた放熱部材25.
26を前記キャップを挟持して前記半導体チップの背面
に溶着した構造を具備した半導体装置によって解決され
る。
The problem is to have at least one semiconductor chip 2 electrically connected to a package substrate with its surface facing downward, as in the embodiment shown in FIGS. A plurality of holes 18.2 having a predetermined shape
A heat dissipating member 25.8 is provided with a cap 11.degree. 21 provided with a plurality of protrusions 16.degree.
26 is solved by a semiconductor device having a structure in which the cap is sandwiched and welded to the back surface of the semiconductor chip.

〔作 用〕[For production]

即ち、本発明は放熱部材の半導体チップ背面に溶着させ
る部分(複数のキャップの空孔からなる部分)を複数個
設けて、その部分に放熱部材の突起部を嵌合させて半導
体チップと放熱部材とを溶着させる。
That is, the present invention provides a plurality of portions of the heat dissipation member to be welded to the back surface of the semiconductor chip (portions consisting of holes of a plurality of caps), and the protrusions of the heat dissipation member are fitted into the portions to weld the semiconductor chip and the heat dissipation member. Weld together.

そうすれば、その溶着部では溶着材を溶融した時に流動
性が増加して空気層や酸化物が浮き上がる状態で除去さ
れ、その突起部での接着性が良くなる。その結果、半導
体チップ背面からの熱放散が均一化され、且つ、このよ
うに構成すると半導体チップとキャップと放熱部材とが
一体化されるためにキャップからの放熱が増加する利点
もある。
By doing so, when the welding material is melted at the welded portion, the fluidity increases and the air layer and oxide are removed in a floating state, improving the adhesion at the protrusion. As a result, heat dissipation from the back surface of the semiconductor chip is made uniform, and with this configuration, the semiconductor chip, the cap, and the heat dissipation member are integrated, so there is an advantage that heat dissipation from the cap is increased.

〔実 施 例] 以下に図面を参照して実施例によって詳細に説明する。〔Example] Examples will be described in detail below with reference to the drawings.

第1図(a)〜(C)は本発明にかかる実施例(1)の
断面図を示しており、第1図(a)は断面図、第1図ら
)は放熱部材の斜視図1第1図(C)は同図(a)のA
A断面図である。図中の記号11はキャップ、15は放
熱部材、16は放熱部材の鍵形突起部で、その他の記号
は第3図と同一部位に同一記号が付けである。
1(a) to 1(C) show cross-sectional views of the embodiment (1) according to the present invention, FIG. 1(a) is a sectional view, and FIG. Figure 1 (C) is A in Figure 1 (a).
It is an A sectional view. In the figure, symbol 11 is a cap, 15 is a heat radiating member, 16 is a key-shaped protrusion of the heat radiating member, and other symbols are the same parts as in FIG. 3 with the same symbols.

即ち、放熱部材15は第1図(b)に示す斜視図によっ
て明らかなように、4個の鍵形突起部16が設けてあり
、この鍵形突起部16をキャップ11に設けた同形状の
複数の空孔に嵌合させ、その突起部の全面および半導体
チップ2背面、キャップ11両面に溶着材6を溶着して
接合する。
That is, as is clear from the perspective view shown in FIG. They are fitted into a plurality of holes, and the welding material 6 is welded to the entire surface of the protrusion, the back surface of the semiconductor chip 2, and both surfaces of the cap 11 to join them.

第1図(C)は放熱部材15と半導体チップ2との4つ
の溶着面18を示しており、この溶着面で溶着材6によ
って半導体チップと放熱部材15とが溶着接合される。
FIG. 1C shows four welding surfaces 18 between the heat dissipating member 15 and the semiconductor chip 2, and the semiconductor chip and the heat dissipating member 15 are welded and joined using the welding material 6 on these welding surfaces.

且つ、この溶着面18がキャップ11の空孔に一致して
いる。
Moreover, this welding surface 18 corresponds to the hole in the cap 11.

かくすれば、少なくとも鍵形突起部16が溶着した半導
体チップの背面部分は空気層や酸化物が噛み込まれるこ
となく、従って、半導体チップの背面からの熱放散が均
一化され易くなる。且つ、キャップを挟持し、半導体チ
ップとキャップと放熱部材とを一体化して溶着している
ために、キャップからの熱放散も増加する。
In this way, at least the back surface portion of the semiconductor chip to which the key-shaped protrusion 16 is welded will not be trapped by an air layer or oxide, and therefore, heat dissipation from the back surface of the semiconductor chip will be more likely to be uniform. Furthermore, since the cap is sandwiched and the semiconductor chip, the cap, and the heat radiating member are integrally welded, heat dissipation from the cap is also increased.

このような形状のキャップ11は空孔を圧延機で打抜き
して容易に形成でき、また、放熱部材15も同じく圧延
機によって整形することができる。
The cap 11 having such a shape can be easily formed by punching holes using a rolling mill, and the heat dissipating member 15 can also be shaped using a rolling mill.

次に、第2図(a)〜(C)は本発明にかかる実施例(
n)の断面図を示しており、第2図(a)は断面図3第
2図(b)は放熱部材の斜視図、第2図(C)は同図(
a)のBB断面図である。図中の記号21はキャップ。
Next, FIGS. 2(a) to (C) show examples (
2(a) is a sectional view of the heat dissipating member, FIG. 2(C) is a perspective view of the heat dissipation member, and FIG.
It is a BB sectional view of a). Symbol 21 in the figure is a cap.

25は放熱部材、26は放熱部材の円形突起部で、その
他の記号は第3図、第1図と同一部位に同一記号が付け
てあり、本例の放熱部材25は第2図(b)に示す斜視
図によって明らかなように、12個の円形突起部26が
設けてあり、この円形突起部26をキャップ21に設け
た同形状の複数の空孔に嵌合させ、その突起部の全面お
よび半導体チップ2背而、キャップ21両面に溶着材6
を溶着する。
25 is a heat dissipation member, 26 is a circular protrusion of the heat dissipation member, and the other symbols are the same parts as in FIG. 3 and FIG. As is clear from the perspective view shown in FIG. And semiconductor chip 2 back, welding material 6 on both sides of cap 21
weld.

第2図(C)は放熱部材25と半導体チップ2との12
個の溶着面28を示しており、この溶着面で溶着材6に
よって半導体チップと放熱部材25とが溶着接合される
が、同様に溶着面2日がキャップ21の相対位置で空孔
になる。
FIG. 2(C) shows 12 parts of the heat dissipating member 25 and the semiconductor chip 2.
A welding surface 28 is shown, on which the semiconductor chip and the heat dissipating member 25 are welded together using the welding material 6, and similarly, the welding surface 2 becomes a hole at the relative position of the cap 21.

このようにすれば、同様に半導体チップの背面からの熱
放散が均一化されて放熱性が改善され、半導体装置の信
頼性向上に繋がる。
In this way, the heat dissipation from the back side of the semiconductor chip is also made uniform, and the heat dissipation performance is improved, leading to improved reliability of the semiconductor device.

上記は2つの実施例について説明したが、その他の種々
の形状をもつ放熱部材を用いた実施例も考えられ、同様
に放熱の均一性が得られるものである。
Although two embodiments have been described above, embodiments using heat dissipating members having various other shapes can also be considered, and uniformity of heat dissipation can be similarly obtained.

(発明の効果) 以上の説明から明らかなように、本発明にかかる半導体
装置によれば、放熱性が改善されて半導体チップから均
一に熱放散され、熱抵抗が一層低下して、その信頼性向
上に大きく寄与するものである。
(Effects of the Invention) As is clear from the above explanation, according to the semiconductor device according to the present invention, the heat dissipation performance is improved and heat is dissipated uniformly from the semiconductor chip, the thermal resistance is further reduced, and the reliability thereof is improved. This greatly contributes to improvement.

示す図、 第3図(a)〜(C)は従来の半導体装置を示す図であ
る。
The figures shown in FIGS. 3(a) to 3(C) are diagrams showing a conventional semiconductor device.

図において、 1、11.21はキャップ、 2は半導体チップ、 3は基板、 4はリードピン、 5、15.25は放熱部材、 6は溶着材、 8、18.28は溶着面(空孔)、 16、26は突起部 を示している。In the figure, 1, 11.21 is the cap, 2 is a semiconductor chip, 3 is the board, 4 is the lead pin, 5, 15.25 is a heat dissipation member, 6 is welding material, 8, 18.28 is the welding surface (hole), 16 and 26 are protrusions It shows.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(C)は本発明にかかる実施例(1)を
示す図、 第2図(a)〜(C)は本発明にかかる実施例(II)
を* ←))−; ノi’ 〉5’jj ゴQ “tr
J (1戸、ty<冥;1阜 11η ギ←ヤ;オ゛〉3豐剰++7 (x)と何)阿$21劇
FIGS. 1(a) to (C) are diagrams showing embodiment (1) according to the present invention, and FIGS. 2(a) to (C) are diagrams showing embodiment (II) according to the present invention.
* ←))−; ノi'〉5'jj goQ “tr
J (1 house, ty<mei; 1 11η gi←ya;

Claims (1)

【特許請求の範囲】[Claims] 表面を下向きにして、パッケージ基板に電気的に接続し
た少なくとも1つの半導体チップ(2)を有し、該半導
体チップの背面に所定形状からなる複数の空孔を設けた
キャップ(11、21)を介在させ、該空孔に嵌合する
複数の突起部(16、26)を設けた放熱部材(15、
25)を前記キャップを挟持して前記半導体チップに溶
着した構造を具備してなることを特徴とする半導体装置
A cap (11, 21) has at least one semiconductor chip (2) electrically connected to a package substrate with the surface facing downward, and a plurality of holes having a predetermined shape are provided on the back surface of the semiconductor chip. A heat dissipation member (15,
25) is welded to the semiconductor chip with the cap sandwiched therebetween.
JP1066573A 1989-03-16 1989-03-16 Semiconductor device Pending JPH02244661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1066573A JPH02244661A (en) 1989-03-16 1989-03-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1066573A JPH02244661A (en) 1989-03-16 1989-03-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02244661A true JPH02244661A (en) 1990-09-28

Family

ID=13319836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1066573A Pending JPH02244661A (en) 1989-03-16 1989-03-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02244661A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04345055A (en) * 1991-05-22 1992-12-01 Nec Corp Lsi chip carrier structure
JP2000289992A (en) * 1999-04-02 2000-10-17 Wako Kogyo Kk Bottom device of screw jack
JP2004071658A (en) * 2002-08-01 2004-03-04 Nec Corp Electronic equipment equipped with chip component and its manufacturing method
EP1734577A1 (en) * 2005-06-16 2006-12-20 ABB Research Ltd Cooling device and semiconductor module with such a cooling device
US20100244237A1 (en) * 2009-03-26 2010-09-30 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04345055A (en) * 1991-05-22 1992-12-01 Nec Corp Lsi chip carrier structure
JP2000289992A (en) * 1999-04-02 2000-10-17 Wako Kogyo Kk Bottom device of screw jack
JP2004071658A (en) * 2002-08-01 2004-03-04 Nec Corp Electronic equipment equipped with chip component and its manufacturing method
US7186928B2 (en) 2002-08-01 2007-03-06 Nec Corporation Electronic device including chip parts and a method for manufacturing the same
EP1734577A1 (en) * 2005-06-16 2006-12-20 ABB Research Ltd Cooling device and semiconductor module with such a cooling device
US20100244237A1 (en) * 2009-03-26 2010-09-30 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
US8338944B2 (en) * 2009-03-26 2012-12-25 Mitsubishi Electric Corporation Semiconductor device, semiconductor module, radiating fin and fitting portions

Similar Documents

Publication Publication Date Title
JP3066579B2 (en) Semiconductor package
US5081067A (en) Ceramic package type semiconductor device and method of assembling the same
US6857470B2 (en) Stacked chip package with heat transfer wires
KR20080083533A (en) Power module with stacked flip-chip and method of fabricating the same power module
JP2001060645A (en) Interposer for mounting semiconductor die on board
US20060164813A1 (en) Semiconductor package and semiconductor module
US20020189853A1 (en) BGA substrate with direct heat dissipating structure
JPH02244661A (en) Semiconductor device
US8253239B2 (en) Multi-chip semiconductor connector
JP2570645B2 (en) Semiconductor device
MXPA96002171A (en) A digital integrated circuit package employing i/o bga (ball grid array) format, and a single ceramic substrate layer with bimetallic technology of filled path.
JP3314574B2 (en) Method for manufacturing semiconductor device
JPS6220701B2 (en)
KR20210001495A (en) Semiconductor package
JPH10256428A (en) Semiconductor package
JPS63190363A (en) Power package
JPH08148647A (en) Semiconductor device
US20230066512A1 (en) Semiconductor device
CN221508171U (en) STOLL double-sided heat dissipation frame, copper sheet and packaging structure
JPS63155734A (en) Method for mounting semiconductor chip
JPH05198708A (en) Semiconductor integrated circuit device
CN211828769U (en) Laminated chip packaging structure
JP2986661B2 (en) Method for manufacturing semiconductor device
JPH11204565A (en) Semiconductor device
JP2653504B2 (en) Semiconductor device