JPH0226243U - - Google Patents

Info

Publication number
JPH0226243U
JPH0226243U JP10509588U JP10509588U JPH0226243U JP H0226243 U JPH0226243 U JP H0226243U JP 10509588 U JP10509588 U JP 10509588U JP 10509588 U JP10509588 U JP 10509588U JP H0226243 U JPH0226243 U JP H0226243U
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding wire
circuit element
insulating substrate
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10509588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10509588U priority Critical patent/JPH0226243U/ja
Publication of JPH0226243U publication Critical patent/JPH0226243U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例を示す拡大断面図
、第２図はその平面図、第３図乃至第６図はこの
考案に用いる回路素子の例を説明するための接続
図、第７図及び第８図はこの考案の変形実施例を
示す断面図、第９図は従来の技術を説明するため
の拡大断面図である。 １：絶縁基板、２：半導体チツプ、３：ヒート
スプレツダ、４：信号導体、５：端子、６：ボン
デングワイヤ、７〜１０：回路素子、１１：共通
電位導体。 FIG. 1 is an enlarged sectional view showing one embodiment of this invention, FIG. 2 is a plan view thereof, FIGS. 3 to 6 are connection diagrams for explaining examples of circuit elements used in this invention, and FIG. 8 and 8 are cross-sectional views showing modified embodiments of this invention, and FIG. 9 is an enlarged cross-sectional view for explaining the conventional technique. 1: Insulating substrate, 2: Semiconductor chip, 3: Heat spreader, 4: Signal conductor, 5: Terminal, 6: Bonding wire, 7 to 10: Circuit element, 11: Common potential conductor.

Claims (1)

【実用新案登録請求の範囲】 高周波用ＩＣを構成する半導体チツプと、この
半導体チツプを支持する絶縁基板との間に、この
絶縁基板の熱伝導率より良い熱伝導率を持つ材質
で形成したヒートスプレツダを介挿し、上記半導
体チツプと上記絶縁基板に設けた信号導体との間
をボンデングワイヤで接続した構造の高周波用Ｉ
Ｃにおいて、 上記ヒートスプレツダのチツプ実装面を絶縁面
とし、この絶縁面に上記ボンデングワイヤの共振
を抑止する回路素子を形成し、半導体チツプと外
部との間を接続するボンデングワイヤの接続路に
上記回路素子を介在させて成る高周波用ＩＣ。[Claim for Utility Model Registration] Between the semiconductor chip that constitutes the high-frequency IC and the insulating substrate that supports this semiconductor chip, there is a A high frequency I with a structure in which a spreader is inserted and a bonding wire is used to connect the semiconductor chip and the signal conductor provided on the insulating substrate.
In C, the chip mounting surface of the heat spreader is an insulating surface, a circuit element for suppressing resonance of the bonding wire is formed on this insulating surface, and the bonding wire is connected between the semiconductor chip and the outside. A high frequency IC comprising the above circuit element interposed in a circuit.
JP10509588U 1988-08-08 1988-08-08 Pending JPH0226243U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10509588U JPH0226243U (en) 1988-08-08 1988-08-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10509588U JPH0226243U (en) 1988-08-08 1988-08-08

Publications (1)

Publication Number Publication Date
JPH0226243U true JPH0226243U (en) 1990-02-21

Family

ID=31337405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10509588U Pending JPH0226243U (en) 1988-08-08 1988-08-08

Country Status (1)

Country Link
JP (1) JPH0226243U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007042738A (en) * 2005-08-01 2007-02-15 Fuji Electric Holdings Co Ltd Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6116539A (en) * 1984-05-14 1986-01-24 ジガビツト・ロジツク・インコ−ポレイテツド High speed integrated circuit contained in package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6116539A (en) * 1984-05-14 1986-01-24 ジガビツト・ロジツク・インコ−ポレイテツド High speed integrated circuit contained in package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007042738A (en) * 2005-08-01 2007-02-15 Fuji Electric Holdings Co Ltd Semiconductor device

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