JP2007042738A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007042738A
JP2007042738A JP2005222793A JP2005222793A JP2007042738A JP 2007042738 A JP2007042738 A JP 2007042738A JP 2005222793 A JP2005222793 A JP 2005222793A JP 2005222793 A JP2005222793 A JP 2005222793A JP 2007042738 A JP2007042738 A JP 2007042738A
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semiconductor chip
connection body
conductive plate
semiconductor device
electrode
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JP4797492B2 (en
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Yuji Iizuka
祐二 飯塚
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which ensures high electric conductivity and a heat transfer property and effectively reduce stress in the surface direction generated in a bonding layer (solder layer) due to a difference in a linear expansion factor between a semiconductor chip and a wiring lead or a substrate, so as to improve the connection reliability of a mounted circuit. <P>SOLUTION: The semiconductor device is provided with a mounted circuit which is formed by mounting a semiconductor chip 3 to an insulating substrate 2, and connecting a wiring lead 8 as a wiring member to the upper surface main electrode of a semiconductor chip. In this case, a connection body 7 has such a structure that a conductive plate 7a made of a material with a low linear expansion factor (e.g. 42 alloy) as an electrically conductive and a heat transfer route member, and a columnar post electrode 7b made of a high electrically conductive and high heat transferring material (e.g. pure copper) are scattered, and penetrated and erected on the upper main electrode surface of the semiconductor chip and the surface of the conductive plate, respectively. The connection body 7 is bonded by soldering, and the wiring lead is connected to the post electrode on the rear surface side of the connection body. As a result, high electrical conduction and a heat transfer property can be ensured, and the mismatch of a linear expansion factor to the semiconductor chip can be reduced and stress generated in a solder layer 6 can be also reduced, resulting in improving the connection reliability of a module. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、パワー半導体モジュール，スイッチングＩＣなどを対象とする半導体装置、詳しくは半導体装置に搭載した半導体チップの実装回路構造に関する。   The present invention relates to a semiconductor device intended for a power semiconductor module, a switching IC, and the like, and more particularly to a mounting circuit structure of a semiconductor chip mounted on the semiconductor device.

昨今ではパワー半導体モジュールの小型，大容量化が進み、これに伴いパワー半導体モジュールに搭載するパワー半導体チップ（例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor））等は高い電流密度で通電使用されることから、その放熱対策が重要課題となっている。
すなわち、ＩＧＢＴなどのパワー半導体デバイスでは、半導体チップの接合部温度Ｔjに上限保証温度（例えば１２５℃）が規定されているのに対して、放熱用ベース（銅ベース板）に絶縁基板を介して半導体チップをマウントした片面冷却方式では、半導体チップの上面側がパッケージ内に充填した封止樹脂で封止されているためにチップの上面側からの放熱は殆ど期待できない。このために半導体チップの小型,大電流化に伴い発熱密度が増大すると、半導体チップの上面電極に接続する配線リードとしてアルミワイヤをボンディングした在来の配線構造では、チップの接合部温度を上限保証温度以下に抑えることが困難であるばかりか、アルミワイヤのジュール発熱も加わってワイヤ溶断のおそれもあってヒートサイクル，パワーサイクル耐量の低下が懸念される。 In recent years, power semiconductor modules have become smaller and larger in capacity, and accordingly, power semiconductor chips (for example, IGBT (Insulated Gate Bipolar Transistor)) mounted on the power semiconductor modules are energized and used at a high current density. The heat dissipation countermeasure has become an important issue.
That is, in a power semiconductor device such as an IGBT, an upper limit guaranteed temperature (for example, 125 ° C.) is defined for the junction temperature Tj of the semiconductor chip, whereas the heat dissipation base (copper base plate) is interposed via an insulating substrate. In the single-sided cooling method in which the semiconductor chip is mounted, the upper surface side of the semiconductor chip is sealed with the sealing resin filled in the package, so that heat radiation from the upper surface side of the chip can hardly be expected. For this reason, when the heat generation density increases as the semiconductor chip becomes smaller and the current increases, the upper limit of the chip junction temperature is guaranteed in the conventional wiring structure in which an aluminum wire is bonded as the wiring lead connected to the upper electrode of the semiconductor chip. Not only is it difficult to keep it below the temperature, but there is also a concern that the heat cycle and power cycle resistance may be reduced due to the possibility of wire fusing due to the Joule heat generation of the aluminum wire.

一方、半導体チップの上面からの放熱性を高めるための手段として、前記のアルミワイヤに代えてストラップ状の金属箔になる配線リードを半導体チップの上面主電極に半田接合し、この金属箔を伝熱経路として半導体チップの発生熱をチップ上面側から絶縁基板に放熱させるようにした構成のものが知られており（例えば、特許文献１参照）、さらに配線リードを高伝熱性材質の平板ないしブロック状のリードフレームで構成し、該リードフレーム自身をヒートスプレッダとして半導体チップの発熱集中を緩和させるようにした構成のものも知られている（例えば、特許文献２参照）。なお、配線部材として前記リードフレームを配線用基板に置き換え、半導体チップ３の上下両主面を基板に接合したパッケージ形態の半導体モジュールもある。
次に、パワー半導体モジュールを例に、特許文献２に開示されているモジュール組立構造を図７に示す。図において、１は放熱用銅ベース、２はセラミックス基板２ａの表，裏両面に導体パターン２ｂ，２ｃを形成して銅ベース１の上に搭載接合した絶縁基板（例えば、Direct Copper Bonding基板）、３は絶縁基板２の導体パターン２ｂに半田接合してマウントした半導体チップ(ＩＧＢＴ)、４は半導体チップ３の上面電極（エミッタ電極）と絶縁基板２の導体パターン２ａとの間に半田接合したリードフレーム（銅製の配線リード）、５は外囲樹脂ケースである。なお、１ａは銅ベース１に伝熱結合した放熱フィン（ヒートシンク）である。 On the other hand, as a means for improving the heat dissipation from the upper surface of the semiconductor chip, a wiring lead that becomes a strap-like metal foil instead of the aluminum wire is soldered to the upper main electrode of the semiconductor chip, and this metal foil is transmitted. As a heat path, a structure in which heat generated by a semiconductor chip is radiated from an upper surface side of the chip to an insulating substrate is known (see, for example, Patent Document 1), and a wiring lead is a flat plate or block made of a highly heat conductive material. There is also known a configuration in which the lead frame itself is used as a heat spreader to reduce concentration of heat generation of the semiconductor chip (see, for example, Patent Document 2). There is also a package-type semiconductor module in which the lead frame is replaced with a wiring substrate as a wiring member, and the upper and lower main surfaces of the semiconductor chip 3 are bonded to the substrate.
Next, a module assembly structure disclosed in Patent Document 2 is shown in FIG. 7 taking a power semiconductor module as an example. In the figure, 1 is a heat-dissipating copper base, 2 is an insulating substrate (for example, a Direct Copper Bonding substrate) in which conductor patterns 2b and 2c are formed on the front and back surfaces of the ceramic substrate 2a and mounted on the copper base 1. 3 is a semiconductor chip (IGBT) mounted by solder bonding to the conductor pattern 2 b of the insulating substrate 2, and 4 is a lead solder-bonded between the upper surface electrode (emitter electrode) of the semiconductor chip 3 and the conductor pattern 2 a of the insulating substrate 2. Frames (copper lead wires) 5 are enclosing resin cases. In addition, 1a is a radiation fin (heat sink) thermally coupled to the copper base 1.

ところで、前記のように半導体チップ３の主面にリードフレーム４の接合端面を重ね合わせて両者の間を半田接合（面接合）した実装回路では、半導体チップ３とリードフレーム４との線膨張係数差から、通電時のヒートサイクルにより半田接合層に発生する熱応力がその接合面方向に剪断応力として繰り返し作用し、この応力による疲労で半田層にクラックが発生するなどの欠陥が生じて半導体モジュールの接続信頼性が低下する問題がある。また、同様な応力問題は絶縁基板２の導体パターン２ａに半導体チップ３を接合した半田層にも起こり得る。
一方、前記した半田層の熱応力緩和対策として、半導体チップの主面に半田よりもヤング率が低い樹脂緩衝層と、該緩衝層を貫通して分散配備したポスト電極とを組合せた応力緩和層を半導体チップの主面電極に積層した上でその上面に配線リードを半田接合し、半導体チップと配線リードとの熱膨張係数差に起因して半田層に発生する応力を前記の樹脂緩衝層の変形により吸収して応力を緩和するようにした半導体チップの実装回路構造が知られている（例えば、特許文献３参照）。
特開２００１−３３２６６４号公報 特開２００５−６４４４１号公報 特開２００３−２３４４４７号公報 By the way, in the mounting circuit in which the joining end face of the lead frame 4 is superposed on the main surface of the semiconductor chip 3 and soldered (surface joining) between the two, as described above, the linear expansion coefficient between the semiconductor chip 3 and the lead frame 4 Due to the difference, the thermal stress generated in the solder joint layer due to the heat cycle during energization repeatedly acts as a shear stress in the direction of the joint surface, resulting in defects such as cracks in the solder layer due to fatigue due to this stress. There is a problem that the connection reliability of the system is lowered. Similar stress problems may also occur in the solder layer in which the semiconductor chip 3 is bonded to the conductor pattern 2a of the insulating substrate 2.
On the other hand, as a measure against thermal stress relaxation of the solder layer described above, a stress relaxation layer in which a resin buffer layer having a Young's modulus lower than that of solder is formed on the main surface of the semiconductor chip and post electrodes dispersed and arranged through the buffer layer Is laminated on the main surface electrode of the semiconductor chip, and a wiring lead is soldered to the upper surface thereof, and the stress generated in the solder layer due to the difference in thermal expansion coefficient between the semiconductor chip and the wiring lead is applied to the resin buffer layer. 2. Description of the Related Art A semiconductor chip mounting circuit structure is known that absorbs stress by deformation to relieve stress (see, for example, Patent Document 3).
JP 2001-332664 A JP 2005-64441 A JP 2003-234447 A

ところで、特許文献３に開示されている応力緩和策は、その応力緩衝部を非導電性の樹脂層で形成し、該樹脂層に分散植設したポスト電極を通じて通電，伝熱を行うようにしていることから、その通電，伝熱経路がポスト電極の部分に制約される。このために、パワー半導体モジュールなどのように通電電流，発熱量の大きな半導体チップへの適用には不向きである。
本発明は上記の点に鑑みなされたものであり、その目的は高い通電性と伝熱性を確保しつつ、半導体チップと配線リードもしくは基板との線膨張係数差が原因で接合層に発生する面方向の応力を効果的に緩和できるようにして実装回路の接続信頼性の向上を図った半導体装置を提供することにある。 By the way, the stress relaxation measure disclosed in Patent Document 3 is such that the stress buffer portion is formed of a non-conductive resin layer, and energization and heat transfer are performed through post electrodes dispersedly implanted in the resin layer. Therefore, the energization and heat transfer paths are restricted to the post electrode portion. For this reason, it is not suitable for application to a semiconductor chip having a large energization current and heat generation such as a power semiconductor module.
The present invention has been made in view of the above points, and the object thereof is a surface generated in a bonding layer due to a difference in coefficient of linear expansion between a semiconductor chip and a wiring lead or a substrate while ensuring high electrical conductivity and heat conductivity. An object of the present invention is to provide a semiconductor device in which the connection reliability of a mounting circuit is improved by effectively reducing the stress in the direction.

上記目的を達成するために、本発明によれば、絶縁基板に半導体チップをマウントした上で、該半導体チップの上面主電極に配線部材として配線リードもしくは配線基板を接続した実装回路になる半導体装置において、
半導体チップの少なくとも一方の主電極面に、応力緩和機能を有する通電，伝熱経路部材として、低線膨張係数の材質になる導電板と、該導電板の板面に高導電，高伝熱性の材質になる柱状のポスト電極を分散して貫通植設した構造の接続体を面接合（例えば半田接合）し、該接続体を介して配線部材ないし絶縁基板に接合するものとし（請求項１）、具体的には次記のような態様で構成することができる。
（１）前記接続体を半導体チップの主面に接合した上で、その導電板の背面に露呈しているポスト電極を配線部材，ないし絶縁基板の導体パターンに接合する（請求項２）。
（２）前記接続体を半導体チップの上面主電極に接合した上で、その導電板から引出し形成した端子部に配線リードを接合する（請求項３）。
（３）前記接続体のポスト電極を中空構造体として水平方向の撓み剛性を低め、接続体の応力緩和機能を高めるようにする（請求項４）。
（４）前記接続体の導電板を断面波形板として水平方向の撓み剛性を低め、接続体としての応力緩和機能を一層高めるようにする（請求項５）。
（５）前記のポスト電極を断面波形になる導電板の山部に配置し、かつポスト電極の挿入深さを導電板の波形高さよりも小に設定して接続体の全面域で接合層の導電抵抗，および伝熱抵抗を平均化させて熱応力を分散させるようにする（請求項６）。
（６）前記の接続体について、その導電板の材質をＦｅ−Ｎｉ系合金，Ｍｏ，Ｗ、もしくはそのいずれかの成分と銅またはアルミを含む低膨張合金とし、ポスト電極の材質は純銅，純アルミ、もしくはＭｏ，Ｗ，またはそのいずれかの成分と銅またはアルミを含む合金として半導体チップと接続体との間で線膨張係数のミスマッチを低く抑えるようにする（請求項７）。 In order to achieve the above object, according to the present invention, a semiconductor device which is a mounting circuit in which a semiconductor chip is mounted on an insulating substrate and then a wiring lead or a wiring substrate is connected as a wiring member to the upper main electrode of the semiconductor chip. In
At least one main electrode surface of the semiconductor chip has a conductive plate made of a material having a low linear expansion coefficient as a current-carrying and heat-transfer path member having a stress relaxation function, and a highly conductive and highly heat-conductive material on the plate surface of the conductive plate. A connection body having a structure in which pillar-shaped post electrodes that are made of material are dispersed and penetrated is surface bonded (for example, solder bonding), and is bonded to a wiring member or an insulating substrate via the connection body (Claim 1). Specifically, it can be configured in the following manner.
(1) After joining the connection body to the main surface of the semiconductor chip, the post electrode exposed on the back surface of the conductive plate is joined to a wiring member or a conductor pattern of an insulating substrate.
(2) After joining the connection body to the upper surface main electrode of the semiconductor chip, a wiring lead is joined to a terminal portion formed by being drawn out from the conductive plate.
(3) The post electrode of the connection body is formed as a hollow structure body to reduce the bending rigidity in the horizontal direction and enhance the stress relaxation function of the connection body (claim 4).
(4) The conductive plate of the connection body is used as a corrugated cross section to reduce the horizontal bending rigidity and further enhance the stress relaxation function as the connection body (claim 5).
(5) The post electrode is disposed on the peak portion of the conductive plate having a corrugated cross section, and the insertion depth of the post electrode is set to be smaller than the corrugated height of the conductive plate so that the bonding layer is formed on the entire surface of the connection body. The conductive resistance and the heat transfer resistance are averaged to disperse the thermal stress (claim 6).
(6) For the connection body, the material of the conductive plate is Fe-Ni alloy, Mo, W, or any component thereof and a low expansion alloy containing copper or aluminum, and the post electrode is pure copper, pure The mismatch of the linear expansion coefficient between the semiconductor chip and the connection body is kept low as an alloy containing aluminum, Mo, W, or any one component thereof and copper or aluminum.

上記のように、低線膨張係数の導電板に高導電，高伝熱性のポスト電極を分散植設して該ポスト電極の相互間を導電板で分離するよう構成した接続体を、通電，伝熱経路部材として半導体チップの主面に接合（例えば、半田接合）することにより、半導体チップとの線膨張係数のミスマッチを低く抑えて前記接合層に発生する応力を低減できるとともに、この接続体自身がヒートスプレッダとしても機能し、半導体チップの発熱温度分布を平均化させることができる。したがって、この接続体を介して半導体チップに配線部材，もしくは基板を接続することで実装回路の接続信頼性が向上する。
しかも、導電板を接続体の接合層に対する応力緩衝部として機能させるようにしたことで、先記の特許文献３に開示されている応力緩和層（応力緩衝部を樹脂層で形成している）と比べて高い通電性と伝熱性を確保することができて通電容量，発熱量の大きなパワー半導体モジュールにも十分に対応可能となる。 As described above, a connection body configured such that post electrodes having high conductivity and high heat conductivity are dispersedly planted on a conductive plate having a low linear expansion coefficient and the post electrodes are separated from each other by the conductive plate is connected to a conductive and conductive material. By bonding (for example, solder bonding) to the main surface of the semiconductor chip as a heat path member, it is possible to reduce the stress generated in the bonding layer by suppressing the mismatch of the linear expansion coefficient with the semiconductor chip, and this connection body itself Functions as a heat spreader and can average the heat generation temperature distribution of the semiconductor chip. Therefore, the connection reliability of the mounting circuit is improved by connecting the wiring member or the substrate to the semiconductor chip via this connection body.
In addition, since the conductive plate is made to function as a stress buffering portion for the bonding layer of the connection body, the stress relaxation layer disclosed in the aforementioned Patent Document 3 (the stress buffering portion is formed of a resin layer). Compared to the above, it is possible to ensure high electrical conductivity and heat conductivity, and it is possible to sufficiently handle power semiconductor modules with large electrical capacity and heat generation.

ここで、前記接続体は、半導体装置のパッケージ形態に合わせてポスト電極，あるいは導電板の端子部を選択して接続相手部材（配線リード，配線基板，絶縁基板）に接合（例えば、ロウ付け）するようにすることで、先記したパワー半導体モジュールのほか、表面実装形デバイスなど各種のパッケージ形態に適用できる。
また、前記接続体の構造について、そのポスト電極を中空構造体，導電板を断面波形板として撓み剛性を低めるようにしたことで、接続体の応力緩和機能をより一層高めることができ、さらに接続体に先記のような材質を選択することにより、接続体の実効的な線膨張係数を半導体チップに近づけて接合層に発生する応力を軽減できる。
また、接続体のポスト電極を断面波形になる導電板の山部に配置し、かつポスト電極の挿入深さを導電板の波形高さよりも小に設定した構成を採用することにより、接続体の接合面全域で接合層の導電抵抗および伝熱抵抗を平均化し、併せて熱応力を分散させることができて接続信頼性がさらに向上する。 Here, the connection body selects a post electrode or a terminal portion of a conductive plate in accordance with the package form of the semiconductor device and joins (for example, brazing) to a connection partner member (wiring lead, wiring board, insulating substrate). By doing so, in addition to the power semiconductor module described above, it can be applied to various package forms such as a surface-mounted device.
In addition, with regard to the structure of the connection body, the post electrode is a hollow structure body and the conductive plate is a cross-sectional corrugated plate so as to reduce the flexural rigidity. By selecting the material as described above for the body, it is possible to reduce the stress generated in the bonding layer by bringing the effective linear expansion coefficient of the connection body closer to the semiconductor chip.
In addition, by adopting a configuration in which the post electrode of the connection body is arranged at the peak portion of the conductive plate having a corrugated cross section and the insertion depth of the post electrode is set smaller than the corrugated height of the conductive plate, The conductive resistance and heat transfer resistance of the bonding layer can be averaged over the entire bonding surface, and thermal stress can be dispersed together, further improving connection reliability.

以下、本発明の実施の形態を図１〜図６に示す実施例に基づいて説明する。なお、実施例の図中で、図７に対応する部材には同じ符号を付してその説明は省略する。   Hereinafter, embodiments of the present invention will be described based on examples shown in FIGS. In addition, in the figure of an Example, the same code | symbol is attached | subjected to the member corresponding to FIG. 7, and the description is abbreviate | omitted.

図１（ａ）〜（ｃ）は、半導体チップ３を絶縁基板２に半田マウントし、該半導体チップ３の上面主電極に配線リード（アルミワイヤ，もしくはリードフレーム）を接続して実装回路を構成したパッケージ形態のパワー半導体モジュールに適用した実施例を示すものであり、図１（ａ）で示すように半導体チップ３の上面主電極（エミッタ電極）には、半田層６に対する応力緩和手段として接続体７（詳細構造は後記する）を半田接合（面接合）した上で、該接続体７に配線リード８を接続するようにしている。
ここで、前記の接続体７は、図１（ｂ），（ｃ）で示すように、半導体チップ３の主面と略同等な外形サイズでその材質が低熱膨張係数である導電板７ａに対し、その板面に例えば打ち抜き加工によって貫通穴７ａ−１を分散開口した上で、この貫通穴７ａ−１に柱状のポスト電極７ｂをその先端が導電板７ａの接合面側に突き出すように圧入して植設した構造になる。また、前記の導電板７ａは、例えば４２アロイ，コバール，インバーなどの低膨張合金（Ｆｅ−Ｎｉ合金）であり、ポスト電極７ｂは導電性，伝熱性の高い純銅で作られている。 1A to 1C, a semiconductor chip 3 is solder-mounted on an insulating substrate 2, and a wiring lead (aluminum wire or lead frame) is connected to the upper main electrode of the semiconductor chip 3 to constitute a mounting circuit. FIG. 1 shows an embodiment applied to a power semiconductor module of the package form, and as shown in FIG. 1A, the upper main electrode (emitter electrode) of the semiconductor chip 3 is connected as stress relaxation means to the solder layer 6. After the body 7 (detailed structure will be described later) is soldered (surface joined), the wiring lead 8 is connected to the connecting body 7.
Here, as shown in FIGS. 1B and 1C, the connection body 7 has an outer size substantially the same as that of the main surface of the semiconductor chip 3 and is made of a material having a low thermal expansion coefficient. The through holes 7a-1 are dispersed and opened on the plate surface by, for example, punching, and a columnar post electrode 7b is press-fitted into the through hole 7a-1 so that the tip protrudes to the joining surface side of the conductive plate 7a. It becomes a planted structure. The conductive plate 7a is made of a low expansion alloy (Fe—Ni alloy) such as 42 alloy, Kovar, or Invar, and the post electrode 7b is made of pure copper having high conductivity and heat conductivity.

そして、図１（ａ）で示すように半導体チップ３の上面主電極に前記接続体７を重ねて半田接合し、この接続体７を通電，伝熱経路部材としてその導電板７ａの背面側に露呈しているポスト電極７ｂに配線リード８をロウ付け，超音波接合などの適宜な接合方法により接合して実装回路を構成している。
上記構成によれば、個々のポスト電極７ｂが導電板７ａの板面上に分離して担持されていることから、接続体７の実質的な線膨張係数は低膨張合金の導電板７ａの線膨張係数となり、これにより半導体チップとの線膨張係数のミスマッチが低減する。したがって、通電時のヒートサイクルに伴い半田層６に発生する応力を低レベルに低減しつつ、一方では導電板７ａ，および該導電板に植設した導電性，伝熱性の高いポスト電極７ｂにより電気的，伝熱的に高い導通機能を確保し、特に通電容量の大きなパワー半導体モジュールの実装回路としてその接続信頼性が向上する。また、接続体７の導電板７ａの板厚を増して熱容量を大きく設定することにより接続体自身がヒートスプレッダとして有効に機能し、半導体チップ３の発熱集中を緩和させることができる。また、半導体チップ３の発熱はチップの中央域に多く発生することから、前記ポスト電極７ｂは導電板７ａに対してその中央範囲での配列ピッチを小さくし、周域では配列ピッチを大きくすればよい。 Then, as shown in FIG. 1 (a), the connection body 7 is overlapped and soldered to the upper surface main electrode of the semiconductor chip 3, and this connection body 7 is used as a current and heat transfer path member on the back side of the conductive plate 7a. A wiring circuit 8 is brazed to the exposed post electrode 7b and bonded by an appropriate bonding method such as ultrasonic bonding to constitute a mounting circuit.
According to the above configuration, since the individual post electrodes 7b are separately carried on the plate surface of the conductive plate 7a, the substantial linear expansion coefficient of the connection body 7 is the line of the conductive plate 7a of the low expansion alloy. This results in an expansion coefficient, which reduces the mismatch of the linear expansion coefficient with the semiconductor chip. Therefore, while the stress generated in the solder layer 6 due to the heat cycle during energization is reduced to a low level, on the other hand, the conductive plate 7a and the post electrode 7b having high conductivity and heat conductivity embedded in the conductive plate As a mounting circuit for a power semiconductor module having a large current carrying capacity, the connection reliability is improved. Further, by increasing the thickness of the conductive plate 7a of the connection body 7 and setting the heat capacity to be large, the connection body itself effectively functions as a heat spreader, and the heat generation concentration of the semiconductor chip 3 can be reduced. In addition, since the heat generation of the semiconductor chip 3 is often generated in the central area of the chip, the post electrode 7b can be reduced in the central pitch with respect to the conductive plate 7a and increased in the peripheral area. Good.

なお、導電板７ａの材質は前記の低膨張合金のほか、Ｍｏ，Ｗ，もしくはＭｏ−Ｃｕ，Ｍｏ−Ａｌ，Ｗ−Ｃｕ，Ｗ−Ａｌなどの合金でもよく、またポスト電極７ｂも純Ｃｕのほか、純Ａｌ，Ｍｏ−Ｃｕ，Ｍｏ−Ａｌ，Ｗ−Ｃｕ，Ｗ−Ａｌの合金を選択してもよい。
次に、前記接続体７に関して、図１の構造を変更したいくつかの改良実施例について述べる。 The material of the conductive plate 7a may be Mo, W, or an alloy such as Mo-Cu, Mo-Al, W-Cu, W-Al, etc. in addition to the low expansion alloy, and the post electrode 7b is also made of pure Cu. In addition, an alloy of pure Al, Mo—Cu, Mo—Al, W—Cu, and W—Al may be selected.
Next, with respect to the connection body 7, some improved embodiments in which the structure of FIG. 1 is changed will be described.

まず、図２は本発明の請求項４に対応する接続体の実施例であり、図1と同様に、例えば打ち抜き加工によって導電板７ａに分散開口した貫通穴に圧入してポスト電極７ｂ’を植設している。このポスト電極７ｂ’は、中空構造のコニック形状体（錐形）として水平方向の撓み剛性を低めるようにしている。これにより、半田層６（図１（ａ）参照）に発生した応力に対してポスト電極７ａが容易に変形して応力を吸収緩和するようになり、接続体７の応力緩和機能が向上する。   First, FIG. 2 shows an embodiment of a connecting body corresponding to claim 4 of the present invention. Like FIG. 1, for example, the post electrode 7b 'is inserted by press-fitting into through holes opened in the conductive plate 7a by punching. Planted. The post electrode 7b 'is a hollow conic body (conical shape) that reduces the flexural rigidity in the horizontal direction. Thereby, the post electrode 7a is easily deformed with respect to the stress generated in the solder layer 6 (see FIG. 1A) to absorb and relax the stress, and the stress relaxation function of the connection body 7 is improved.

図３は本発明の請求項５に対応する接続体の実施例であり、先記実施例１（図１（ｂ），（ｃ）参照）における導電板７ａを図示のような断面波形板７ａ’として水平方向の撓み剛性を低めようにし、実施例２と中空構造のポスト電極と同様に応力緩和機能を高めることができる。なお、平坦な導電板７ａを断面波形板７ａ’に加工するにはプレス加工が好適である。また、このプレス加工工程で同時に貫通穴７ａ−１を板面に分散開口することもできる。
また、この実施例では断面波形の導電板７ａ’に対し、ポスト電極７ｂ”を波形の山部に分散して圧入，植設し、かつ導電板７ａ’を貫通してその半田接合面側に突き出す圧入深さｄを導電板７ａ’の波形高さｈよりも小（ｄ＜ｈ）に設定している。
上記の波形導電板７ａ’およびポスト電極７ｂ”の採用により、接続体７を半導体チップ３の上主面に半田接合した状態（図１（ａ）参照）では、導電性，膨張係数が低い断面波形形導電板７ａ’の谷部範囲に対応する半田層６の厚さに比べて、導電性，膨張係数の高いポスト電極７ｂ”に対応する半田層６の厚さが厚くなる。これにより、接続体７の全面域で半田層６の電気抵抗，伝熱抵抗が平均化されるとともに、熱応力の集中を避けて半田歪みを半田層６の全域に分散させることができる。 FIG. 3 shows an embodiment of a connecting body corresponding to claim 5 of the present invention. The conductive plate 7a in the first embodiment (see FIGS. 1B and 1C) is shown in the cross-sectional corrugated plate 7a as shown. As described above, it is possible to reduce the bending rigidity in the horizontal direction, and the stress relaxation function can be enhanced as in the case of the second embodiment and the hollow structure post electrode. Note that press working is suitable for processing the flat conductive plate 7a into the corrugated plate 7a ′. In addition, the through holes 7a-1 can be dispersed and opened on the plate surface at the same time in this pressing process.
Further, in this embodiment, the post electrode 7b ″ is dispersed and press-fitted and planted on the corrugated peak portion with respect to the corrugated conductive plate 7a ′, and penetrates the conductive plate 7a ′ to the solder joint surface side. The protruding press-in depth d is set smaller than the waveform height h of the conductive plate 7a ′ (d <h).
By adopting the corrugated conductive plate 7a ′ and the post electrode 7b ″, a cross section having a low conductivity and a low expansion coefficient when the connection body 7 is soldered to the upper main surface of the semiconductor chip 3 (see FIG. 1A). Compared with the thickness of the solder layer 6 corresponding to the valley region of the corrugated conductive plate 7a ′, the thickness of the solder layer 6 corresponding to the post electrode 7b ″ having a high conductivity and expansion coefficient is increased. Thereby, the electrical resistance and heat transfer resistance of the solder layer 6 are averaged over the entire area of the connection body 7, and the solder strain can be dispersed throughout the solder layer 6 while avoiding concentration of thermal stress.

ここで、図３に示すポスト電極７ｂ”は一方の端部に鍔状部７ｂ”-1を設けており、このポスト電極７ｂ”を導電板７ａ’の開口穴に圧入する際に前記鍔状部７ｂ”-1を開口穴の縁に突き当ててポスト電極７ｂ”の圧入深さｄを決めるようにしている。また、前記鍔状部７ｂ”-1を配線リード８（図１（ａ）参照）との接続端側に設けることで、配線リード８との接合面積が広くなって確実な接合が得られる。しかも、このポスト電極７ｂ”と配線リード８は膨張係数が近いので、半田接合面６（図１（ａ）参照）に作用する熱応力の影響も小さい。   Here, the post electrode 7b ″ shown in FIG. 3 is provided with a flange portion 7b ″ -1 at one end, and when the post electrode 7b ″ is press-fitted into the opening hole of the conductive plate 7a ′, the flange shape is formed. The portion 7b ″ -1 is abutted against the edge of the opening hole to determine the press-fitting depth d of the post electrode 7b ″. Further, the flange portion 7b ″ -1 is connected to the wiring lead 8 (FIG. 1A). By providing it on the connection end side with respect to the reference), the bonding area with the wiring lead 8 is widened and reliable bonding is obtained. In addition, since the post electrode 7b ″ and the wiring lead 8 have close expansion coefficients, the influence of the thermal stress acting on the solder joint surface 6 (see FIG. 1A) is small.

また、図４は実施例３の応用実施例であり、図３における中実構造のポスト電極７ｂを図２に示した中空構造のポスト電極７ｂに置き換えた構成になる。これにより、実施例３と同様な機能を発揮して応力緩和効果がより一層向上する。   FIG. 4 shows an application example of the third embodiment, in which the solid structure post electrode 7b in FIG. 3 is replaced with the hollow structure post electrode 7b shown in FIG. Thereby, the same function as Example 3 is exhibited and the stress relaxation effect is further improved.

図５は半導体チップ３の上下両主面に図４に示した接続体７を半田接合した上で、該接続体７を介して絶縁基板２および上方の配線基板７に接合したモジュール形態の実施例を示すものであり、この実施例においては、半導体チップ３の上下主面に半田接合した接続体７の導電板７ａからその背面側に露呈しているポスト電極７ｂの端面をそれぞれ絶縁基板２，および配線基板９の導体パターンに突き当ててロウ付けなどにより接合している。
この構成によれば、半導体チップ３の発生熱をその上下両主面に配した接続体７を介して絶縁基板２および配線基板９に放熱してモジュールの放熱性が向上するとともに、半導体チップ３／絶縁基板２および半導体チップ３／配線基板９の間で半田層６に発生する熱応力を接続体７により低減緩和して高い接続信頼性を実現できる。さらに、各基板についても接合前後の応力が低減されることから、基板の品質管理条件も緩和されて製造上での歩留も向上する。 FIG. 5 shows an embodiment of a module configuration in which the connection body 7 shown in FIG. 4 is soldered to both the upper and lower main surfaces of the semiconductor chip 3 and then joined to the insulating substrate 2 and the upper wiring board 7 via the connection body 7. In this embodiment, the end surfaces of the post electrodes 7b exposed from the conductive plate 7a of the connection body 7 soldered to the upper and lower main surfaces of the semiconductor chip 3 on the back side thereof are respectively shown on the insulating substrate 2. , And a conductor pattern of the wiring board 9 and joined by brazing or the like.
According to this configuration, the heat generated by the semiconductor chip 3 is dissipated to the insulating substrate 2 and the wiring substrate 9 via the connecting bodies 7 arranged on the upper and lower main surfaces to improve the heat dissipation of the module, and the semiconductor chip 3 The thermal stress generated in the solder layer 6 between the insulating substrate 2 and the semiconductor chip 3 / wiring substrate 9 can be reduced and relaxed by the connecting body 7 to realize high connection reliability. Furthermore, since the stress before and after bonding is reduced for each substrate, the quality control conditions of the substrate are relaxed and the manufacturing yield is improved.

図６は、図１（ａ）に示したモジュール形態の応用実施例を示すものである。この実施例においては、半導体チップ３の上面主電極に半田接合した接続体７と配線リード８との接続構造に関して、あらかじめ導電板７ａの周縁より上方に引き出した端子部７ｃを形成しておき、モジュールの組立工程で前記端子部７ｃに配線リード８をロウ付け，あるいは超音波接合するようにしている。
この構成においても、図１（ａ）と同様に半田層６に発生する応力を緩和して接続信頼性の高い実装回路を実現できる。
なお、以上述べた各実施例では、半導体チップ３の主面と接続体７とを半田接合した場合について述べたが、半導体チップ３／接続体７の間の接合は半田接合のみに限定されるものではなく、ロウ付けなど他の接合法においても同様な応力低減効果を奏することができる。 FIG. 6 shows an application example of the module form shown in FIG. In this embodiment, with respect to the connection structure between the connection body 7 soldered to the upper surface main electrode of the semiconductor chip 3 and the wiring lead 8, a terminal portion 7c led out above the periphery of the conductive plate 7a is formed in advance. In the module assembling process, the wiring lead 8 is brazed or ultrasonically bonded to the terminal portion 7c.
Also in this configuration, a mounting circuit with high connection reliability can be realized by relieving the stress generated in the solder layer 6 as in FIG.
In each of the above-described embodiments, the case where the main surface of the semiconductor chip 3 and the connection body 7 are joined by soldering has been described. However, the joining between the semiconductor chip 3 and the connection body 7 is limited to solder joining. However, the same stress reduction effect can be obtained in other joining methods such as brazing.

本発明の実施例１に対応する実施例の構成図で、（ａ）は半導体モジュールの組立構造図、（ｂ），（ｃ）はそれぞれ（ａ）における接続体の詳細構造を表す平面図および拡大断面図BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the Example corresponding to Example 1 of this invention, (a) is an assembly structure figure of a semiconductor module, (b), (c) is a top view showing the detailed structure of the connection body in (a), respectively. Enlarged sectional view 本発明の実施例２に対応する接続体の断面図Sectional drawing of the connection body corresponding to Example 2 of this invention 本発明の実施例３に対応する接続体の断面図Sectional drawing of the connection body corresponding to Example 3 of this invention 本発明の実施例４に対応する接続体の断面図Sectional drawing of the connection body corresponding to Example 4 of this invention 本発明の実施例５に対応する半導体モジュールの組立構造図Assembly structure diagram of semiconductor module corresponding to Embodiment 5 of the present invention 本発明の実施例６に対応する半導体モジュールの組立構造図Assembly structure diagram of semiconductor module corresponding to Embodiment 6 of the present invention パワー半導体モジュールを例にした従来例のモジュール組立構造図Module assembly structure diagram of conventional example using power semiconductor module as an example

符号の説明Explanation of symbols

２ 絶縁基板
３ 半導体チップ
６ 半田層
７ 接続体
７ａ 導電板
７ｂ ポスト電極
８ 配線リード
９ 配線基板 2 Insulating substrate 3 Semiconductor chip 6 Solder layer 7 Connector 7a Conductive plate 7b Post electrode 8 Wiring lead 9 Wiring substrate

Claims (7)

絶縁基板に半導体チップをマウントした上で、該半導体チップの上面主電極に配線部材として配線リードもしくは配線基板を接続した実装回路になる半導体装置において、
半導体チップの少なくとも一方の主電極面に、通電，伝熱経路部材として低線膨張係数の導電板に高導電，高伝熱性の柱状ポスト電極を分散して貫通植設した構造の接続体を面接合し、該接続体を介して配線部材ないし絶縁基板に接合したことを特徴とする半導体装置。 In a semiconductor device which becomes a mounting circuit in which a wiring lead or a wiring board is connected as a wiring member to the upper surface main electrode of the semiconductor chip after mounting the semiconductor chip on the insulating substrate.
Interfacing a connection body with a structure in which high-conductivity and high-heat-conductivity post-shaped post electrodes are dispersed in a conductive plate with a low linear expansion coefficient as a current-carrying and heat-transfer path member on at least one main electrode surface of the semiconductor chip. In addition, the semiconductor device is bonded to a wiring member or an insulating substrate through the connection body. 請求項１記載の半導体装置において、半導体チップの主面に接続体を接合した上で、その導電板の背面に露呈しているポスト電極を配線部材，ないし絶縁基板の導体パターンに接合したことを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein after the connection body is bonded to the main surface of the semiconductor chip, the post electrode exposed on the back surface of the conductive plate is bonded to the wiring member or the conductor pattern of the insulating substrate. A featured semiconductor device. 請求項１記載の半導体装置において、半導体チップの上面主電極に接続体を接合した上で、その導電板から引出し形成した端子部に配線リードを接合したことを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein a connection body is bonded to the upper surface main electrode of the semiconductor chip, and a wiring lead is bonded to a terminal portion formed by drawing out from the conductive plate. 請求項１ないし３のいずれかに記載の半導体装置において、接続体のポスト電極が中空構造体になることを特徴とする半導体装置。 4. The semiconductor device according to claim 1, wherein the post electrode of the connection body has a hollow structure. 請求項１ないし４のいずれかに記載の半導体装置置において、接続体の導電板が断面波形板であることを特徴とする半導体装置。 5. The semiconductor device device according to claim 1, wherein the conductive plate of the connection body is a corrugated plate. 請求項５記載の半導体装置において、ポスト電極を断面波形になる導電板の山部に配置し、かつポスト電極の挿入深さを導電板の波形高さよりも小に設定したことを特徴とする半導体装置。 6. The semiconductor device according to claim 5, wherein the post electrode is disposed at a peak portion of the conductive plate having a corrugated cross section, and the insertion depth of the post electrode is set smaller than the corrugated height of the conductive plate. apparatus. 請求項１ないし６のいずれかに記載の半導体装置において、接続体の導電板の材質がＦｅ−Ｎｉ系合金，Ｍｏ，Ｗ、もしくはそのいずれかの成分と銅またはアルミを含む低膨張合金であり、ポスト電極の材質が純銅，純アルミ、もしくはＭｏ，Ｗ，またはそのいずれかの成分と銅またはアルミを含む合金であることを特徴とする半導体装置。 7. The semiconductor device according to claim 1, wherein a material of the conductive plate of the connection body is an Fe—Ni alloy, Mo, W, or any component thereof and a low expansion alloy containing copper or aluminum. A semiconductor device characterized in that the material of the post electrode is pure copper, pure aluminum, or Mo, W, or an alloy containing any component thereof and copper or aluminum.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015045648A1 (en) * 2013-09-30 2015-04-02 富士電機株式会社 Semiconductor device, method for assembling semiconductor device, component for semiconductor devices and unit module
CN109950194A (en) * 2019-04-11 2019-06-28 京东方科技集团股份有限公司 A kind of chip transfer base substrate and chip transfer method
WO2020225097A1 (en) * 2019-05-08 2020-11-12 Danfoss Silicon Power Gmbh Semiconductor module comprising a semiconductor body electrically contected to a shaped metal body, as well as the method of obtaining the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0226243U (en) * 1988-08-08 1990-02-21
JPH0396064U (en) * 1990-01-22 1991-10-01
JPH07273256A (en) * 1994-04-01 1995-10-20 Nippon Steel Corp Semiconductor device and heat spreader for semiconductor device
JPH0964258A (en) * 1995-08-25 1997-03-07 Hitachi Ltd Large power semiconductor device
JP2000349207A (en) * 1999-06-02 2000-12-15 Denso Corp Method and device for mounting semiconductor device
JP2004047598A (en) * 2002-07-10 2004-02-12 Toyota Industries Corp Composite material and connection structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0226243U (en) * 1988-08-08 1990-02-21
JPH0396064U (en) * 1990-01-22 1991-10-01
JPH07273256A (en) * 1994-04-01 1995-10-20 Nippon Steel Corp Semiconductor device and heat spreader for semiconductor device
JPH0964258A (en) * 1995-08-25 1997-03-07 Hitachi Ltd Large power semiconductor device
JP2000349207A (en) * 1999-06-02 2000-12-15 Denso Corp Method and device for mounting semiconductor device
JP2004047598A (en) * 2002-07-10 2004-02-12 Toyota Industries Corp Composite material and connection structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015045648A1 (en) * 2013-09-30 2015-04-02 富士電機株式会社 Semiconductor device, method for assembling semiconductor device, component for semiconductor devices and unit module
CN105122446A (en) * 2013-09-30 2015-12-02 富士电机株式会社 Semiconductor device, method for assembling semiconductor device, component for semiconductor devices and unit module
US20160035646A1 (en) * 2013-09-30 2016-02-04 Fuji Electric Co., Ltd. Semiconductor device, method for assembling semiconductor device, semiconductor device component, and unit module
JPWO2015045648A1 (en) * 2013-09-30 2017-03-09 富士電機株式会社 Semiconductor device, method for assembling semiconductor device, component for semiconductor device, and unit module
US9917031B2 (en) 2013-09-30 2018-03-13 Fuji Electric Co., Ltd. Semiconductor device, and method for assembling semiconductor device
CN109950194A (en) * 2019-04-11 2019-06-28 京东方科技集团股份有限公司 A kind of chip transfer base substrate and chip transfer method
CN109950194B (en) * 2019-04-11 2021-04-16 京东方科技集团股份有限公司 Chip transfer substrate and chip transfer method
WO2020225097A1 (en) * 2019-05-08 2020-11-12 Danfoss Silicon Power Gmbh Semiconductor module comprising a semiconductor body electrically contected to a shaped metal body, as well as the method of obtaining the same

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